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Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IntSyncCrossingSource_n2x1_Registered( // @[Crossing.scala:48:9]
input auto_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_out_1_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_1_0_0 = auto_in_1_0; // @[Crossing.scala:48:9]
wire auto_in_0_0_0 = auto_in_0_0; // @[Crossing.scala:48:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_1_0 = auto_in_1_0_0; // @[Crossing.scala:48:9]
wire nodeIn_0 = auto_in_0_0_0; // @[Crossing.scala:48:9]
wire x1_nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_1_sync_0_0; // @[Crossing.scala:48:9]
wire auto_out_0_sync_0_0; // @[Crossing.scala:48:9]
assign nodeOut_sync_0 = nodeIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_sync_0 = nodeIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:48:9]
assign auto_out_1_sync_0_0 = x1_nodeOut_sync_0; // @[Crossing.scala:48:9]
assign auto_out_1_sync_0 = auto_out_1_sync_0_0; // @[Crossing.scala:48:9]
assign auto_out_0_sync_0 = auto_out_0_sync_0_0; // @[Crossing.scala:48:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_22( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_22 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PermuteSequencer.scala:
package saturn.backend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import saturn.common._
import saturn.insns._
class PermuteSequencer(exu_insns: Seq[VectorInstruction])(implicit p: Parameters) extends PipeSequencer(new PermuteMicroOp)(p) {
def accepts(inst: VectorIssueInst) = {
val needs_mask = inst.vmu && (!inst.vm && inst.mop =/= mopUnit)
val needs_index = inst.vmu && inst.mop(0)
val arith = !inst.vmu && new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, exu_insns.filter(_.props.contains(UsesPermuteSeq.Y)), Nil).matched
needs_mask || needs_index || arith
}
val valid = RegInit(false.B)
val inst = Reg(new BackendIssueInst)
val eidx = Reg(UInt(log2Ceil(maxVLMax).W))
val rvs2_mask = Reg(UInt(egsTotal.W))
val rvm_mask = Reg(UInt(egsPerVReg.W))
val head = Reg(Bool())
val slide_offset = Reg(UInt((1+log2Ceil(maxVLMax)).W))
val slide = !inst.vmu && inst.funct3 =/= OPIVV
val slide_up = !inst.funct6(0)
val rs2 = Mux(inst.rs1_is_rs2, inst.rs1, inst.rs2)
val gatherei16 = inst.funct3 === OPIVV && inst.opif6 === OPIFunct6.rgatherei16
val renvm = inst.renvm
val renv2 = inst.renv2
val incr_eew = Mux(inst.vmu, inst.mem_idx_size,
Mux(gatherei16, 1.U, inst.vconfig.vtype.vsew))
val eff_vl = Mux(slide,
Mux(slide_up, inst.vconfig.vl - slide_offset, min(inst.vconfig.vtype.vlMax, inst.vconfig.vl + slide_offset)),
inst.vconfig.vl
)(log2Ceil(maxVLMax),0)
val next_eidx = get_next_eidx(eff_vl, eidx, incr_eew, 0.U, false.B, false.B)
val tail = next_eidx === eff_vl
io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall
when (io.dis.fire) {
val iss_inst = io.dis.bits
val offset = Mux(iss_inst.isOpi, get_max_offset(Mux(iss_inst.funct3(2), iss_inst.rs1_data, iss_inst.imm5)), 1.U)
val slide = !iss_inst.vmu && iss_inst.funct3 =/= OPIVV
val slide_up = !iss_inst.funct6(0)
val slide_start = Mux(slide_up, 0.U, offset)
val vlmax = iss_inst.vconfig.vtype.vlMax
val slide_no_read = Mux(slide_up,
iss_inst.vconfig.vl <= offset,
offset >= vlmax)
valid := Mux(!slide, true.B, !slide_no_read)
inst := iss_inst
eidx := Mux(!slide, iss_inst.vstart, slide_start)
slide_offset := offset
val rs2 = Mux(iss_inst.rs1_is_rs2, iss_inst.rs1, iss_inst.rs2)
val renv2_arch_mask = get_arch_mask(rs2, iss_inst.emul)
rvs2_mask := Mux(iss_inst.renv2, FillInterleaved(egsPerVReg, renv2_arch_mask), 0.U)
rvm_mask := Mux(iss_inst.renvm, ~(0.U(egsPerVReg.W)), 0.U)
head := true.B
} .elsewhen (io.iss.fire) {
valid := !tail
head := false.B
}
io.vat := inst.vat
io.seq_hazard.valid := valid
io.seq_hazard.bits.rintent := hazardMultiply(rvs2_mask | rvm_mask)
io.seq_hazard.bits.wintent := false.B
io.seq_hazard.bits.vat := inst.vat
val vs2_read_oh = Mux(renv2, UIntToOH(io.rvs2.req.bits.eg), 0.U)
val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U)
val raw_hazard = ((vm_read_oh | vs2_read_oh) & io.older_writes) =/= 0.U
val data_hazard = raw_hazard
val oldest = inst.vat === io.vat_head
io.rvs2.req.valid := valid && renv2
io.rvs2.req.bits.eg := getEgId(rs2, eidx, incr_eew, false.B)
io.rvs2.req.bits.oldest := oldest
io.rvm.req.valid := valid && renvm
io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B)
io.rvm.req.bits.oldest := oldest
io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && (!renv2 || io.rvs2.req.ready)
io.iss.bits.renv2 := renv2
io.iss.bits.renvm := renvm
io.iss.bits.rvs2_data := io.rvs2.resp
io.iss.bits.rvs2_eew := incr_eew
io.iss.bits.eidx := eidx
io.iss.bits.vl := eff_vl
io.iss.bits.rvm_data := Mux(renvm, io.rvm.resp, ~(0.U(dLen.W)))
io.iss.bits.vmu := inst.vmu
io.iss.bits.tail := tail
when (io.iss.fire && !tail) {
when (next_is_new_eg(eidx, next_eidx, incr_eew, false.B) && vParams.enableChaining.B) {
rvs2_mask := rvs2_mask & ~vs2_read_oh
}
when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) {
rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg)
}
eidx := next_eidx
}
io.busy := valid
io.head := head
}
File Parameters.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy.{BufferParams}
import saturn.exu._
object VectorParams {
// minParams:
// For a very small area-efficient vector unit with iterative
// and element-wise functional units
def minParams = VectorParams()
// refParams
// For a standard modestly capable small vector unit with
// SIMD functional units
def refParams = minParams.copy(
vlrobEntries = 4,
vlissqEntries = 3,
vsissqEntries = 3,
vxissqEntries = 3,
vatSz = 5,
useSegmentedIMul = true,
doubleBufferSegments = true,
useScalarFPFMA = false,
vrfBanking = 4,
)
// dspParams
// For a wide high-performance vector unit with multi-issue
def dspParams = refParams.copy(
issStructure = VectorIssueStructure.Shared
)
// genParams:
// For a vector unit that performs better on less-optimized
// code sequences
def genParams = dspParams.copy(
issStructure = VectorIssueStructure.Split,
vlifqEntries = 16,
vlrobEntries = 16
)
// multiFMAParams:
// Provides a second sequencer and set of functional units for FMA operations
def multiFMAParams = genParams.copy(
issStructure = VectorIssueStructure.MultiFMA
)
// multiMACParams:
// Provides a second sequencer and set of functional units for integer MAC operations
def multiMACParams = genParams.copy(
issStructure = VectorIssueStructure.MultiMAC
)
// dmaParams:
// For a vector unit that only does memcpys, and no arithmetic
def dmaParams = VectorParams(
vdqEntries = 2,
vliqEntries = 4,
vsiqEntries = 4,
vlifqEntries = 32,
vlrobEntries = 4,
vsifqEntries = 32,
vlissqEntries = 2,
vsissqEntries = 1,
vrfBanking = 1,
useIterativeIMul = true
)
// The parameters below are approximations
// hwaParams
// For a vector unit with limited sequencer slots akin to Hwacha
def hwaParams = genParams.copy(
vatSz = 3, // 8 mseq Entries
vdqEntries = 1,
vlissqEntries = 8,
vsissqEntries = 8,
vxissqEntries = 8,
vpissqEntries = 8,
hwachaLimiter = Some(8), // sequencer slots
)
// lgvParams
// For a vector unit with very long vector lengths
def lgvParams = VectorParams(
vatSz = 5,
vlifqEntries = 32,
vsifqEntries = 32,
vlrobEntries = 32,
vlissqEntries = 8,
vsissqEntries = 8,
vxissqEntries = 8,
vpissqEntries = 8,
useSegmentedIMul = true,
useScalarFPMisc = false,
useScalarFPFMA = false,
vrfBanking = 4,
issStructure = VectorIssueStructure.Split
)
}
case class VXSequencerParams(
name: String,
fus: Seq[FunctionalUnitFactory]
) {
def insns = fus.map(_.insns).flatten
}
case class VXIssuePathParams(
name: String,
depth: Int,
seqs: Seq[VXSequencerParams]
) {
def insns = seqs.map(_.insns).flatten
}
object VXFunctionalUnitGroups {
def integerFUs(idivDoesImul: Boolean = false) = Seq(
IntegerPipeFactory,
ShiftPipeFactory,
BitwisePipeFactory,
IntegerDivideFactory(idivDoesImul),
MaskUnitFactory,
PermuteUnitFactory
)
def integerMAC(pipeDepth: Int, useSegmented: Boolean) = Seq(
IntegerMultiplyFactory(pipeDepth, useSegmented)
)
def allIntegerFUs(idivDoesImul: Boolean, imaDepth: Int, useSegmentedImul: Boolean) = (
integerFUs(idivDoesImul) ++ integerMAC(imaDepth, useSegmentedImul)
)
def sharedFPFMA(pipeDepth: Int) = Seq(
FPFMAFactory(pipeDepth, true)
)
def sharedFPMisc = Seq(
SharedFPMiscFactory
)
def fpFMA(pipeDepth: Int) = Seq(
FPFMAFactory(pipeDepth, false)
)
def fpMisc = Seq(
FPDivSqrtFactory,
FPCmpFactory,
FPConvFactory
)
def allFPFUs(fmaPipeDepth: Int, useScalarFPFMA: Boolean, useScalarFPMisc: Boolean) = (
(if (useScalarFPFMA) sharedFPFMA(fmaPipeDepth) else fpFMA(fmaPipeDepth)) ++
(if (useScalarFPMisc) sharedFPMisc else fpMisc)
)
}
sealed trait VectorIssueStructure {
def generate(params: VectorParams): Seq[VXIssuePathParams]
}
object VectorIssueStructure {
import VXFunctionalUnitGroups._
case object Unified extends VectorIssueStructure {
def generate(params: VectorParams) = {
val fp_int_path = VXIssuePathParams(
name = "fp_int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp_int", (
allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul) ++
allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)
))
)
)
Seq(fp_int_path)
}
}
case object Shared extends VectorIssueStructure {
def generate(params: VectorParams) = {
val fp_int_path = VXIssuePathParams(
name = "fp_int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(fp_int_path)
}
}
case object Split extends VectorIssueStructure {
def generate(params: VectorParams) = {
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(int_path, fp_path)
}
}
case object MultiFMA extends VectorIssueStructure {
def generate(params: VectorParams) = {
require(!params.useScalarFPFMA)
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp0", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)),
VXSequencerParams("fp1", fpFMA(params.fmaPipeDepth))
)
)
Seq(int_path, fp_path)
}
}
case object MultiMAC extends VectorIssueStructure {
def generate(params: VectorParams) = {
require(!params.useIterativeIMul && params.useSegmentedIMul)
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int0", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
VXSequencerParams("int1", integerMAC(params.imaPipeDepth, params.useSegmentedIMul))
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(int_path, fp_path)
}
}
}
case class VectorParams(
// In-order dispatch Queue
vdqEntries: Int = 4,
// Load store instruction queues (in VLSU)
vliqEntries: Int = 4,
vsiqEntries: Int = 4,
// Load store in-flight queues (in VLSU)
vlifqEntries: Int = 8,
vsifqEntries: Int = 16,
vlrobEntries: Int = 2,
// Scatter-gather engine params
vsgPorts: Int = 8,
vsgifqEntries: Int = 4,
vsgBuffers: Int = 3,
// Load/store/execute/permute/maskindex issue queues
vlissqEntries: Int = 0,
vsissqEntries: Int = 0,
vxissqEntries: Int = 0,
vpissqEntries: Int = 0,
dLen: Int = 64,
vatSz: Int = 3,
useSegmentedIMul: Boolean = false,
useScalarFPFMA: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions
useScalarFPMisc: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions
useIterativeIMul: Boolean = false,
fmaPipeDepth: Int = 4,
imaPipeDepth: Int = 3,
// for comparisons only
hazardingMultiplier: Int = 0,
hwachaLimiter: Option[Int] = None,
enableChaining: Boolean = true,
latencyInject: Boolean = false,
enableDAE: Boolean = true,
enableOOO: Boolean = true,
enableScalarVectorAddrDisambiguation: Boolean = true,
doubleBufferSegments: Boolean = false,
vrfBanking: Int = 2,
vrfHiccupBuffer: Boolean = true,
issStructure: VectorIssueStructure = VectorIssueStructure.Unified,
tlBuffer: BufferParams = BufferParams.default,
) {
def supported_ex_insns = issStructure.generate(this).map(_.insns).flatten
}
case object VectorParamsKey extends Field[VectorParams]
trait HasVectorParams extends HasVectorConsts { this: HasCoreParameters =>
implicit val p: Parameters
def vParams: VectorParams = p(VectorParamsKey)
def dLen = vParams.dLen
def dLenB = dLen / 8
def dLenOffBits = log2Ceil(dLenB)
def dmemTagBits = log2Ceil(vParams.vlifqEntries.max(vParams.vsifqEntries))
def sgmemTagBits = log2Ceil(vParams.vsgifqEntries)
def egsPerVReg = vLen / dLen
def egsTotal = (vLen / dLen) * 32
def vrfBankBits = log2Ceil(vParams.vrfBanking)
def lsiqIdBits = log2Ceil(vParams.vliqEntries.max(vParams.vsiqEntries))
val debugIdSz = 16
val nRelease = vParams.issStructure match {
case VectorIssueStructure.Unified => 3
case VectorIssueStructure.Shared | VectorIssueStructure.Split => 4
case VectorIssueStructure.MultiFMA | VectorIssueStructure.MultiMAC => 5
}
def getEgId(vreg: UInt, eidx: UInt, eew: UInt, bitwise: Bool): UInt = {
val base = vreg << log2Ceil(egsPerVReg)
val off = eidx >> Mux(bitwise, log2Ceil(dLen).U, (log2Ceil(dLenB).U - eew))
base +& off
}
def getByteId(vreg: UInt, eidx: UInt, eew: UInt): UInt = {
Cat(getEgId(vreg, eidx, eew, false.B), (eidx << eew)(log2Ceil(dLenB)-1,0))
}
def eewByteMask(eew: UInt) = (0 until (1+log2Ceil(eLen/8))).map { e =>
Mux(e.U === eew, ((1 << (1 << e)) - 1).U, 0.U)
}.reduce(_|_)((eLen/8)-1,0)
def eewBitMask(eew: UInt) = FillInterleaved(8, eewByteMask(eew))
def cqOlder(i0: UInt, i1: UInt, tail: UInt) = (i0 < i1) ^ (i0 < tail) ^ (i1 < tail)
def dLenSplat(in: UInt, eew: UInt) = {
val v = Wire(UInt(64.W))
v := in
Mux1H(UIntToOH(eew), (0 until 4).map { i => Fill(dLenB >> i, v((8<<i)-1,0)) })
}
def sextElem(in: UInt, in_eew: UInt): UInt = VecInit.tabulate(4)( { eew =>
Cat(in((8 << eew)-1), in((8 << eew)-1,0)).asSInt
})(in_eew)(64,0)
def extractElem(in: UInt, in_eew: UInt, eidx: UInt): UInt = {
val bytes = in.asTypeOf(Vec(dLenB, UInt(8.W)))
VecInit.tabulate(4) { eew =>
val elem = if (dLen == 64 && eew == 3) {
in
} else {
VecInit(bytes.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq)(eidx(log2Ceil(dLenB)-1-eew,0))
}
elem((8 << eew)-1,0)
}(in_eew)
}
def maxPosUInt(sew: Int) = Cat(0.U, ~(0.U(((8 << sew)-1).W)))
def minNegUInt(sew: Int) = Cat(1.U, 0.U(((8 << sew)-1).W))
def maxPosSInt(sew: Int) = ((1 << ((8 << sew)-1))-1).S
def minNegSInt(sew: Int) = (-1 << ((8 << sew)-1)).S
def maxPosFPUInt(sew: Int) = {
val expBits = Seq(4, 5, 8, 11)(sew)
val fracBits = (8 << sew) - expBits - 1
Cat(0.U, ~(0.U(expBits.W)), 0.U(fracBits.W))
}
def minNegFPUInt(sew: Int) = {
val expBits = Seq(4, 5, 8, 11)(sew)
val fracBits = (8 << sew) - expBits - 1
Cat(1.U, ~(0.U(expBits.W)), 0.U(fracBits.W))
}
def get_arch_mask(reg: UInt, emul: UInt) = VecInit.tabulate(4)({ lmul =>
FillInterleaved(1 << lmul, UIntToOH(reg >> lmul)((32>>lmul)-1,0))
})(emul)
def log2_up(f: UInt, max: Int) = VecInit.tabulate(max)({nf => log2Ceil(nf+1).U})(f)
def hazardMultiply(mask: UInt): UInt = if (vParams.hazardingMultiplier == 0) { mask } else {
require((1 << vParams.hazardingMultiplier) <= egsTotal)
VecInit(mask.asBools.grouped(1 << vParams.hazardingMultiplier).map { g =>
Fill(1 << vParams.hazardingMultiplier, g.orR)
}.toSeq).asUInt
}
}
File PipeSequencer.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile.{CoreModule}
import saturn.common._
abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val dis = Flipped(Decoupled(new BackendIssueInst))
val dis_stall = Input(Bool()) // used to disable OOO
val seq_hazard = Output(Valid(new SequencerHazard))
val vat = Output(UInt(vParams.vatSz.W))
val vat_head = Input(UInt(vParams.vatSz.W))
val older_writes = Input(UInt(egsTotal.W))
val older_reads = Input(UInt(egsTotal.W))
val busy = Output(Bool())
val head = Output(Bool())
val rvs1 = new VectorReadIO
val rvs2 = new VectorReadIO
val rvd = new VectorReadIO
val rvm = new VectorReadIO
val perm = new Bundle {
val req = Decoupled(new CompactorReq(dLenB))
val data = Input(UInt(dLen.W))
}
val iss = Decoupled(issType)
val acc = Input(Valid(new VectorWrite(dLen)))
})
def accepts(inst: VectorIssueInst): Bool
def min(a: UInt, b: UInt) = Mux(a > b, b, a)
def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0)
def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0)
def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0))
def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = {
val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W)
val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0)
val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0)
Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) })
}
def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = {
val next = Wire(UInt((1+log2Ceil(maxVLMax)).W))
next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask,
eidx +& dLen.U,
(((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen))
))
min(vl, next)
}
def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = {
val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew)
(next_eidx >> offset) =/= (eidx >> offset)
}
io.rvs1.req.valid := false.B
io.rvs1.req.bits := DontCare
io.rvs2.req.valid := false.B
io.rvs2.req.bits := DontCare
io.rvd.req.valid := false.B
io.rvd.req.bits := DontCare
io.rvm.req.valid := false.B
io.rvm.req.bits := DontCare
io.perm.req.valid := false.B
io.perm.req.bits := DontCare
}
| module PermuteSequencer( // @[PermuteSequencer.scala:9:7]
input clock, // @[PermuteSequencer.scala:9:7]
input reset, // @[PermuteSequencer.scala:9:7]
output io_dis_ready, // @[PipeSequencer.scala:11:14]
input io_dis_valid, // @[PipeSequencer.scala:11:14]
input [31:0] io_dis_bits_bits, // @[PipeSequencer.scala:11:14]
input [8:0] io_dis_bits_vconfig_vl, // @[PipeSequencer.scala:11:14]
input [2:0] io_dis_bits_vconfig_vtype_vsew, // @[PipeSequencer.scala:11:14]
input io_dis_bits_vconfig_vtype_vlmul_sign, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_vconfig_vtype_vlmul_mag, // @[PipeSequencer.scala:11:14]
input [7:0] io_dis_bits_vstart, // @[PipeSequencer.scala:11:14]
input [63:0] io_dis_bits_rs1_data, // @[PipeSequencer.scala:11:14]
input [4:0] io_dis_bits_vat, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_emul, // @[PipeSequencer.scala:11:14]
input io_dis_bits_rs1_is_rs2, // @[PipeSequencer.scala:11:14]
input io_dis_bits_renv2, // @[PipeSequencer.scala:11:14]
input io_dis_bits_renvm, // @[PipeSequencer.scala:11:14]
output io_seq_hazard_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_seq_hazard_bits_vat, // @[PipeSequencer.scala:11:14]
output [63:0] io_seq_hazard_bits_rintent, // @[PipeSequencer.scala:11:14]
output [4:0] io_vat, // @[PipeSequencer.scala:11:14]
input [4:0] io_vat_head, // @[PipeSequencer.scala:11:14]
input [63:0] io_older_writes, // @[PipeSequencer.scala:11:14]
output io_busy, // @[PipeSequencer.scala:11:14]
input io_rvs2_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvs2_req_valid, // @[PipeSequencer.scala:11:14]
output [5:0] io_rvs2_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvs2_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [127:0] io_rvs2_resp, // @[PipeSequencer.scala:11:14]
input io_rvm_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvm_req_valid, // @[PipeSequencer.scala:11:14]
output [5:0] io_rvm_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvm_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [127:0] io_rvm_resp, // @[PipeSequencer.scala:11:14]
input io_iss_ready, // @[PipeSequencer.scala:11:14]
output io_iss_valid, // @[PipeSequencer.scala:11:14]
output io_iss_bits_renv2, // @[PipeSequencer.scala:11:14]
output io_iss_bits_renvm, // @[PipeSequencer.scala:11:14]
output [127:0] io_iss_bits_rvs2_data, // @[PipeSequencer.scala:11:14]
output [7:0] io_iss_bits_eidx, // @[PipeSequencer.scala:11:14]
output [1:0] io_iss_bits_rvs2_eew, // @[PipeSequencer.scala:11:14]
output [127:0] io_iss_bits_rvm_data, // @[PipeSequencer.scala:11:14]
output io_iss_bits_vmu, // @[PipeSequencer.scala:11:14]
output [8:0] io_iss_bits_vl, // @[PipeSequencer.scala:11:14]
output io_iss_bits_tail // @[PipeSequencer.scala:11:14]
);
wire io_iss_valid_0; // @[PermuteSequencer.scala:88:{25,41,73}]
wire _eidx_7; // @[Parameters.scala:343:{20,26}]
wire [5:0] _io_rvs2_req_bits_eg_T; // @[Parameters.scala:344:10]
reg valid; // @[PermuteSequencer.scala:17:22]
reg [31:0] inst_bits; // @[PermuteSequencer.scala:18:18]
reg [8:0] inst_vconfig_vl; // @[PermuteSequencer.scala:18:18]
reg [2:0] inst_vconfig_vtype_vsew; // @[PermuteSequencer.scala:18:18]
reg inst_vconfig_vtype_vlmul_sign; // @[PermuteSequencer.scala:18:18]
reg [1:0] inst_vconfig_vtype_vlmul_mag; // @[PermuteSequencer.scala:18:18]
reg [4:0] inst_vat; // @[PermuteSequencer.scala:18:18]
reg inst_rs1_is_rs2; // @[PermuteSequencer.scala:18:18]
reg inst_renv2; // @[PermuteSequencer.scala:18:18]
reg inst_renvm; // @[PermuteSequencer.scala:18:18]
reg [7:0] eidx; // @[PermuteSequencer.scala:19:18]
reg [63:0] rvs2_mask; // @[PermuteSequencer.scala:20:22]
reg [1:0] rvm_mask; // @[PermuteSequencer.scala:21:21]
reg [8:0] slide_offset; // @[PermuteSequencer.scala:23:25]
wire [2:0] incr_eew = inst_bits[6:0] == 7'h7 | inst_bits[6:0] == 7'h27 ? {1'h0, inst_bits[13:12]} : ~(|(inst_bits[14:12])) & (~(|(inst_bits[14:12])) | inst_bits[14:12] == 3'h3 | inst_bits[14:12] == 3'h4 ? {1'h0, inst_bits[31:26]} : 7'h40) == 7'hE ? 3'h1 : inst_vconfig_vtype_vsew; // @[Bundles.scala:56:20, :58:26, :72:20, :75:20, :84:{18,35}]
wire [8:0] _eff_vl_T_9 = 9'h100 >> {1'h0, inst_vconfig_vtype_vsew} + {1'h0, inst_vconfig_vtype_vlmul_sign, ~inst_vconfig_vtype_vlmul_mag}; // @[PermuteSequencer.scala:18:18]
wire [8:0] _eff_vl_T_10 = inst_vconfig_vl + slide_offset; // @[PermuteSequencer.scala:18:18, :23:25, :34:97]
wire [8:0] eff_vl = ~(inst_bits[6:0] == 7'h7 | inst_bits[6:0] == 7'h27) & (|(inst_bits[14:12])) ? (inst_bits[26] ? (_eff_vl_T_9 > _eff_vl_T_10 ? _eff_vl_T_10 : _eff_vl_T_9) : inst_vconfig_vl - slide_offset) : inst_vconfig_vl; // @[Bundles.scala:56:20, :72:20, :75:20]
wire [2:0] _offset_T_13 = 3'h4 - incr_eew; // @[PipeSequencer.scala:54:33]
wire [7:0] _GEN = {5'h0, _offset_T_13}; // @[PipeSequencer.scala:54:{15,33}]
wire [15:0] _next_eidx_next_T_14 = {7'h0, {1'h0, eidx >> _GEN} + 9'h1} << _offset_T_13; // @[PipeSequencer.scala:54:{15,33,52,60}]
wire [8:0] next_eidx = eff_vl > _next_eidx_next_T_14[8:0] ? _next_eidx_next_T_14[8:0] : eff_vl; // @[PipeSequencer.scala:40:{34,37}, :52:10, :54:60]
wire tail = next_eidx == eff_vl; // @[PipeSequencer.scala:40:34]
wire _io_dis_ready_T_1 = io_iss_ready & io_iss_valid_0; // @[Decoupled.scala:51:35]
wire io_dis_ready_0 = ~valid | tail & _io_dis_ready_T_1; // @[Decoupled.scala:51:35]
wire [63:0] vs2_read_oh = inst_renv2 ? 64'h1 << _io_rvs2_req_bits_eg_T : 64'h0; // @[OneHot.scala:58:35]
wire [63:0] _rvm_mask_T_2 = 64'h1 << _eidx_7; // @[OneHot.scala:58:35]
wire oldest = inst_vat == io_vat_head; // @[PermuteSequencer.scala:18:18, :79:25]
wire [7:0] io_rvs2_req_bits_eg_off = eidx >> _GEN; // @[Parameters.scala:343:20]
assign _io_rvs2_req_bits_eg_T = {inst_rs1_is_rs2 ? inst_bits[19:15] : inst_bits[24:20], 1'h0} + io_rvs2_req_bits_eg_off[5:0]; // @[Parameters.scala:343:20, :344:10]
assign _eidx_7 = eidx[7]; // @[Parameters.scala:343:{20,26}]
assign io_iss_valid_0 = valid & (((inst_renvm ? _rvm_mask_T_2 : 64'h0) | vs2_read_oh) & io_older_writes) == 64'h0 & (~inst_renvm | io_rvm_req_ready) & (~inst_renv2 | io_rvs2_req_ready); // @[OneHot.scala:58:35]
wire _GEN_0 = io_dis_ready_0 & io_dis_valid; // @[Decoupled.scala:51:35]
wire [63:0] _offset_T_9 = io_dis_bits_bits[14] ? io_dis_bits_rs1_data : {59'h0, io_dis_bits_bits[19:15]}; // @[Bundles.scala:72:20, :73:18]
wire [8:0] offset = io_dis_bits_bits[14:12] == 3'h0 | io_dis_bits_bits[14:12] == 3'h3 | io_dis_bits_bits[14:12] == 3'h4 ? (_offset_T_9 > 64'h100 ? 9'h100 : _offset_T_9[8:0]) : 9'h1; // @[Bundles.scala:72:20]
wire slide_1 = ~(io_dis_bits_bits[6:0] == 7'h7 | io_dis_bits_bits[6:0] == 7'h27) & (|(io_dis_bits_bits[14:12])); // @[Bundles.scala:56:20, :72:20]
wire _GEN_1 = _io_dis_ready_T_1 & next_eidx != eff_vl; // @[Decoupled.scala:51:35]
wire [4:0] rs2_1 = io_dis_bits_rs1_is_rs2 ? io_dis_bits_bits[19:15] : io_dis_bits_bits[24:20]; // @[Bundles.scala:69:17, :73:18]
wire [3:0][31:0] _GEN_2 = {{{{8{&(rs2_1[4:3])}}, {8{rs2_1[4:3] == 2'h2}}, {8{rs2_1[4:3] == 2'h1}}, {8{rs2_1[4:3] == 2'h0}}}}, {{{4{&(rs2_1[4:2])}}, {4{rs2_1[4:2] == 3'h6}}, {4{rs2_1[4:2] == 3'h5}}, {4{rs2_1[4:2] == 3'h4}}, {4{rs2_1[4:2] == 3'h3}}, {4{rs2_1[4:2] == 3'h2}}, {4{rs2_1[4:2] == 3'h1}}, {4{rs2_1[4:2] == 3'h0}}}}, {{{2{&(rs2_1[4:1])}}, {2{rs2_1[4:1] == 4'hE}}, {2{rs2_1[4:1] == 4'hD}}, {2{rs2_1[4:1] == 4'hC}}, {2{rs2_1[4:1] == 4'hB}}, {2{rs2_1[4:1] == 4'hA}}, {2{rs2_1[4:1] == 4'h9}}, {2{rs2_1[4:1] == 4'h8}}, {2{rs2_1[4:1] == 4'h7}}, {2{rs2_1[4:1] == 4'h6}}, {2{rs2_1[4:1] == 4'h5}}, {2{rs2_1[4:1] == 4'h4}}, {2{rs2_1[4:1] == 4'h3}}, {2{rs2_1[4:1] == 4'h2}}, {2{rs2_1[4:1] == 4'h1}}, {2{rs2_1[4:1] == 4'h0}}}}, {32'h1 << rs2_1}}; // @[OneHot.scala:58:35]
always @(posedge clock) begin // @[PermuteSequencer.scala:9:7]
if (reset) // @[PermuteSequencer.scala:9:7]
valid <= 1'h0; // @[PermuteSequencer.scala:17:22]
else if (_GEN_0) // @[Decoupled.scala:51:35]
valid <= ~slide_1 | ~(io_dis_bits_bits[26] ? offset >= 9'h100 >> {1'h0, io_dis_bits_vconfig_vtype_vsew} + {1'h0, io_dis_bits_vconfig_vtype_vlmul_sign, ~io_dis_bits_vconfig_vtype_vlmul_mag} : io_dis_bits_vconfig_vl <= offset); // @[Bundles.scala:75:20]
else if (_io_dis_ready_T_1) // @[Decoupled.scala:51:35]
valid <= next_eidx != eff_vl; // @[PipeSequencer.scala:40:34]
if (_GEN_0) begin // @[Decoupled.scala:51:35]
inst_bits <= io_dis_bits_bits; // @[PermuteSequencer.scala:18:18]
inst_vconfig_vl <= io_dis_bits_vconfig_vl; // @[PermuteSequencer.scala:18:18]
inst_vconfig_vtype_vsew <= io_dis_bits_vconfig_vtype_vsew; // @[PermuteSequencer.scala:18:18]
inst_vconfig_vtype_vlmul_sign <= io_dis_bits_vconfig_vtype_vlmul_sign; // @[PermuteSequencer.scala:18:18]
inst_vconfig_vtype_vlmul_mag <= io_dis_bits_vconfig_vtype_vlmul_mag; // @[PermuteSequencer.scala:18:18]
inst_vat <= io_dis_bits_vat; // @[PermuteSequencer.scala:18:18]
inst_rs1_is_rs2 <= io_dis_bits_rs1_is_rs2; // @[PermuteSequencer.scala:18:18]
inst_renv2 <= io_dis_bits_renv2; // @[PermuteSequencer.scala:18:18]
inst_renvm <= io_dis_bits_renvm; // @[PermuteSequencer.scala:18:18]
slide_offset <= offset; // @[PermuteSequencer.scala:23:25, :44:21]
end
if (_GEN_1) // @[PermuteSequencer.scala:99:21]
eidx <= next_eidx[7:0]; // @[PipeSequencer.scala:40:34]
else if (_GEN_0) // @[Decoupled.scala:51:35]
eidx <= slide_1 ? (io_dis_bits_bits[26] ? offset[7:0] : 8'h0) : io_dis_bits_vstart; // @[Bundles.scala:75:20]
if (~_GEN_1 | next_eidx >> _offset_T_13 == {1'h0, eidx >> _GEN}) begin // @[PipeSequencer.scala:40:34, :54:{15,33}, :60:{16,27,37}]
if (_GEN_0) // @[Decoupled.scala:51:35]
rvs2_mask <= io_dis_bits_renv2 ? {{2{_GEN_2[io_dis_bits_emul][31]}}, {2{_GEN_2[io_dis_bits_emul][30]}}, {2{_GEN_2[io_dis_bits_emul][29]}}, {2{_GEN_2[io_dis_bits_emul][28]}}, {2{_GEN_2[io_dis_bits_emul][27]}}, {2{_GEN_2[io_dis_bits_emul][26]}}, {2{_GEN_2[io_dis_bits_emul][25]}}, {2{_GEN_2[io_dis_bits_emul][24]}}, {2{_GEN_2[io_dis_bits_emul][23]}}, {2{_GEN_2[io_dis_bits_emul][22]}}, {2{_GEN_2[io_dis_bits_emul][21]}}, {2{_GEN_2[io_dis_bits_emul][20]}}, {2{_GEN_2[io_dis_bits_emul][19]}}, {2{_GEN_2[io_dis_bits_emul][18]}}, {2{_GEN_2[io_dis_bits_emul][17]}}, {2{_GEN_2[io_dis_bits_emul][16]}}, {2{_GEN_2[io_dis_bits_emul][15]}}, {2{_GEN_2[io_dis_bits_emul][14]}}, {2{_GEN_2[io_dis_bits_emul][13]}}, {2{_GEN_2[io_dis_bits_emul][12]}}, {2{_GEN_2[io_dis_bits_emul][11]}}, {2{_GEN_2[io_dis_bits_emul][10]}}, {2{_GEN_2[io_dis_bits_emul][9]}}, {2{_GEN_2[io_dis_bits_emul][8]}}, {2{_GEN_2[io_dis_bits_emul][7]}}, {2{_GEN_2[io_dis_bits_emul][6]}}, {2{_GEN_2[io_dis_bits_emul][5]}}, {2{_GEN_2[io_dis_bits_emul][4]}}, {2{_GEN_2[io_dis_bits_emul][3]}}, {2{_GEN_2[io_dis_bits_emul][2]}}, {2{_GEN_2[io_dis_bits_emul][1]}}, {2{_GEN_2[io_dis_bits_emul][0]}}} : 64'h0; // @[PermuteSequencer.scala:20:22, :59:{21,53}]
end
else // @[PermuteSequencer.scala:42:22, :99:31, :100:91]
rvs2_mask <= rvs2_mask & ~vs2_read_oh; // @[PermuteSequencer.scala:20:22, :73:24, :101:{30,32}]
if (~_GEN_1 | {7'h0, next_eidx[8:7]} == {8'h0, _eidx_7}) begin // @[Parameters.scala:342:21, :343:{20,26}, :344:10]
if (_GEN_0) // @[Decoupled.scala:51:35]
rvm_mask <= {2{io_dis_bits_renvm}}; // @[PermuteSequencer.scala:21:21, :60:20]
end
else // @[PermuteSequencer.scala:42:22, :99:31, :103:85]
rvm_mask <= ~(_rvm_mask_T_2[1:0]) & rvm_mask; // @[OneHot.scala:58:35]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
| module MulAddRecFNToRaw_preMul_e8_s24_60( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_267( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_11 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_72( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30] |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_25( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h6 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 3'h5 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire [1:0] _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_1, 1'h0}; // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'hD; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'hD; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [9:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [9:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_165 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_171 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_177 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_183 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_189 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_195 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_201 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_207 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_213 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_219 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_225 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_231 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_237 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_243 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_249 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_255 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_261 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_267 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_273 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_279 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_285 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_291 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_293 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_first_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_first_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_first_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_first_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_set_wo_ready_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_set_wo_ready_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_opcodes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_opcodes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_sizes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_sizes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_opcodes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_opcodes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_sizes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_sizes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_probe_ack_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_probe_ack_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _c_probe_ack_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _c_probe_ack_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _same_cycle_resp_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _same_cycle_resp_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _same_cycle_resp_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _same_cycle_resp_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [9:0] _same_cycle_resp_WIRE_4_bits_source = 10'h0; // @[Bundles.scala:265:74]
wire [9:0] _same_cycle_resp_WIRE_5_bits_source = 10'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [8194:0] _c_opcodes_set_T_1 = 8195'h0; // @[Monitor.scala:767:54]
wire [8194:0] _c_sizes_set_T_1 = 8195'h0; // @[Monitor.scala:768:52]
wire [12:0] _c_opcodes_set_T = 13'h0; // @[Monitor.scala:767:79]
wire [12:0] _c_sizes_set_T = 13'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [1023:0] _c_set_wo_ready_T = 1024'h1; // @[OneHot.scala:58:35]
wire [1023:0] _c_set_T = 1024'h1; // @[OneHot.scala:58:35]
wire [2051:0] c_opcodes_set = 2052'h0; // @[Monitor.scala:740:34]
wire [2051:0] c_sizes_set = 2052'h0; // @[Monitor.scala:741:34]
wire [512:0] c_set = 513'h0; // @[Monitor.scala:738:34]
wire [512:0] c_set_wo_ready = 513'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [9:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [9:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [7:0] _source_ok_T_1 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_7 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_13 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_19 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_25 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_31 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_73 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_79 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 8'h70; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 8'h71; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 8'h72; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 8'h73; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 8'h7C; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 8'h7B; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_61 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_67 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_91 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_97 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_109 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_115 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_121 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_127 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'hD; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'hC; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 8'h7A; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_80 = _source_ok_T_79 == 8'h79; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_92 = _source_ok_T_91 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_98 = _source_ok_T_97 == 5'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_110 = _source_ok_T_109 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_122 = _source_ok_T_121 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_128 = _source_ok_T_127 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31]
wire _source_ok_T_133 = io_in_a_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31]
wire _source_ok_T_134 = io_in_a_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31]
wire _source_ok_T_135 = io_in_a_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_25 = _source_ok_T_135; // @[Parameters.scala:1138:31]
wire _source_ok_T_136 = io_in_a_bits_source_0 == 10'h200; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_26 = _source_ok_T_136; // @[Parameters.scala:1138:31]
wire _source_ok_T_137 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_158 = _source_ok_T_157 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_159 = _source_ok_T_158 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_160 = _source_ok_T_159 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_161 = _source_ok_T_160 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_161 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_162 = io_in_d_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_162; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [7:0] _source_ok_T_163 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_169 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_175 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_181 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_187 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_193 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_235 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_T_241 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_164 = _source_ok_T_163 == 8'h70; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_166 = _source_ok_T_164; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_168; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_170 = _source_ok_T_169 == 8'h71; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_172 = _source_ok_T_170; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_174; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_176 = _source_ok_T_175 == 8'h72; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_178 = _source_ok_T_176; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_180; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_182 = _source_ok_T_181 == 8'h73; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_184 = _source_ok_T_182; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_186; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_188 = _source_ok_T_187 == 8'h7C; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_190 = _source_ok_T_188; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_192; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_194 = _source_ok_T_193 == 8'h7B; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_196 = _source_ok_T_194; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_198; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_199 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_205 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_211 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_217 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_223 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_229 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_247 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_253 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_259 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_265 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_271 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_277 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_283 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_289 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_200 = _source_ok_T_199 == 5'hD; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_202 = _source_ok_T_200; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_204; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_206 = _source_ok_T_205 == 5'hC; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_208 = _source_ok_T_206; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_210; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_212 = _source_ok_T_211 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_214 = _source_ok_T_212; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_9 = _source_ok_T_216; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_218 = _source_ok_T_217 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_220 = _source_ok_T_218; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_10 = _source_ok_T_222; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_224 = _source_ok_T_223 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_226 = _source_ok_T_224; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_11 = _source_ok_T_228; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_230 = _source_ok_T_229 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_232 = _source_ok_T_230; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_12 = _source_ok_T_234; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_236 = _source_ok_T_235 == 8'h7A; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_238 = _source_ok_T_236; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_13 = _source_ok_T_240; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_242 = _source_ok_T_241 == 8'h79; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_244 = _source_ok_T_242; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_14 = _source_ok_T_246; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_248 = _source_ok_T_247 == 5'h7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_250 = _source_ok_T_248; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_15 = _source_ok_T_252; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_254 = _source_ok_T_253 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_256 = _source_ok_T_254; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_16 = _source_ok_T_258; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_260 = _source_ok_T_259 == 5'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_262 = _source_ok_T_260; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_17 = _source_ok_T_264; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_266 = _source_ok_T_265 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_268 = _source_ok_T_266; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_18 = _source_ok_T_270; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_272 = _source_ok_T_271 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_274 = _source_ok_T_272; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_19 = _source_ok_T_276; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_278 = _source_ok_T_277 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_280 = _source_ok_T_278; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_20 = _source_ok_T_282; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_284 = _source_ok_T_283 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_286 = _source_ok_T_284; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_21 = _source_ok_T_288; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_290 = _source_ok_T_289 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_292 = _source_ok_T_290; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_294 = _source_ok_T_292; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_22 = _source_ok_T_294; // @[Parameters.scala:1138:31]
wire _source_ok_T_295 = io_in_d_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_23 = _source_ok_T_295; // @[Parameters.scala:1138:31]
wire _source_ok_T_296 = io_in_d_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_24 = _source_ok_T_296; // @[Parameters.scala:1138:31]
wire _source_ok_T_297 = io_in_d_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_25 = _source_ok_T_297; // @[Parameters.scala:1138:31]
wire _source_ok_T_298 = io_in_d_bits_source_0 == 10'h200; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_26 = _source_ok_T_298; // @[Parameters.scala:1138:31]
wire _source_ok_T_299 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_300 = _source_ok_T_299 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_301 = _source_ok_T_300 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_302 = _source_ok_T_301 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_303 = _source_ok_T_302 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_304 = _source_ok_T_303 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_305 = _source_ok_T_304 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_306 = _source_ok_T_305 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_307 = _source_ok_T_306 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_308 = _source_ok_T_307 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_309 = _source_ok_T_308 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_310 = _source_ok_T_309 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_311 = _source_ok_T_310 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_312 = _source_ok_T_311 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_313 = _source_ok_T_312 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_314 = _source_ok_T_313 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_315 = _source_ok_T_314 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_316 = _source_ok_T_315 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_317 = _source_ok_T_316 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_318 = _source_ok_T_317 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_319 = _source_ok_T_318 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_320 = _source_ok_T_319 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_321 = _source_ok_T_320 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_322 = _source_ok_T_321 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_323 = _source_ok_T_322 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_323 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46]
wire _T_2709 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2709; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2709; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_2782 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2782; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2782; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2782; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [512:0] inflight; // @[Monitor.scala:614:27]
reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [512:0] a_set; // @[Monitor.scala:626:34]
wire [512:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [2051:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2051:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [12:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [12:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [12:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [12:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [12:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [12:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [12:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [12:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [12:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [2051:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [2051:0] _a_opcode_lookup_T_6 = {2048'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [2051:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [2051:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2051:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [2051:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2051:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1023:0] _GEN_2 = 1024'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [1023:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [1023:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire _T_2635 = _T_2709 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2635 ? _a_set_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2635 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2635 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [12:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [12:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [12:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [8194:0] _a_opcodes_set_T_1 = {8191'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2635 ? _a_opcodes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8194:0] _a_sizes_set_T_1 = {8191'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2635 ? _a_sizes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [512:0] d_clr; // @[Monitor.scala:664:34]
wire [512:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [2051:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2051:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_2681 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1023:0] _GEN_5 = 1024'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [1023:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2681 & ~d_release_ack ? _d_clr_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire _T_2650 = _T_2782 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2650 ? _d_clr_T[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire [8206:0] _d_opcodes_clr_T_5 = 8207'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2650 ? _d_opcodes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [8206:0] _d_sizes_clr_T_5 = 8207'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2650 ? _d_sizes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [512:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [512:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [512:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [2051:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [2051:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [2051:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2051:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2051:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2051:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [512:0] inflight_1; // @[Monitor.scala:726:35]
wire [512:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [2051:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [2051:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2051:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [2051:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [2051:0] _c_opcode_lookup_T_6 = {2048'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [2051:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2051:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2051:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [2051:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2051:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [512:0] d_clr_1; // @[Monitor.scala:774:34]
wire [512:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [2051:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2051:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2753 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2753 & d_release_ack_1 ? _d_clr_wo_ready_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire _T_2735 = _T_2782 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2735 ? _d_clr_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35]
wire [8206:0] _d_opcodes_clr_T_11 = 8207'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2735 ? _d_opcodes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [8206:0] _d_sizes_clr_T_11 = 8207'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2735 ? _d_sizes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 10'h0; // @[Monitor.scala:36:7, :795:113]
wire [512:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [512:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [2051:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [2051:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2051:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2051:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_358( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_406( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncQueueSink_DebugInternalBundle( // @[AsyncQueue.scala:136:7]
input clock, // @[AsyncQueue.scala:136:7]
input reset, // @[AsyncQueue.scala:136:7]
output io_deq_valid, // @[AsyncQueue.scala:139:14]
output io_deq_bits_resumereq, // @[AsyncQueue.scala:139:14]
output [9:0] io_deq_bits_hartsel, // @[AsyncQueue.scala:139:14]
output io_deq_bits_ackhavereset, // @[AsyncQueue.scala:139:14]
output io_deq_bits_hasel, // @[AsyncQueue.scala:139:14]
output io_deq_bits_hamask_0, // @[AsyncQueue.scala:139:14]
output io_deq_bits_hrmask_0, // @[AsyncQueue.scala:139:14]
input io_async_mem_0_resumereq, // @[AsyncQueue.scala:139:14]
input [9:0] io_async_mem_0_hartsel, // @[AsyncQueue.scala:139:14]
input io_async_mem_0_ackhavereset, // @[AsyncQueue.scala:139:14]
input io_async_mem_0_hrmask_0, // @[AsyncQueue.scala:139:14]
output io_async_ridx, // @[AsyncQueue.scala:139:14]
input io_async_widx, // @[AsyncQueue.scala:139:14]
output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14]
input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14]
input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14]
output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14]
);
wire io_deq_valid_0; // @[AsyncQueue.scala:136:7]
wire _source_extend_io_out; // @[AsyncQueue.scala:175:31]
wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33]
wire io_async_mem_0_resumereq_0 = io_async_mem_0_resumereq; // @[AsyncQueue.scala:136:7]
wire [9:0] io_async_mem_0_hartsel_0 = io_async_mem_0_hartsel; // @[AsyncQueue.scala:136:7]
wire io_async_mem_0_ackhavereset_0 = io_async_mem_0_ackhavereset; // @[AsyncQueue.scala:136:7]
wire io_async_mem_0_hrmask_0_0 = io_async_mem_0_hrmask_0; // @[AsyncQueue.scala:136:7]
wire io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7]
wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7]
wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7]
wire _ridx_T = reset; // @[AsyncQueue.scala:148:30]
wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35]
wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34]
wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35]
wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35]
wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35]
wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34]
wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32]
wire io_deq_ready = 1'h1; // @[AsyncQueue.scala:136:7]
wire [1:0] io_deq_bits_deq_bits_reg_io_d_lo_hi = 2'h0; // @[SynchronizerReg.scala:209:24]
wire io_async_mem_0_hasel = 1'h0; // @[AsyncQueue.scala:136:7]
wire io_async_mem_0_hamask_0 = 1'h0; // @[AsyncQueue.scala:136:7]
wire _ridx_T_3 = 1'h0; // @[AsyncQueue.scala:54:32]
wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29]
wire _ridx_T_1 = io_deq_valid_0; // @[Decoupled.scala:51:35]
wire _io_deq_bits_WIRE_resumereq; // @[SynchronizerReg.scala:211:26]
wire [9:0] _io_deq_bits_WIRE_hartsel; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_WIRE_ackhavereset; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_WIRE_hasel; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_WIRE_hamask_0; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_WIRE_hrmask_0; // @[SynchronizerReg.scala:211:26]
wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25]
wire io_deq_bits_hamask_0_0; // @[AsyncQueue.scala:136:7]
wire io_deq_bits_hrmask_0_0; // @[AsyncQueue.scala:136:7]
wire io_deq_bits_resumereq_0; // @[AsyncQueue.scala:136:7]
wire [9:0] io_deq_bits_hartsel_0; // @[AsyncQueue.scala:136:7]
wire io_deq_bits_ackhavereset_0; // @[AsyncQueue.scala:136:7]
wire io_deq_bits_hasel_0; // @[AsyncQueue.scala:136:7]
wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7]
wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7]
wire io_async_ridx_0; // @[AsyncQueue.scala:136:7]
wire source_ready; // @[AsyncQueue.scala:147:30]
wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77]
wire _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire ridx_incremented; // @[AsyncQueue.scala:51:27]
wire ridx = ridx_incremented; // @[AsyncQueue.scala:51:27, :54:17]
reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25]
wire [1:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {1'h0, _ridx_T_1}; // @[Decoupled.scala:51:35]
wire _ridx_incremented_T_1 = _ridx_incremented_T[0]; // @[AsyncQueue.scala:53:43]
assign _ridx_incremented_T_2 = ~_ridx_T_2 & _ridx_incremented_T_1; // @[AsyncQueue.scala:53:{23,43}, :148:77]
assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire widx; // @[ShiftReg.scala:48:24]
wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24]
wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}]
wire [2:0] io_deq_bits_deq_bits_reg_io_d_lo = {2'h0, io_async_mem_0_hrmask_0_0}; // @[SynchronizerReg.scala:209:24]
wire [10:0] io_deq_bits_deq_bits_reg_io_d_hi_hi = {io_async_mem_0_resumereq_0, io_async_mem_0_hartsel_0}; // @[SynchronizerReg.scala:209:24]
wire [11:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_deq_bits_deq_bits_reg_io_d_hi_hi, io_async_mem_0_ackhavereset_0}; // @[SynchronizerReg.scala:209:24]
wire [14:0] _io_deq_bits_deq_bits_reg_io_d_T = {io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala:209:24]
wire _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_resumereq_0 = _io_deq_bits_WIRE_resumereq; // @[SynchronizerReg.scala:211:26]
wire [9:0] _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_hartsel_0 = _io_deq_bits_WIRE_hartsel; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_ackhavereset_0 = _io_deq_bits_WIRE_ackhavereset; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_hasel_0 = _io_deq_bits_WIRE_hasel; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_hamask_0_0 = _io_deq_bits_WIRE_hamask_0; // @[SynchronizerReg.scala:211:26]
wire _io_deq_bits_T; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_hrmask_0_0 = _io_deq_bits_WIRE_hrmask_0; // @[SynchronizerReg.scala:211:26]
wire [14:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_hrmask_0 = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T_1 = _io_deq_bits_WIRE_1[1]; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_hamask_0 = _io_deq_bits_T_1; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T_2 = _io_deq_bits_WIRE_1[2]; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_hasel = _io_deq_bits_T_2; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T_3 = _io_deq_bits_WIRE_1[3]; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_ackhavereset = _io_deq_bits_T_3; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T_4 = _io_deq_bits_WIRE_1[13:4]; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_hartsel = _io_deq_bits_T_4; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T_5 = _io_deq_bits_WIRE_1[14]; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_resumereq = _io_deq_bits_T_5; // @[SynchronizerReg.scala:211:26]
reg valid_reg; // @[AsyncQueue.scala:165:56]
assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29]
assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29]
reg ridx_gray; // @[AsyncQueue.scala:168:55]
assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55]
wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45]
wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}]
wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}]
wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45]
wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}]
wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}]
wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45]
wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}]
wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}]
assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}]
assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25]
always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30]
if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30]
ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:136:7]
ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35]
if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35]
valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56]
else // @[AsyncQueue.scala:136:7]
valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56]
always @(posedge, posedge)
always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34]
if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34]
ridx_gray <= 1'h0; // @[AsyncQueue.scala:168:55]
else // @[AsyncQueue.scala:136:7]
ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_135( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_135 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_62( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_27( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_283 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
| module PlusArgTimeout( // @[PlusArg.scala:58:7]
input clock, // @[PlusArg.scala:58:7]
input reset, // @[PlusArg.scala:58:7]
input [31:0] io_count // @[PlusArg.scala:59:14]
);
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19]
wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File BusBypass.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096)
(implicit p: Parameters) extends LazyModule
{
protected val nodeIn = TLIdentityNode()
protected val nodeOut = TLIdentityNode()
val node = NodeHandle(nodeIn, nodeOut)
protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp =>
mp.v1copy(managers = mp.managers.map { m =>
m.v1copy(
mayDenyPut = m.mayDenyPut || !deadlock,
mayDenyGet = m.mayDenyGet || !deadlock)
})
}))
protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
protected val params = DevNullParams(everything, maxAtomic, maxTransfer, region=RegionType.TRACKED)
protected val error = if (deadlock) LazyModule(new TLDeadlock(params, beatBytes))
else LazyModule(new TLError(params, bufferError, beatBytes))
// order matters because the parameters and bypass
// assume that the non-bypassed connection is
// the last connection to the bar, so keep nodeOut last.
bar.node := nodeIn
error.node := bar.node
nodeOut := bar.node
}
class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = 16, maxTransfer: Int = 4096)(implicit p: Parameters)
extends TLBusBypassBase(beatBytes, deadlock = false, bufferError = bufferError, maxAtomic = maxAtomic, maxTransfer = maxTransfer)
{
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val bypass = Input(Bool())
})
bar.module.io.bypass := io.bypass
}
}
class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode
{
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
require (iStars == 0 && oStars == 0, "TLBypass node does not support :=* or :*=")
require (iKnown == 1, "TLBypass node expects exactly one input")
require (oKnown == 2, "TLBypass node expects exactly two outputs")
(0, 0)
}
def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p }
def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))}
}
class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule
{
val node = new TLBypassNode(dFn)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val bypass = Input(Bool())
val pending = Output(Bool())
})
val (in, edgeIn) = node.in(0)
val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out
require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes,
s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)")
// We need to be locked to the given bypass direction until all transactions stop
val in_reset = RegNext(false.B, init = true.B)
val bypass_reg = Reg(Bool())
val bypass = Mux(in_reset, io.bypass, bypass_reg)
val (flight, next_flight) = edgeIn.inFlight(in)
io.pending := (flight > 0.U)
when (in_reset || (next_flight === 0.U)) { bypass_reg := io.bypass }
val stall = (bypass =/= io.bypass) && edgeIn.first(in.a)
out0.a.valid := !stall && in.a.valid && bypass
out1.a.valid := !stall && in.a.valid && !bypass
in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready)
out0.a.bits := in.a.bits
out1.a.bits := in.a.bits
out0.d.ready := in.d.ready && bypass
out1.d.ready := in.d.ready && !bypass
in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid)
def cast(x: TLBundleD) = { val out = WireDefault(in.d.bits); out <> x; out }
in.d.bits := Mux(bypass, cast(out0.d.bits), cast(out1.d.bits))
if (edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
out0.b.ready := in.b.ready && bypass
out1.b.ready := in.b.ready && !bypass
in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid)
def cast(x: TLBundleB) = { val out = Wire(in.b.bits); out <> x; out }
in.b.bits := Mux(bypass, cast(out0.b.bits), cast(out1.b.bits))
out0.c.valid := in.c.valid && bypass
out1.c.valid := in.c.valid && !bypass
in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready)
out0.c.bits := in.c.bits
out1.c.bits := in.c.bits
out0.e.valid := in.e.valid && bypass
out1.e.valid := in.e.valid && !bypass
in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready)
out0.e.bits := in.e.bits
out1.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out0.b.ready := true.B
out0.c.valid := false.B
out0.e.valid := false.B
out1.b.ready := true.B
out1.c.valid := false.B
out1.e.valid := false.B
}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLBusBypassBar( // @[BusBypass.scala:66:9]
input clock, // @[BusBypass.scala:66:9]
input reset, // @[BusBypass.scala:66:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_bypass // @[BusBypass.scala:67:16]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9]
wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71]
wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71]
wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46]
wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9]
wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_last = 1'h1; // @[Edges.scala:232:33]
wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire b_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43]
wire d_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28]
wire e_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43]
wire e_last = 1'h1; // @[Edges.scala:232:33]
wire c_response = 1'h1; // @[Edges.scala:82:41]
wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire stall_last = 1'h1; // @[Edges.scala:232:33]
wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire r_beats1 = 1'h0; // @[Edges.scala:221:14]
wire r_4 = 1'h0; // @[Edges.scala:234:25]
wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire r_3_1 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire r_4_1 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25]
wire r_3_2 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27]
wire r_4_2 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14]
wire r_4_3 = 1'h0; // @[Edges.scala:234:25]
wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25]
wire r_3_4 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27]
wire r_4_4 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21]
wire c_request = 1'h0; // @[Edges.scala:68:40]
wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26]
wire b_inc = 1'h0; // @[Edges.scala:311:37]
wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26]
wire c_inc = 1'h0; // @[Edges.scala:312:37]
wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26]
wire e_inc = 1'h0; // @[Edges.scala:314:37]
wire a_dec = 1'h0; // @[Edges.scala:317:36]
wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26]
wire b_dec = 1'h0; // @[Edges.scala:318:36]
wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26]
wire c_dec = 1'h0; // @[Edges.scala:319:36]
wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26]
wire e_dec = 1'h0; // @[Edges.scala:321:36]
wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire stall_beats1 = 1'h0; // @[Edges.scala:221:14]
wire stall_count = 1'h0; // @[Edges.scala:234:25]
wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire _io_pending_T; // @[BusBypass.scala:84:27]
wire auto_in_a_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire auto_in_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
wire io_pending; // @[BusBypass.scala:66:9]
wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
reg in_reset; // @[BusBypass.scala:79:27]
reg bypass_reg; // @[BusBypass.scala:80:25]
wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21]
reg [1:0] flight; // @[Edges.scala:295:25]
wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35]
wire r_3; // @[Edges.scala:233:22]
assign r_3 = _T; // @[Decoupled.scala:51:35]
wire _a_inc_T; // @[Decoupled.scala:51:35]
assign _a_inc_T = _T; // @[Decoupled.scala:51:35]
wire _a_dec_T; // @[Decoupled.scala:51:35]
assign _a_dec_T = _T; // @[Decoupled.scala:51:35]
wire _stall_T_1; // @[Decoupled.scala:51:35]
assign _stall_T_1 = _T; // @[Decoupled.scala:51:35]
wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg r_counter; // @[Edges.scala:229:27]
wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25]
wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire r_3_3; // @[Edges.scala:233:22]
assign r_3_3 = _T_3; // @[Decoupled.scala:51:35]
wire _d_inc_T; // @[Decoupled.scala:51:35]
assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35]
wire _d_dec_T; // @[Decoupled.scala:51:35]
assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35]
wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg r_counter_3; // @[Edges.scala:229:27]
wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28]
wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25]
wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}]
wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35]
wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}]
wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35]
wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}]
wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18]
wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35]
wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35]
wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}]
wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18]
wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40]
wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40]
wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40]
wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40]
wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}]
wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30]
wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56]
wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56]
wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56]
wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56]
wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}]
wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46]
assign _io_pending_T = |flight; // @[Edges.scala:295:25]
assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27]
wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25]
wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35]
wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg stall_counter; // @[Edges.scala:229:27]
wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28]
wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25]
wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27]
wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire stall = _stall_T & stall_first; // @[Edges.scala:231:25]
wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21]
wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21]
wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}]
wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45]
assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}]
assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21]
wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34]
assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}]
assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18]
assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32]
assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35]
assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}]
assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24]
assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
always @(posedge clock) begin // @[BusBypass.scala:66:9]
if (reset) begin // @[BusBypass.scala:66:9]
in_reset <= 1'h1; // @[BusBypass.scala:79:27]
flight <= 2'h0; // @[Edges.scala:295:25]
r_counter <= 1'h0; // @[Edges.scala:229:27]
r_counter_3 <= 1'h0; // @[Edges.scala:229:27]
stall_counter <= 1'h0; // @[Edges.scala:229:27]
end
else begin // @[BusBypass.scala:66:9]
in_reset <= 1'h0; // @[BusBypass.scala:79:27]
flight <= next_flight; // @[Edges.scala:295:25, :324:46]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T_3) // @[Decoupled.scala:51:35]
r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21]
if (_stall_T_1) // @[Decoupled.scala:51:35]
stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46]
bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25]
always @(posedge)
TLMonitor_37 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_124( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_124 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
| module MulAddRecFNToRaw_preMul_e8_s24_57( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File SourceA.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
class SourceARequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val tag = UInt(params.tagBits.W)
val set = UInt(params.setBits.W)
val param = UInt(3.W)
val source = UInt(params.outer.bundle.sourceBits.W)
val block = Bool()
}
class SourceA(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceARequest(params)))
val a = Decoupled(new TLBundleA(params.outer.bundle))
})
// ready must be a register, because we derive valid from ready
require (!params.micro.outerBuf.a.pipe && params.micro.outerBuf.a.isDefined)
val a = Wire(chiselTypeOf(io.a))
io.a <> params.micro.outerBuf.a(a)
io.req.ready := a.ready
a.valid := io.req.valid
params.ccover(a.valid && !a.ready, "SOURCEA_STALL", "Backpressured when issuing an Acquire")
a.bits.opcode := Mux(io.req.bits.block, TLMessages.AcquireBlock, TLMessages.AcquirePerm)
a.bits.param := io.req.bits.param
a.bits.size := params.offsetBits.U
a.bits.source := io.req.bits.source
a.bits.address := params.expandAddress(io.req.bits.tag, io.req.bits.set, 0.U)
a.bits.mask := ~0.U(params.outer.manager.beatBytes.W)
a.bits.data := 0.U
a.bits.corrupt := false.B
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module SourceA( // @[SourceA.scala:33:7]
input clock, // @[SourceA.scala:33:7]
input reset, // @[SourceA.scala:33:7]
output io_req_ready, // @[SourceA.scala:35:14]
input io_req_valid, // @[SourceA.scala:35:14]
input [12:0] io_req_bits_tag, // @[SourceA.scala:35:14]
input [9:0] io_req_bits_set, // @[SourceA.scala:35:14]
input [2:0] io_req_bits_param, // @[SourceA.scala:35:14]
input [2:0] io_req_bits_source, // @[SourceA.scala:35:14]
input io_req_bits_block, // @[SourceA.scala:35:14]
input io_a_ready, // @[SourceA.scala:35:14]
output io_a_valid, // @[SourceA.scala:35:14]
output [2:0] io_a_bits_opcode, // @[SourceA.scala:35:14]
output [2:0] io_a_bits_param, // @[SourceA.scala:35:14]
output [2:0] io_a_bits_size, // @[SourceA.scala:35:14]
output [2:0] io_a_bits_source, // @[SourceA.scala:35:14]
output [31:0] io_a_bits_address, // @[SourceA.scala:35:14]
output [7:0] io_a_bits_mask, // @[SourceA.scala:35:14]
output [63:0] io_a_bits_data, // @[SourceA.scala:35:14]
output io_a_bits_corrupt // @[SourceA.scala:35:14]
);
wire io_req_valid_0 = io_req_valid; // @[SourceA.scala:33:7]
wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceA.scala:33:7]
wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceA.scala:33:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceA.scala:33:7]
wire [2:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceA.scala:33:7]
wire io_req_bits_block_0 = io_req_bits_block; // @[SourceA.scala:33:7]
wire io_a_ready_0 = io_a_ready; // @[SourceA.scala:33:7]
wire _a_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12]
wire _a_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12]
wire _a_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12]
wire [2:0] a_bits_size = 3'h6; // @[SourceA.scala:43:15]
wire [63:0] a_bits_data = 64'h0; // @[SourceA.scala:43:15]
wire a_bits_corrupt = 1'h0; // @[SourceA.scala:43:15]
wire _a_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15]
wire _a_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12]
wire _a_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15]
wire _a_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12]
wire _a_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15]
wire _a_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12]
wire _a_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24]
wire _a_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24]
wire _a_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24]
wire [5:0] a_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15]
wire [5:0] _a_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6]
wire [1:0] a_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8]
wire a_ready; // @[SourceA.scala:43:15]
wire [7:0] a_bits_mask = 8'hFF; // @[SourceA.scala:43:15]
wire [7:0] _a_bits_mask_T = 8'hFF; // @[SourceA.scala:55:21]
wire a_valid = io_req_valid_0; // @[SourceA.scala:33:7, :43:15]
wire [12:0] a_bits_address_base_y = io_req_bits_tag_0; // @[SourceA.scala:33:7]
wire [9:0] a_bits_address_base_y_1 = io_req_bits_set_0; // @[SourceA.scala:33:7]
wire [2:0] a_bits_param = io_req_bits_param_0; // @[SourceA.scala:33:7, :43:15]
wire [2:0] a_bits_source = io_req_bits_source_0; // @[SourceA.scala:33:7, :43:15]
wire io_req_ready_0; // @[SourceA.scala:33:7]
wire [2:0] io_a_bits_opcode_0; // @[SourceA.scala:33:7]
wire [2:0] io_a_bits_param_0; // @[SourceA.scala:33:7]
wire [2:0] io_a_bits_size_0; // @[SourceA.scala:33:7]
wire [2:0] io_a_bits_source_0; // @[SourceA.scala:33:7]
wire [31:0] io_a_bits_address_0; // @[SourceA.scala:33:7]
wire [7:0] io_a_bits_mask_0; // @[SourceA.scala:33:7]
wire [63:0] io_a_bits_data_0; // @[SourceA.scala:33:7]
wire io_a_bits_corrupt_0; // @[SourceA.scala:33:7]
wire io_a_valid_0; // @[SourceA.scala:33:7]
assign io_req_ready_0 = a_ready; // @[SourceA.scala:33:7, :43:15]
wire [2:0] _a_bits_opcode_T; // @[SourceA.scala:50:24]
wire [31:0] _a_bits_address_T_29; // @[Parameters.scala:230:8]
wire [2:0] a_bits_opcode; // @[SourceA.scala:43:15]
wire [31:0] a_bits_address; // @[SourceA.scala:43:15]
assign _a_bits_opcode_T = {2'h3, ~io_req_bits_block_0}; // @[SourceA.scala:33:7, :50:24]
assign a_bits_opcode = _a_bits_opcode_T; // @[SourceA.scala:43:15, :50:24]
wire [12:0] _a_bits_address_base_T_5 = a_bits_address_base_y; // @[Parameters.scala:221:15, :223:6]
wire _a_bits_address_base_T_3 = ~_a_bits_address_base_T_2; // @[Parameters.scala:222:12]
wire [9:0] _a_bits_address_base_T_11 = a_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6]
wire _a_bits_address_base_T_9 = ~_a_bits_address_base_T_8; // @[Parameters.scala:222:12]
wire _a_bits_address_base_T_15 = ~_a_bits_address_base_T_14; // @[Parameters.scala:222:12]
wire [22:0] a_bits_address_base_hi = {_a_bits_address_base_T_5, _a_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19]
wire [28:0] a_bits_address_base = {a_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19]
wire _a_bits_address_T = a_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_1 = a_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_2 = a_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_3 = a_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_4 = a_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_5 = a_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_6 = a_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_7 = a_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_8 = a_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_9 = a_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_10 = a_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_11 = a_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_12 = a_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_13 = a_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_14 = a_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_15 = a_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_16 = a_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_17 = a_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_18 = a_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_19 = a_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_20 = a_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_21 = a_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_22 = a_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_23 = a_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_24 = a_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_25 = a_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_26 = a_bits_address_base[26]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_27 = a_bits_address_base[27]; // @[Parameters.scala:227:19, :229:72]
wire _a_bits_address_T_28 = a_bits_address_base[28]; // @[Parameters.scala:227:19, :229:72]
wire [1:0] a_bits_address_lo_lo_lo_lo = {_a_bits_address_T_1, _a_bits_address_T}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_lo_lo_lo_hi = {_a_bits_address_T_3, _a_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_lo_lo_lo = {a_bits_address_lo_lo_lo_hi, a_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_lo_lo_hi_lo = {_a_bits_address_T_5, _a_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_lo_lo_hi_hi = {_a_bits_address_T_7, _a_bits_address_T_6}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_lo_lo_hi = {a_bits_address_lo_lo_hi_hi, a_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] a_bits_address_lo_lo = {a_bits_address_lo_lo_hi, a_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_lo_hi_lo_lo = {_a_bits_address_T_9, _a_bits_address_T_8}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_lo_hi_lo_hi = {_a_bits_address_T_11, _a_bits_address_T_10}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_lo_hi_lo = {a_bits_address_lo_hi_lo_hi, a_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_lo_hi_hi_lo = {_a_bits_address_T_13, _a_bits_address_T_12}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_lo_hi_hi_hi = {_a_bits_address_T_15, _a_bits_address_T_14}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_lo_hi_hi = {a_bits_address_lo_hi_hi_hi, a_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] a_bits_address_lo_hi = {a_bits_address_lo_hi_hi, a_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [15:0] a_bits_address_lo = {a_bits_address_lo_hi, a_bits_address_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_hi_lo_lo_lo = {_a_bits_address_T_17, _a_bits_address_T_16}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_hi_lo_lo_hi = {_a_bits_address_T_19, _a_bits_address_T_18}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_hi_lo_lo = {a_bits_address_hi_lo_lo_hi, a_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_hi_lo_hi_lo = {_a_bits_address_T_21, _a_bits_address_T_20}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_hi_lo_hi_hi = {_a_bits_address_T_23, _a_bits_address_T_22}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_hi_lo_hi = {a_bits_address_hi_lo_hi_hi, a_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] a_bits_address_hi_lo = {a_bits_address_hi_lo_hi, a_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_hi_hi_lo_lo = {_a_bits_address_T_25, _a_bits_address_T_24}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] a_bits_address_hi_hi_lo_hi = {_a_bits_address_T_27, _a_bits_address_T_26}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_hi_hi_lo = {a_bits_address_hi_hi_lo_hi, a_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] a_bits_address_hi_hi_hi_hi = {_a_bits_address_T_28, 1'h0}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] a_bits_address_hi_hi_hi = {a_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8]
wire [7:0] a_bits_address_hi_hi = {a_bits_address_hi_hi_hi, a_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8]
wire [15:0] a_bits_address_hi = {a_bits_address_hi_hi, a_bits_address_hi_lo}; // @[Parameters.scala:230:8]
assign _a_bits_address_T_29 = {a_bits_address_hi, a_bits_address_lo}; // @[Parameters.scala:230:8]
assign a_bits_address = _a_bits_address_T_29; // @[SourceA.scala:43:15]
Queue2_TLBundleA_a32d64s3k3z3c io_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (a_ready),
.io_enq_valid (a_valid), // @[SourceA.scala:43:15]
.io_enq_bits_opcode (a_bits_opcode), // @[SourceA.scala:43:15]
.io_enq_bits_param (a_bits_param), // @[SourceA.scala:43:15]
.io_enq_bits_source (a_bits_source), // @[SourceA.scala:43:15]
.io_enq_bits_address (a_bits_address), // @[SourceA.scala:43:15]
.io_deq_ready (io_a_ready_0), // @[SourceA.scala:33:7]
.io_deq_valid (io_a_valid_0),
.io_deq_bits_opcode (io_a_bits_opcode_0),
.io_deq_bits_param (io_a_bits_param_0),
.io_deq_bits_size (io_a_bits_size_0),
.io_deq_bits_source (io_a_bits_source_0),
.io_deq_bits_address (io_a_bits_address_0),
.io_deq_bits_mask (io_a_bits_mask_0),
.io_deq_bits_data (io_a_bits_data_0),
.io_deq_bits_corrupt (io_a_bits_corrupt_0)
); // @[Decoupled.scala:362:21]
assign io_req_ready = io_req_ready_0; // @[SourceA.scala:33:7]
assign io_a_valid = io_a_valid_0; // @[SourceA.scala:33:7]
assign io_a_bits_opcode = io_a_bits_opcode_0; // @[SourceA.scala:33:7]
assign io_a_bits_param = io_a_bits_param_0; // @[SourceA.scala:33:7]
assign io_a_bits_size = io_a_bits_size_0; // @[SourceA.scala:33:7]
assign io_a_bits_source = io_a_bits_source_0; // @[SourceA.scala:33:7]
assign io_a_bits_address = io_a_bits_address_0; // @[SourceA.scala:33:7]
assign io_a_bits_mask = io_a_bits_mask_0; // @[SourceA.scala:33:7]
assign io_a_bits_data = io_a_bits_data_0; // @[SourceA.scala:33:7]
assign io_a_bits_corrupt = io_a_bits_corrupt_0; // @[SourceA.scala:33:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w1_i0_46( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module IntSyncCrossingSource_n1x2_5( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
input auto_in_1, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_1 // @[LazyModuleImp.scala:107:25]
);
wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21]
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_1; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
wire auto_out_sync_1_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9]
assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21]
AsyncResetRegVec_w2_i0_5 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36]
.io_q (_reg_io_q)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File BusBypass.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096)
(implicit p: Parameters) extends LazyModule
{
protected val nodeIn = TLIdentityNode()
protected val nodeOut = TLIdentityNode()
val node = NodeHandle(nodeIn, nodeOut)
protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp =>
mp.v1copy(managers = mp.managers.map { m =>
m.v1copy(
mayDenyPut = m.mayDenyPut || !deadlock,
mayDenyGet = m.mayDenyGet || !deadlock)
})
}))
protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
protected val params = DevNullParams(everything, maxAtomic, maxTransfer, region=RegionType.TRACKED)
protected val error = if (deadlock) LazyModule(new TLDeadlock(params, beatBytes))
else LazyModule(new TLError(params, bufferError, beatBytes))
// order matters because the parameters and bypass
// assume that the non-bypassed connection is
// the last connection to the bar, so keep nodeOut last.
bar.node := nodeIn
error.node := bar.node
nodeOut := bar.node
}
class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = 16, maxTransfer: Int = 4096)(implicit p: Parameters)
extends TLBusBypassBase(beatBytes, deadlock = false, bufferError = bufferError, maxAtomic = maxAtomic, maxTransfer = maxTransfer)
{
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val bypass = Input(Bool())
})
bar.module.io.bypass := io.bypass
}
}
class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode
{
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
require (iStars == 0 && oStars == 0, "TLBypass node does not support :=* or :*=")
require (iKnown == 1, "TLBypass node expects exactly one input")
require (oKnown == 2, "TLBypass node expects exactly two outputs")
(0, 0)
}
def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p }
def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))}
}
class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule
{
val node = new TLBypassNode(dFn)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val bypass = Input(Bool())
val pending = Output(Bool())
})
val (in, edgeIn) = node.in(0)
val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out
require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes,
s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)")
// We need to be locked to the given bypass direction until all transactions stop
val in_reset = RegNext(false.B, init = true.B)
val bypass_reg = Reg(Bool())
val bypass = Mux(in_reset, io.bypass, bypass_reg)
val (flight, next_flight) = edgeIn.inFlight(in)
io.pending := (flight > 0.U)
when (in_reset || (next_flight === 0.U)) { bypass_reg := io.bypass }
val stall = (bypass =/= io.bypass) && edgeIn.first(in.a)
out0.a.valid := !stall && in.a.valid && bypass
out1.a.valid := !stall && in.a.valid && !bypass
in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready)
out0.a.bits := in.a.bits
out1.a.bits := in.a.bits
out0.d.ready := in.d.ready && bypass
out1.d.ready := in.d.ready && !bypass
in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid)
def cast(x: TLBundleD) = { val out = WireDefault(in.d.bits); out <> x; out }
in.d.bits := Mux(bypass, cast(out0.d.bits), cast(out1.d.bits))
if (edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
out0.b.ready := in.b.ready && bypass
out1.b.ready := in.b.ready && !bypass
in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid)
def cast(x: TLBundleB) = { val out = Wire(in.b.bits); out <> x; out }
in.b.bits := Mux(bypass, cast(out0.b.bits), cast(out1.b.bits))
out0.c.valid := in.c.valid && bypass
out1.c.valid := in.c.valid && !bypass
in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready)
out0.c.bits := in.c.bits
out1.c.bits := in.c.bits
out0.e.valid := in.e.valid && bypass
out1.e.valid := in.e.valid && !bypass
in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready)
out0.e.bits := in.e.bits
out1.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out0.b.ready := true.B
out0.c.valid := false.B
out0.e.valid := false.B
out1.b.ready := true.B
out1.c.valid := false.B
out1.e.valid := false.B
}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBusBypass( // @[BusBypass.scala:41:9]
input clock, // @[BusBypass.scala:41:9]
input reset, // @[BusBypass.scala:41:9]
input auto_node_out_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_node_out_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_node_out_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_node_out_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_node_out_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_node_out_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_node_out_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_node_out_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_node_out_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_node_out_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_node_out_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_node_out_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_node_out_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_node_out_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_node_out_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_node_in_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_node_in_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_node_in_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_node_in_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_node_in_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_node_in_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_node_in_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_node_in_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_node_in_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_node_in_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_node_in_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_node_in_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_node_in_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_node_in_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_node_in_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_bypass // @[BusBypass.scala:42:16]
);
wire nodeInOut_d_valid; // @[MixedNode.scala:542:17]
wire nodeInOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [31:0] nodeInOut_d_bits_data; // @[MixedNode.scala:542:17]
wire nodeInOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire nodeInOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire nodeInOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] nodeInOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeInOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeInOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire nodeInOut_a_ready; // @[MixedNode.scala:542:17]
wire _error_auto_in_a_ready; // @[BusBypass.scala:27:40]
wire _error_auto_in_d_valid; // @[BusBypass.scala:27:40]
wire [2:0] _error_auto_in_d_bits_opcode; // @[BusBypass.scala:27:40]
wire [1:0] _error_auto_in_d_bits_param; // @[BusBypass.scala:27:40]
wire [1:0] _error_auto_in_d_bits_size; // @[BusBypass.scala:27:40]
wire _error_auto_in_d_bits_denied; // @[BusBypass.scala:27:40]
wire _error_auto_in_d_bits_corrupt; // @[BusBypass.scala:27:40]
wire _bar_auto_out_0_a_valid; // @[BusBypass.scala:17:33]
wire [2:0] _bar_auto_out_0_a_bits_opcode; // @[BusBypass.scala:17:33]
wire [127:0] _bar_auto_out_0_a_bits_address; // @[BusBypass.scala:17:33]
wire [31:0] _bar_auto_out_0_a_bits_data; // @[BusBypass.scala:17:33]
wire _bar_auto_out_0_d_ready; // @[BusBypass.scala:17:33]
wire auto_node_out_out_a_ready_0 = auto_node_out_out_a_ready; // @[BusBypass.scala:41:9]
wire auto_node_out_out_d_valid_0 = auto_node_out_out_d_valid; // @[BusBypass.scala:41:9]
wire [2:0] auto_node_out_out_d_bits_opcode_0 = auto_node_out_out_d_bits_opcode; // @[BusBypass.scala:41:9]
wire [1:0] auto_node_out_out_d_bits_param_0 = auto_node_out_out_d_bits_param; // @[BusBypass.scala:41:9]
wire [1:0] auto_node_out_out_d_bits_size_0 = auto_node_out_out_d_bits_size; // @[BusBypass.scala:41:9]
wire auto_node_out_out_d_bits_source_0 = auto_node_out_out_d_bits_source; // @[BusBypass.scala:41:9]
wire auto_node_out_out_d_bits_sink_0 = auto_node_out_out_d_bits_sink; // @[BusBypass.scala:41:9]
wire auto_node_out_out_d_bits_denied_0 = auto_node_out_out_d_bits_denied; // @[BusBypass.scala:41:9]
wire [31:0] auto_node_out_out_d_bits_data_0 = auto_node_out_out_d_bits_data; // @[BusBypass.scala:41:9]
wire auto_node_out_out_d_bits_corrupt_0 = auto_node_out_out_d_bits_corrupt; // @[BusBypass.scala:41:9]
wire auto_node_in_in_a_valid_0 = auto_node_in_in_a_valid; // @[BusBypass.scala:41:9]
wire [2:0] auto_node_in_in_a_bits_opcode_0 = auto_node_in_in_a_bits_opcode; // @[BusBypass.scala:41:9]
wire [8:0] auto_node_in_in_a_bits_address_0 = auto_node_in_in_a_bits_address; // @[BusBypass.scala:41:9]
wire [31:0] auto_node_in_in_a_bits_data_0 = auto_node_in_in_a_bits_data; // @[BusBypass.scala:41:9]
wire auto_node_in_in_d_ready_0 = auto_node_in_in_d_ready; // @[BusBypass.scala:41:9]
wire io_bypass_0 = io_bypass; // @[BusBypass.scala:41:9]
wire [3:0] auto_node_out_out_a_bits_mask = 4'hF; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [3:0] auto_node_in_in_a_bits_mask = 4'hF; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [3:0] nodeInOut_a_bits_mask = 4'hF; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [3:0] nodeInIn_a_bits_mask = 4'hF; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [3:0] nodeOutOut_a_bits_mask = 4'hF; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [3:0] nodeOutIn_a_bits_mask = 4'hF; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire auto_node_out_out_a_bits_source = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire auto_node_out_out_a_bits_corrupt = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire auto_node_in_in_a_bits_source = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire auto_node_in_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeInOut_a_bits_source = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeInOut_a_bits_corrupt = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeInIn_a_bits_source = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeInIn_a_bits_corrupt = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeOutOut_a_bits_source = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeOutOut_a_bits_corrupt = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeOutIn_a_bits_source = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeOutIn_a_bits_corrupt = 1'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [1:0] auto_node_out_out_a_bits_size = 2'h2; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [1:0] auto_node_in_in_a_bits_size = 2'h2; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [1:0] nodeInOut_a_bits_size = 2'h2; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [1:0] nodeInIn_a_bits_size = 2'h2; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [1:0] nodeOutOut_a_bits_size = 2'h2; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [1:0] nodeOutIn_a_bits_size = 2'h2; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [2:0] auto_node_out_out_a_bits_param = 3'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [2:0] auto_node_in_in_a_bits_param = 3'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [2:0] nodeInOut_a_bits_param = 3'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [2:0] nodeInIn_a_bits_param = 3'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [2:0] nodeOutOut_a_bits_param = 3'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire [2:0] nodeOutIn_a_bits_param = 3'h0; // @[BusBypass.scala:17:33, :27:40, :41:9]
wire nodeOutOut_a_ready = auto_node_out_out_a_ready_0; // @[BusBypass.scala:41:9]
wire nodeOutOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOutOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] nodeOutOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOutOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOutOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOutOut_d_valid = auto_node_out_out_d_valid_0; // @[BusBypass.scala:41:9]
wire [2:0] nodeOutOut_d_bits_opcode = auto_node_out_out_d_bits_opcode_0; // @[BusBypass.scala:41:9]
wire [1:0] nodeOutOut_d_bits_param = auto_node_out_out_d_bits_param_0; // @[BusBypass.scala:41:9]
wire [1:0] nodeOutOut_d_bits_size = auto_node_out_out_d_bits_size_0; // @[BusBypass.scala:41:9]
wire nodeOutOut_d_bits_source = auto_node_out_out_d_bits_source_0; // @[BusBypass.scala:41:9]
wire nodeOutOut_d_bits_sink = auto_node_out_out_d_bits_sink_0; // @[BusBypass.scala:41:9]
wire nodeOutOut_d_bits_denied = auto_node_out_out_d_bits_denied_0; // @[BusBypass.scala:41:9]
wire [31:0] nodeOutOut_d_bits_data = auto_node_out_out_d_bits_data_0; // @[BusBypass.scala:41:9]
wire nodeInIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeOutOut_d_bits_corrupt = auto_node_out_out_d_bits_corrupt_0; // @[BusBypass.scala:41:9]
wire nodeInIn_a_valid = auto_node_in_in_a_valid_0; // @[BusBypass.scala:41:9]
wire [2:0] nodeInIn_a_bits_opcode = auto_node_in_in_a_bits_opcode_0; // @[BusBypass.scala:41:9]
wire [8:0] nodeInIn_a_bits_address = auto_node_in_in_a_bits_address_0; // @[BusBypass.scala:41:9]
wire [31:0] nodeInIn_a_bits_data = auto_node_in_in_a_bits_data_0; // @[BusBypass.scala:41:9]
wire nodeInIn_d_ready = auto_node_in_in_d_ready_0; // @[BusBypass.scala:41:9]
wire nodeInIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeInIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeInIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeInIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeInIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeInIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeInIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeInIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeInIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_node_out_out_a_bits_opcode_0; // @[BusBypass.scala:41:9]
wire [8:0] auto_node_out_out_a_bits_address_0; // @[BusBypass.scala:41:9]
wire [31:0] auto_node_out_out_a_bits_data_0; // @[BusBypass.scala:41:9]
wire auto_node_out_out_a_valid_0; // @[BusBypass.scala:41:9]
wire auto_node_out_out_d_ready_0; // @[BusBypass.scala:41:9]
wire auto_node_in_in_a_ready_0; // @[BusBypass.scala:41:9]
wire [2:0] auto_node_in_in_d_bits_opcode_0; // @[BusBypass.scala:41:9]
wire [1:0] auto_node_in_in_d_bits_param_0; // @[BusBypass.scala:41:9]
wire [1:0] auto_node_in_in_d_bits_size_0; // @[BusBypass.scala:41:9]
wire auto_node_in_in_d_bits_source_0; // @[BusBypass.scala:41:9]
wire auto_node_in_in_d_bits_sink_0; // @[BusBypass.scala:41:9]
wire auto_node_in_in_d_bits_denied_0; // @[BusBypass.scala:41:9]
wire [31:0] auto_node_in_in_d_bits_data_0; // @[BusBypass.scala:41:9]
wire auto_node_in_in_d_bits_corrupt_0; // @[BusBypass.scala:41:9]
wire auto_node_in_in_d_valid_0; // @[BusBypass.scala:41:9]
assign nodeInIn_a_ready = nodeInOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_valid = nodeInOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_opcode = nodeInOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_param = nodeInOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_size = nodeInOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_source = nodeInOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_sink = nodeInOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_denied = nodeInOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeInIn_d_bits_data = nodeInOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] nodeInOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] nodeInOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeInOut_a_bits_data; // @[MixedNode.scala:542:17]
assign nodeInIn_d_bits_corrupt = nodeInOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire nodeInOut_a_valid; // @[MixedNode.scala:542:17]
wire nodeInOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_node_in_in_a_ready_0 = nodeInIn_a_ready; // @[BusBypass.scala:41:9]
assign nodeInOut_a_valid = nodeInIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeInOut_a_bits_opcode = nodeInIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeInOut_a_bits_address = nodeInIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeInOut_a_bits_data = nodeInIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeInOut_d_ready = nodeInIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_node_in_in_d_valid_0 = nodeInIn_d_valid; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_opcode_0 = nodeInIn_d_bits_opcode; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_param_0 = nodeInIn_d_bits_param; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_size_0 = nodeInIn_d_bits_size; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_source_0 = nodeInIn_d_bits_source; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_sink_0 = nodeInIn_d_bits_sink; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_denied_0 = nodeInIn_d_bits_denied; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_data_0 = nodeInIn_d_bits_data; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_corrupt_0 = nodeInIn_d_bits_corrupt; // @[BusBypass.scala:41:9]
wire nodeOutIn_a_ready = nodeOutOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire nodeOutIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_node_out_out_a_valid_0 = nodeOutOut_a_valid; // @[BusBypass.scala:41:9]
wire [2:0] nodeOutIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_node_out_out_a_bits_opcode_0 = nodeOutOut_a_bits_opcode; // @[BusBypass.scala:41:9]
wire [8:0] nodeOutIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_node_out_out_a_bits_address_0 = nodeOutOut_a_bits_address; // @[BusBypass.scala:41:9]
wire [31:0] nodeOutIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_node_out_out_a_bits_data_0 = nodeOutOut_a_bits_data; // @[BusBypass.scala:41:9]
wire nodeOutIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_node_out_out_d_ready_0 = nodeOutOut_d_ready; // @[BusBypass.scala:41:9]
wire nodeOutIn_d_valid = nodeOutOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] nodeOutIn_d_bits_opcode = nodeOutOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] nodeOutIn_d_bits_param = nodeOutOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] nodeOutIn_d_bits_size = nodeOutOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire nodeOutIn_d_bits_source = nodeOutOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire nodeOutIn_d_bits_sink = nodeOutOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire nodeOutIn_d_bits_denied = nodeOutOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] nodeOutIn_d_bits_data = nodeOutOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire nodeOutIn_d_bits_corrupt = nodeOutOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOutOut_a_valid = nodeOutIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOutOut_a_bits_opcode = nodeOutIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOutOut_a_bits_address = nodeOutIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOutOut_a_bits_data = nodeOutIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOutOut_d_ready = nodeOutIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
TLBusBypassBar bar ( // @[BusBypass.scala:17:33]
.clock (clock),
.reset (reset),
.auto_in_a_ready (nodeInOut_a_ready),
.auto_in_a_valid (nodeInOut_a_valid), // @[MixedNode.scala:542:17]
.auto_in_a_bits_opcode (nodeInOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_a_bits_address (nodeInOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_in_a_bits_data (nodeInOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_in_d_ready (nodeInOut_d_ready), // @[MixedNode.scala:542:17]
.auto_in_d_valid (nodeInOut_d_valid),
.auto_in_d_bits_opcode (nodeInOut_d_bits_opcode),
.auto_in_d_bits_param (nodeInOut_d_bits_param),
.auto_in_d_bits_size (nodeInOut_d_bits_size),
.auto_in_d_bits_source (nodeInOut_d_bits_source),
.auto_in_d_bits_sink (nodeInOut_d_bits_sink),
.auto_in_d_bits_denied (nodeInOut_d_bits_denied),
.auto_in_d_bits_data (nodeInOut_d_bits_data),
.auto_in_d_bits_corrupt (nodeInOut_d_bits_corrupt),
.auto_out_1_a_ready (nodeOutIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_1_a_valid (nodeOutIn_a_valid),
.auto_out_1_a_bits_opcode (nodeOutIn_a_bits_opcode),
.auto_out_1_a_bits_address (nodeOutIn_a_bits_address),
.auto_out_1_a_bits_data (nodeOutIn_a_bits_data),
.auto_out_1_d_ready (nodeOutIn_d_ready),
.auto_out_1_d_valid (nodeOutIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_opcode (nodeOutIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_param (nodeOutIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_size (nodeOutIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_source (nodeOutIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_sink (nodeOutIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_denied (nodeOutIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_data (nodeOutIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_corrupt (nodeOutIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_0_a_ready (_error_auto_in_a_ready), // @[BusBypass.scala:27:40]
.auto_out_0_a_valid (_bar_auto_out_0_a_valid),
.auto_out_0_a_bits_opcode (_bar_auto_out_0_a_bits_opcode),
.auto_out_0_a_bits_address (_bar_auto_out_0_a_bits_address),
.auto_out_0_a_bits_data (_bar_auto_out_0_a_bits_data),
.auto_out_0_d_ready (_bar_auto_out_0_d_ready),
.auto_out_0_d_valid (_error_auto_in_d_valid), // @[BusBypass.scala:27:40]
.auto_out_0_d_bits_opcode (_error_auto_in_d_bits_opcode), // @[BusBypass.scala:27:40]
.auto_out_0_d_bits_param (_error_auto_in_d_bits_param), // @[BusBypass.scala:27:40]
.auto_out_0_d_bits_size (_error_auto_in_d_bits_size), // @[BusBypass.scala:27:40]
.auto_out_0_d_bits_denied (_error_auto_in_d_bits_denied), // @[BusBypass.scala:27:40]
.auto_out_0_d_bits_corrupt (_error_auto_in_d_bits_corrupt), // @[BusBypass.scala:27:40]
.io_bypass (io_bypass_0) // @[BusBypass.scala:41:9]
); // @[BusBypass.scala:17:33]
TLError_1 error ( // @[BusBypass.scala:27:40]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_error_auto_in_a_ready),
.auto_in_a_valid (_bar_auto_out_0_a_valid), // @[BusBypass.scala:17:33]
.auto_in_a_bits_opcode (_bar_auto_out_0_a_bits_opcode), // @[BusBypass.scala:17:33]
.auto_in_a_bits_address (_bar_auto_out_0_a_bits_address), // @[BusBypass.scala:17:33]
.auto_in_a_bits_data (_bar_auto_out_0_a_bits_data), // @[BusBypass.scala:17:33]
.auto_in_d_ready (_bar_auto_out_0_d_ready), // @[BusBypass.scala:17:33]
.auto_in_d_valid (_error_auto_in_d_valid),
.auto_in_d_bits_opcode (_error_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_error_auto_in_d_bits_param),
.auto_in_d_bits_size (_error_auto_in_d_bits_size),
.auto_in_d_bits_denied (_error_auto_in_d_bits_denied),
.auto_in_d_bits_corrupt (_error_auto_in_d_bits_corrupt)
); // @[BusBypass.scala:27:40]
assign auto_node_out_out_a_valid = auto_node_out_out_a_valid_0; // @[BusBypass.scala:41:9]
assign auto_node_out_out_a_bits_opcode = auto_node_out_out_a_bits_opcode_0; // @[BusBypass.scala:41:9]
assign auto_node_out_out_a_bits_address = auto_node_out_out_a_bits_address_0; // @[BusBypass.scala:41:9]
assign auto_node_out_out_a_bits_data = auto_node_out_out_a_bits_data_0; // @[BusBypass.scala:41:9]
assign auto_node_out_out_d_ready = auto_node_out_out_d_ready_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_a_ready = auto_node_in_in_a_ready_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_valid = auto_node_in_in_d_valid_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_opcode = auto_node_in_in_d_bits_opcode_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_param = auto_node_in_in_d_bits_param_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_size = auto_node_in_in_d_bits_size_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_source = auto_node_in_in_d_bits_source_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_sink = auto_node_in_in_d_bits_sink_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_denied = auto_node_in_in_d_bits_denied_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_data = auto_node_in_in_d_bits_data_0; // @[BusBypass.scala:41:9]
assign auto_node_in_in_d_bits_corrupt = auto_node_in_in_d_bits_corrupt_0; // @[BusBypass.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File fetch-buffer.scala:
//******************************************************************************
// Copyright (c) 2018 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Takes a FetchBundle and converts into a vector of MicroOps.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.rocket.{MStatus, BP, BreakpointUnit}
import boom.v3.common._
import boom.v3.util.{BoolToChar, MaskUpper}
/**
* Bundle that is made up of converted MicroOps from the Fetch Bundle
* input to the Fetch Buffer. This is handed to the Decode stage.
*/
class FetchBufferResp(implicit p: Parameters) extends BoomBundle
{
val uops = Vec(coreWidth, Valid(new MicroOp()))
}
/**
* Buffer to hold fetched packets and convert them into a vector of MicroOps
* to give the Decode stage
*
* @param num_entries effectively the number of full-sized fetch packets we can hold.
*/
class FetchBuffer(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val numEntries = numFetchBufferEntries
val io = IO(new BoomBundle {
val enq = Flipped(Decoupled(new FetchBundle()))
val deq = new DecoupledIO(new FetchBufferResp())
// Was the pipeline redirected? Clear/reset the fetchbuffer.
val clear = Input(Bool())
})
require (numEntries > fetchWidth)
require (numEntries % coreWidth == 0)
val numRows = numEntries / coreWidth
val ram = Reg(Vec(numEntries, new MicroOp))
ram.suggestName("fb_uop_ram")
val deq_vec = Wire(Vec(numRows, Vec(coreWidth, new MicroOp)))
val head = RegInit(1.U(numRows.W))
val tail = RegInit(1.U(numEntries.W))
val maybe_full = RegInit(false.B)
//-------------------------------------------------------------
// **** Enqueue Uops ****
//-------------------------------------------------------------
// Step 1: Convert FetchPacket into a vector of MicroOps.
// Step 2: Generate one-hot write indices.
// Step 3: Write MicroOps into the RAM.
def rotateLeft(in: UInt, k: Int) = {
val n = in.getWidth
Cat(in(n-k-1,0), in(n-1, n-k))
}
val might_hit_head = (1 until fetchWidth).map(k => VecInit(rotateLeft(tail, k).asBools.zipWithIndex.filter
{case (e,i) => i % coreWidth == 0}.map {case (e,i) => e}).asUInt).map(tail => head & tail).reduce(_|_).orR
val at_head = (VecInit(tail.asBools.zipWithIndex.filter {case (e,i) => i % coreWidth == 0}
.map {case (e,i) => e}).asUInt & head).orR
val do_enq = !(at_head && maybe_full || might_hit_head)
io.enq.ready := do_enq
// Input microops.
val in_mask = Wire(Vec(fetchWidth, Bool()))
val in_uops = Wire(Vec(fetchWidth, new MicroOp()))
// Step 1: Convert FetchPacket into a vector of MicroOps.
for (b <- 0 until nBanks) {
for (w <- 0 until bankWidth) {
val i = (b * bankWidth) + w
val pc = (bankAlign(io.enq.bits.pc) + (i << 1).U)
in_uops(i) := DontCare
in_mask(i) := io.enq.valid && io.enq.bits.mask(i)
in_uops(i).edge_inst := false.B
in_uops(i).debug_pc := pc
in_uops(i).pc_lob := pc
in_uops(i).is_sfb := io.enq.bits.sfbs(i) || io.enq.bits.shadowed_mask(i)
if (w == 0) {
when (io.enq.bits.edge_inst(b)) {
in_uops(i).debug_pc := bankAlign(io.enq.bits.pc) + (b * bankBytes).U - 2.U
in_uops(i).pc_lob := bankAlign(io.enq.bits.pc) + (b * bankBytes).U
in_uops(i).edge_inst := true.B
}
}
in_uops(i).ftq_idx := io.enq.bits.ftq_idx
in_uops(i).inst := io.enq.bits.exp_insts(i)
in_uops(i).debug_inst := io.enq.bits.insts(i)
in_uops(i).is_rvc := io.enq.bits.insts(i)(1,0) =/= 3.U
in_uops(i).taken := io.enq.bits.cfi_idx.bits === i.U && io.enq.bits.cfi_idx.valid
in_uops(i).xcpt_pf_if := io.enq.bits.xcpt_pf_if
in_uops(i).xcpt_ae_if := io.enq.bits.xcpt_ae_if
in_uops(i).bp_debug_if := io.enq.bits.bp_debug_if_oh(i)
in_uops(i).bp_xcpt_if := io.enq.bits.bp_xcpt_if_oh(i)
in_uops(i).debug_fsrc := io.enq.bits.fsrc
}
}
// Step 2. Generate one-hot write indices.
val enq_idxs = Wire(Vec(fetchWidth, UInt(numEntries.W)))
def inc(ptr: UInt) = {
val n = ptr.getWidth
Cat(ptr(n-2,0), ptr(n-1))
}
var enq_idx = tail
for (i <- 0 until fetchWidth) {
enq_idxs(i) := enq_idx
enq_idx = Mux(in_mask(i), inc(enq_idx), enq_idx)
}
// Step 3: Write MicroOps into the RAM.
for (i <- 0 until fetchWidth) {
for (j <- 0 until numEntries) {
when (do_enq && in_mask(i) && enq_idxs(i)(j)) {
ram(j) := in_uops(i)
}
}
}
//-------------------------------------------------------------
// **** Dequeue Uops ****
//-------------------------------------------------------------
val tail_collisions = VecInit((0 until numEntries).map(i =>
head(i/coreWidth) && (!maybe_full || (i % coreWidth != 0).B))).asUInt & tail
val slot_will_hit_tail = (0 until numRows).map(i => tail_collisions((i+1)*coreWidth-1, i*coreWidth)).reduce(_|_)
val will_hit_tail = slot_will_hit_tail.orR
val do_deq = io.deq.ready && !will_hit_tail
val deq_valids = (~MaskUpper(slot_will_hit_tail)).asBools
// Generate vec for dequeue read port.
for (i <- 0 until numEntries) {
deq_vec(i/coreWidth)(i%coreWidth) := ram(i)
}
io.deq.bits.uops zip deq_valids map {case (d,v) => d.valid := v}
io.deq.bits.uops zip Mux1H(head, deq_vec) map {case (d,q) => d.bits := q}
io.deq.valid := deq_valids.reduce(_||_)
//-------------------------------------------------------------
// **** Update State ****
//-------------------------------------------------------------
when (do_enq) {
tail := enq_idx
when (in_mask.reduce(_||_)) {
maybe_full := true.B
}
}
when (do_deq) {
head := inc(head)
maybe_full := false.B
}
when (io.clear) {
head := 1.U
tail := 1.U
maybe_full := false.B
}
// TODO Is this necessary?
when (reset.asBool) {
io.deq.bits.uops map { u => u.valid := false.B }
}
}
| module FetchBuffer_1( // @[fetch-buffer.scala:40:7]
input clock, // @[fetch-buffer.scala:40:7]
input reset, // @[fetch-buffer.scala:40:7]
output io_enq_ready, // @[fetch-buffer.scala:45:14]
input io_enq_valid, // @[fetch-buffer.scala:45:14]
input [39:0] io_enq_bits_pc, // @[fetch-buffer.scala:45:14]
input [39:0] io_enq_bits_next_pc, // @[fetch-buffer.scala:45:14]
input io_enq_bits_edge_inst_0, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_insts_0, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_insts_1, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_insts_2, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_insts_3, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_exp_insts_0, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_exp_insts_1, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_exp_insts_2, // @[fetch-buffer.scala:45:14]
input [31:0] io_enq_bits_exp_insts_3, // @[fetch-buffer.scala:45:14]
input [7:0] io_enq_bits_sfb_masks_0, // @[fetch-buffer.scala:45:14]
input [7:0] io_enq_bits_sfb_masks_1, // @[fetch-buffer.scala:45:14]
input [7:0] io_enq_bits_sfb_masks_2, // @[fetch-buffer.scala:45:14]
input [7:0] io_enq_bits_sfb_masks_3, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_sfb_dests_0, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_sfb_dests_1, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_sfb_dests_2, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_sfb_dests_3, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowable_mask_0, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowable_mask_1, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowable_mask_2, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowable_mask_3, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowed_mask_0, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowed_mask_1, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowed_mask_2, // @[fetch-buffer.scala:45:14]
input io_enq_bits_shadowed_mask_3, // @[fetch-buffer.scala:45:14]
input io_enq_bits_cfi_idx_valid, // @[fetch-buffer.scala:45:14]
input [1:0] io_enq_bits_cfi_idx_bits, // @[fetch-buffer.scala:45:14]
input [2:0] io_enq_bits_cfi_type, // @[fetch-buffer.scala:45:14]
input io_enq_bits_cfi_is_call, // @[fetch-buffer.scala:45:14]
input io_enq_bits_cfi_is_ret, // @[fetch-buffer.scala:45:14]
input io_enq_bits_cfi_npc_plus4, // @[fetch-buffer.scala:45:14]
input [39:0] io_enq_bits_ras_top, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_ftq_idx, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_mask, // @[fetch-buffer.scala:45:14]
input [3:0] io_enq_bits_br_mask, // @[fetch-buffer.scala:45:14]
input [63:0] io_enq_bits_ghist_old_history, // @[fetch-buffer.scala:45:14]
input io_enq_bits_ghist_current_saw_branch_not_taken, // @[fetch-buffer.scala:45:14]
input io_enq_bits_ghist_new_saw_branch_not_taken, // @[fetch-buffer.scala:45:14]
input io_enq_bits_ghist_new_saw_branch_taken, // @[fetch-buffer.scala:45:14]
input [4:0] io_enq_bits_ghist_ras_idx, // @[fetch-buffer.scala:45:14]
input io_enq_bits_lhist_0, // @[fetch-buffer.scala:45:14]
input io_enq_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14]
input io_enq_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_debug_if_oh_0, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_debug_if_oh_1, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_debug_if_oh_2, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_debug_if_oh_3, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_xcpt_if_oh_0, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_xcpt_if_oh_1, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_xcpt_if_oh_2, // @[fetch-buffer.scala:45:14]
input io_enq_bits_bp_xcpt_if_oh_3, // @[fetch-buffer.scala:45:14]
input io_enq_bits_end_half_valid, // @[fetch-buffer.scala:45:14]
input [15:0] io_enq_bits_end_half_bits, // @[fetch-buffer.scala:45:14]
input [119:0] io_enq_bits_bpd_meta_0, // @[fetch-buffer.scala:45:14]
input [1:0] io_enq_bits_fsrc, // @[fetch-buffer.scala:45:14]
input [1:0] io_enq_bits_tsrc, // @[fetch-buffer.scala:45:14]
input io_deq_ready, // @[fetch-buffer.scala:45:14]
output io_deq_valid, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_valid, // @[fetch-buffer.scala:45:14]
output [31:0] io_deq_bits_uops_0_bits_inst, // @[fetch-buffer.scala:45:14]
output [31:0] io_deq_bits_uops_0_bits_debug_inst, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_is_rvc, // @[fetch-buffer.scala:45:14]
output [39:0] io_deq_bits_uops_0_bits_debug_pc, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_is_sfb, // @[fetch-buffer.scala:45:14]
output [3:0] io_deq_bits_uops_0_bits_ftq_idx, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_edge_inst, // @[fetch-buffer.scala:45:14]
output [5:0] io_deq_bits_uops_0_bits_pc_lob, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_taken, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_xcpt_pf_if, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_xcpt_ae_if, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_bp_debug_if, // @[fetch-buffer.scala:45:14]
output io_deq_bits_uops_0_bits_bp_xcpt_if, // @[fetch-buffer.scala:45:14]
output [1:0] io_deq_bits_uops_0_bits_debug_fsrc, // @[fetch-buffer.scala:45:14]
input io_clear // @[fetch-buffer.scala:45:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[fetch-buffer.scala:40:7]
wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[fetch-buffer.scala:40:7]
wire [39:0] io_enq_bits_next_pc_0 = io_enq_bits_next_pc; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_edge_inst_0_0 = io_enq_bits_edge_inst_0; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_insts_0_0 = io_enq_bits_insts_0; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_insts_1_0 = io_enq_bits_insts_1; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_insts_2_0 = io_enq_bits_insts_2; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_insts_3_0 = io_enq_bits_insts_3; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_exp_insts_0_0 = io_enq_bits_exp_insts_0; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_exp_insts_1_0 = io_enq_bits_exp_insts_1; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_exp_insts_2_0 = io_enq_bits_exp_insts_2; // @[fetch-buffer.scala:40:7]
wire [31:0] io_enq_bits_exp_insts_3_0 = io_enq_bits_exp_insts_3; // @[fetch-buffer.scala:40:7]
wire [7:0] io_enq_bits_sfb_masks_0_0 = io_enq_bits_sfb_masks_0; // @[fetch-buffer.scala:40:7]
wire [7:0] io_enq_bits_sfb_masks_1_0 = io_enq_bits_sfb_masks_1; // @[fetch-buffer.scala:40:7]
wire [7:0] io_enq_bits_sfb_masks_2_0 = io_enq_bits_sfb_masks_2; // @[fetch-buffer.scala:40:7]
wire [7:0] io_enq_bits_sfb_masks_3_0 = io_enq_bits_sfb_masks_3; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_sfb_dests_0_0 = io_enq_bits_sfb_dests_0; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_sfb_dests_1_0 = io_enq_bits_sfb_dests_1; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_sfb_dests_2_0 = io_enq_bits_sfb_dests_2; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_sfb_dests_3_0 = io_enq_bits_sfb_dests_3; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowable_mask_0_0 = io_enq_bits_shadowable_mask_0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowable_mask_1_0 = io_enq_bits_shadowable_mask_1; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowable_mask_2_0 = io_enq_bits_shadowable_mask_2; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowable_mask_3_0 = io_enq_bits_shadowable_mask_3; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowed_mask_0_0 = io_enq_bits_shadowed_mask_0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowed_mask_1_0 = io_enq_bits_shadowed_mask_1; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowed_mask_2_0 = io_enq_bits_shadowed_mask_2; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_shadowed_mask_3_0 = io_enq_bits_shadowed_mask_3; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_cfi_idx_valid_0 = io_enq_bits_cfi_idx_valid; // @[fetch-buffer.scala:40:7]
wire [1:0] io_enq_bits_cfi_idx_bits_0 = io_enq_bits_cfi_idx_bits; // @[fetch-buffer.scala:40:7]
wire [2:0] io_enq_bits_cfi_type_0 = io_enq_bits_cfi_type; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_cfi_is_call_0 = io_enq_bits_cfi_is_call; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_cfi_is_ret_0 = io_enq_bits_cfi_is_ret; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_cfi_npc_plus4_0 = io_enq_bits_cfi_npc_plus4; // @[fetch-buffer.scala:40:7]
wire [39:0] io_enq_bits_ras_top_0 = io_enq_bits_ras_top; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_ftq_idx_0 = io_enq_bits_ftq_idx; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[fetch-buffer.scala:40:7]
wire [3:0] io_enq_bits_br_mask_0 = io_enq_bits_br_mask; // @[fetch-buffer.scala:40:7]
wire [63:0] io_enq_bits_ghist_old_history_0 = io_enq_bits_ghist_old_history; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_ghist_current_saw_branch_not_taken_0 = io_enq_bits_ghist_current_saw_branch_not_taken; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_ghist_new_saw_branch_not_taken_0 = io_enq_bits_ghist_new_saw_branch_not_taken; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_ghist_new_saw_branch_taken_0 = io_enq_bits_ghist_new_saw_branch_taken; // @[fetch-buffer.scala:40:7]
wire [4:0] io_enq_bits_ghist_ras_idx_0 = io_enq_bits_ghist_ras_idx; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_lhist_0_0 = io_enq_bits_lhist_0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_xcpt_pf_if_0 = io_enq_bits_xcpt_pf_if; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_xcpt_ae_if_0 = io_enq_bits_xcpt_ae_if; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_debug_if_oh_0_0 = io_enq_bits_bp_debug_if_oh_0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_debug_if_oh_1_0 = io_enq_bits_bp_debug_if_oh_1; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_debug_if_oh_2_0 = io_enq_bits_bp_debug_if_oh_2; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_debug_if_oh_3_0 = io_enq_bits_bp_debug_if_oh_3; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_xcpt_if_oh_0_0 = io_enq_bits_bp_xcpt_if_oh_0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_xcpt_if_oh_1_0 = io_enq_bits_bp_xcpt_if_oh_1; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_xcpt_if_oh_2_0 = io_enq_bits_bp_xcpt_if_oh_2; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_bp_xcpt_if_oh_3_0 = io_enq_bits_bp_xcpt_if_oh_3; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_end_half_valid_0 = io_enq_bits_end_half_valid; // @[fetch-buffer.scala:40:7]
wire [15:0] io_enq_bits_end_half_bits_0 = io_enq_bits_end_half_bits; // @[fetch-buffer.scala:40:7]
wire [119:0] io_enq_bits_bpd_meta_0_0 = io_enq_bits_bpd_meta_0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_enq_bits_fsrc_0 = io_enq_bits_fsrc; // @[fetch-buffer.scala:40:7]
wire [1:0] io_enq_bits_tsrc_0 = io_enq_bits_tsrc; // @[fetch-buffer.scala:40:7]
wire io_deq_ready_0 = io_deq_ready; // @[fetch-buffer.scala:40:7]
wire io_clear_0 = io_clear; // @[fetch-buffer.scala:40:7]
wire [63:0] io_deq_bits_uops_0_bits_exc_cause = 64'h0; // @[fetch-buffer.scala:40:7]
wire [63:0] deq_vec_0_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_1_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_2_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_3_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_4_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_5_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_6_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] deq_vec_7_0_exc_cause = 64'h0; // @[fetch-buffer.scala:59:21]
wire [63:0] in_uops_0_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21]
wire [63:0] in_uops_1_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21]
wire [63:0] in_uops_2_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21]
wire [63:0] in_uops_3_exc_cause = 64'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] io_deq_bits_uops_0_bits_pdst = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_prs1 = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_prs2 = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_prs3 = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_stale_pdst = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_ldst = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_lrs1 = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_lrs2 = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_lrs3 = 6'h0; // @[fetch-buffer.scala:40:7]
wire [5:0] deq_vec_0_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_0_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_1_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_2_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_3_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_4_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_5_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_6_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_prs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_prs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_prs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_ldst = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_lrs1 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_lrs2 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] deq_vec_7_0_lrs3 = 6'h0; // @[fetch-buffer.scala:59:21]
wire [5:0] in_uops_0_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_prs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_prs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_prs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_stale_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_ldst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_prs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_prs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_prs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_stale_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_ldst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_prs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_prs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_prs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_stale_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_ldst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_prs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_prs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_prs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_stale_pdst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_ldst = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_lrs1 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_lrs2 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_lrs3 = 6'h0; // @[fetch-buffer.scala:88:21]
wire [11:0] io_deq_bits_uops_0_bits_csr_addr = 12'h0; // @[fetch-buffer.scala:40:7]
wire [11:0] deq_vec_0_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_1_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_2_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_3_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_4_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_5_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_6_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] deq_vec_7_0_csr_addr = 12'h0; // @[fetch-buffer.scala:59:21]
wire [11:0] in_uops_0_csr_addr = 12'h0; // @[fetch-buffer.scala:88:21]
wire [11:0] in_uops_1_csr_addr = 12'h0; // @[fetch-buffer.scala:88:21]
wire [11:0] in_uops_2_csr_addr = 12'h0; // @[fetch-buffer.scala:88:21]
wire [11:0] in_uops_3_csr_addr = 12'h0; // @[fetch-buffer.scala:88:21]
wire [19:0] io_deq_bits_uops_0_bits_imm_packed = 20'h0; // @[fetch-buffer.scala:40:7]
wire [19:0] deq_vec_0_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_1_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_2_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_3_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_4_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_5_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_6_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] deq_vec_7_0_imm_packed = 20'h0; // @[fetch-buffer.scala:59:21]
wire [19:0] in_uops_0_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21]
wire [19:0] in_uops_1_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21]
wire [19:0] in_uops_2_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21]
wire [19:0] in_uops_3_imm_packed = 20'h0; // @[fetch-buffer.scala:88:21]
wire [7:0] io_deq_bits_uops_0_bits_br_mask = 8'h0; // @[fetch-buffer.scala:40:7]
wire [7:0] deq_vec_0_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_1_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_2_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_3_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_4_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_5_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_6_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] deq_vec_7_0_br_mask = 8'h0; // @[fetch-buffer.scala:59:21]
wire [7:0] in_uops_0_br_mask = 8'h0; // @[fetch-buffer.scala:88:21]
wire [7:0] in_uops_1_br_mask = 8'h0; // @[fetch-buffer.scala:88:21]
wire [7:0] in_uops_2_br_mask = 8'h0; // @[fetch-buffer.scala:88:21]
wire [7:0] in_uops_3_br_mask = 8'h0; // @[fetch-buffer.scala:88:21]
wire io_enq_bits_sfbs_0 = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_sfbs_1 = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_sfbs_2 = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_enq_bits_sfbs_3 = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_br = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_jalr = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_jal = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_prs1_busy = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_prs2_busy = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_prs3_busy = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ppred_busy = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_exception = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_bypassable = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_mem_signed = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_fence = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_fencei = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_amo = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_uses_ldq = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_uses_stq = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_unique = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_flush_on_commit = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_ldst_val = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_frs3_en = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_fp_val = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_fp_single = 1'h0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:40:7]
wire deq_vec_0_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_0_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_1_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_2_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_3_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_4_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_5_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_6_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_br = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_jalr = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_jal = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_exception = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_bypassable = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_mem_signed = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_fence = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_fencei = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_amo = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_uses_stq = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_is_unique = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_ldst_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_frs3_en = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_fp_val = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_fp_single = 1'h0; // @[fetch-buffer.scala:59:21]
wire deq_vec_7_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:59:21]
wire in_uops_0_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_br = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_jalr = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_jal = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_exception = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_bypassable = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_fence = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_amo = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_unique = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_ldst_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_fp_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_fp_single = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_br = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_jalr = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_jal = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_exception = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_bypassable = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_fence = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_amo = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_unique = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_ldst_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_fp_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_fp_single = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_1_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_br = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_jalr = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_jal = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_exception = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_bypassable = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_fence = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_amo = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_unique = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_ldst_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_fp_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_fp_single = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_2_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ctrl_fcn_dw = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ctrl_is_load = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ctrl_is_sta = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ctrl_is_std = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_iw_p1_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_iw_p2_poisoned = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_br = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_jalr = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_jal = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_edge_inst = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_prs1_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_prs2_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_prs3_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ppred_busy = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_exception = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_bypassable = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_mem_signed = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_fence = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_fencei = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_amo = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_uses_ldq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_uses_stq = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_sys_pc2epc = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_unique = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_flush_on_commit = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ldst_is_rs1 = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_ldst_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_frs3_en = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_fp_val = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_fp_single = 1'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_3_xcpt_ma_if = 1'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] io_deq_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:40:7]
wire [4:0] io_deq_bits_uops_0_bits_rob_idx = 5'h0; // @[fetch-buffer.scala:40:7]
wire [4:0] io_deq_bits_uops_0_bits_mem_cmd = 5'h0; // @[fetch-buffer.scala:40:7]
wire [4:0] deq_vec_0_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_0_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_0_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_1_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_1_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_1_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_2_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_2_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_2_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_3_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_3_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_3_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_4_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_4_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_4_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_5_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_5_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_5_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_6_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_6_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_6_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_7_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_7_0_rob_idx = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] deq_vec_7_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:59:21]
wire [4:0] in_uops_0_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_0_rob_idx = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_0_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_1_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_1_rob_idx = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_1_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_2_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_2_rob_idx = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_2_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_3_ctrl_op_fcn = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_3_rob_idx = 5'h0; // @[fetch-buffer.scala:88:21]
wire [4:0] in_uops_3_mem_cmd = 5'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] io_deq_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_iw_state = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_rxq_idx = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_mem_size = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_dst_rtype = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_debug_tsrc = 2'h0; // @[fetch-buffer.scala:40:7]
wire [1:0] deq_vec_0_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_0_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_1_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_2_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_3_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_4_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_5_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_6_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_iw_state = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_mem_size = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] deq_vec_7_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:59:21]
wire [1:0] in_uops_0_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_iw_state = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_mem_size = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_0_debug_tsrc = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_iw_state = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_mem_size = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_1_debug_tsrc = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_iw_state = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_mem_size = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_2_debug_tsrc = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_ctrl_op1_sel = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_iw_state = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_rxq_idx = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_mem_size = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_dst_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_lrs1_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_lrs2_rtype = 2'h0; // @[fetch-buffer.scala:88:21]
wire [1:0] in_uops_3_debug_tsrc = 2'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] io_deq_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:40:7]
wire [3:0] io_deq_bits_uops_0_bits_ppred = 4'h0; // @[fetch-buffer.scala:40:7]
wire [3:0] deq_vec_0_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_0_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_1_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_1_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_2_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_2_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_3_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_3_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_4_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_4_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_5_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_5_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_6_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_6_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_7_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] deq_vec_7_0_ppred = 4'h0; // @[fetch-buffer.scala:59:21]
wire [3:0] in_uops_0_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_0_ppred = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_1_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_1_ppred = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_2_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_2_ppred = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_3_ctrl_br_type = 4'h0; // @[fetch-buffer.scala:88:21]
wire [3:0] in_uops_3_ppred = 4'h0; // @[fetch-buffer.scala:88:21]
wire [9:0] io_deq_bits_uops_0_bits_fu_code = 10'h0; // @[fetch-buffer.scala:40:7]
wire [9:0] deq_vec_0_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_1_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_2_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_3_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_4_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_5_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_6_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] deq_vec_7_0_fu_code = 10'h0; // @[fetch-buffer.scala:59:21]
wire [9:0] in_uops_0_fu_code = 10'h0; // @[fetch-buffer.scala:88:21]
wire [9:0] in_uops_1_fu_code = 10'h0; // @[fetch-buffer.scala:88:21]
wire [9:0] in_uops_2_fu_code = 10'h0; // @[fetch-buffer.scala:88:21]
wire [9:0] in_uops_3_fu_code = 10'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] io_deq_bits_uops_0_bits_iq_type = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] io_deq_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] io_deq_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] io_deq_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] io_deq_bits_uops_0_bits_br_tag = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] io_deq_bits_uops_0_bits_ldq_idx = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] io_deq_bits_uops_0_bits_stq_idx = 3'h0; // @[fetch-buffer.scala:40:7]
wire [2:0] deq_vec_0_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_0_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_0_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_0_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_0_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_0_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_0_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_1_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_2_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_3_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_4_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_5_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_6_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_iq_type = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_br_tag = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] deq_vec_7_0_stq_idx = 3'h0; // @[fetch-buffer.scala:59:21]
wire [2:0] in_uops_0_iq_type = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_0_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_0_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_0_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_0_br_tag = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_0_ldq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_0_stq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_iq_type = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_br_tag = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_ldq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_1_stq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_iq_type = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_br_tag = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_ldq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_2_stq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_iq_type = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_ctrl_op2_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_ctrl_imm_sel = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_ctrl_csr_cmd = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_br_tag = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_ldq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [2:0] in_uops_3_stq_idx = 3'h0; // @[fetch-buffer.scala:88:21]
wire [6:0] io_deq_bits_uops_0_bits_uopc = 7'h0; // @[fetch-buffer.scala:40:7]
wire [6:0] deq_vec_0_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_1_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_2_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_3_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_4_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_5_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_6_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire [6:0] deq_vec_7_0_uopc = 7'h0; // @[fetch-buffer.scala:59:21]
wire do_enq; // @[fetch-buffer.scala:82:16]
wire [6:0] in_uops_0_uopc = 7'h0; // @[fetch-buffer.scala:88:21]
wire [6:0] in_uops_1_uopc = 7'h0; // @[fetch-buffer.scala:88:21]
wire [6:0] in_uops_2_uopc = 7'h0; // @[fetch-buffer.scala:88:21]
wire [6:0] in_uops_3_uopc = 7'h0; // @[fetch-buffer.scala:88:21]
wire in_uops_0_edge_inst = io_enq_bits_edge_inst_0_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_0_debug_inst = io_enq_bits_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_1_debug_inst = io_enq_bits_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_2_debug_inst = io_enq_bits_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_3_debug_inst = io_enq_bits_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_0_inst = io_enq_bits_exp_insts_0_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_1_inst = io_enq_bits_exp_insts_1_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_2_inst = io_enq_bits_exp_insts_2_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [31:0] in_uops_3_inst = io_enq_bits_exp_insts_3_0; // @[fetch-buffer.scala:40:7, :88:21]
wire _in_uops_0_is_sfb_T = io_enq_bits_shadowed_mask_0_0; // @[fetch-buffer.scala:40:7, :103:56]
wire _in_uops_1_is_sfb_T = io_enq_bits_shadowed_mask_1_0; // @[fetch-buffer.scala:40:7, :103:56]
wire _in_uops_2_is_sfb_T = io_enq_bits_shadowed_mask_2_0; // @[fetch-buffer.scala:40:7, :103:56]
wire _in_uops_3_is_sfb_T = io_enq_bits_shadowed_mask_3_0; // @[fetch-buffer.scala:40:7, :103:56]
wire [3:0] in_uops_0_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [3:0] in_uops_1_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [3:0] in_uops_2_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [3:0] in_uops_3_ftq_idx = io_enq_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_0_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_1_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_2_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_3_xcpt_pf_if = io_enq_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_0_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_1_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_2_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_3_xcpt_ae_if = io_enq_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_0_bp_debug_if = io_enq_bits_bp_debug_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_1_bp_debug_if = io_enq_bits_bp_debug_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_2_bp_debug_if = io_enq_bits_bp_debug_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_3_bp_debug_if = io_enq_bits_bp_debug_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_0_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_0_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_1_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_1_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_2_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_2_0; // @[fetch-buffer.scala:40:7, :88:21]
wire in_uops_3_bp_xcpt_if = io_enq_bits_bp_xcpt_if_oh_3_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [1:0] in_uops_0_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [1:0] in_uops_1_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [1:0] in_uops_2_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21]
wire [1:0] in_uops_3_debug_fsrc = io_enq_bits_fsrc_0; // @[fetch-buffer.scala:40:7, :88:21]
wire deq_valids_0; // @[fetch-buffer.scala:161:53]
wire io_enq_ready_0; // @[fetch-buffer.scala:40:7]
wire [31:0] io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7]
wire [31:0] io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7]
wire [39:0] io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7]
wire [3:0] io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7]
wire [5:0] io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7]
wire [1:0] io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7]
wire io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7]
wire io_deq_valid_0; // @[fetch-buffer.scala:40:7]
reg [31:0] fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_0_0_inst = fb_uop_ram_0_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_0_0_debug_inst = fb_uop_ram_0_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_is_rvc = fb_uop_ram_0_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_0_0_debug_pc = fb_uop_ram_0_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_is_sfb = fb_uop_ram_0_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_0_0_ftq_idx = fb_uop_ram_0_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_edge_inst = fb_uop_ram_0_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_0_0_pc_lob = fb_uop_ram_0_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_taken = fb_uop_ram_0_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_xcpt_pf_if = fb_uop_ram_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_xcpt_ae_if = fb_uop_ram_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_bp_debug_if = fb_uop_ram_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_0_0_bp_xcpt_if = fb_uop_ram_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_0_0_debug_fsrc = fb_uop_ram_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_1_0_inst = fb_uop_ram_1_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_1_0_debug_inst = fb_uop_ram_1_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_is_rvc = fb_uop_ram_1_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_1_0_debug_pc = fb_uop_ram_1_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_is_sfb = fb_uop_ram_1_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_1_0_ftq_idx = fb_uop_ram_1_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_edge_inst = fb_uop_ram_1_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_1_0_pc_lob = fb_uop_ram_1_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_taken = fb_uop_ram_1_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_xcpt_pf_if = fb_uop_ram_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_xcpt_ae_if = fb_uop_ram_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_bp_debug_if = fb_uop_ram_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_1_0_bp_xcpt_if = fb_uop_ram_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_1_0_debug_fsrc = fb_uop_ram_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_2_0_inst = fb_uop_ram_2_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_2_0_debug_inst = fb_uop_ram_2_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_is_rvc = fb_uop_ram_2_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_2_0_debug_pc = fb_uop_ram_2_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_is_sfb = fb_uop_ram_2_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_2_0_ftq_idx = fb_uop_ram_2_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_edge_inst = fb_uop_ram_2_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_2_0_pc_lob = fb_uop_ram_2_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_taken = fb_uop_ram_2_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_xcpt_pf_if = fb_uop_ram_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_xcpt_ae_if = fb_uop_ram_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_bp_debug_if = fb_uop_ram_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_2_0_bp_xcpt_if = fb_uop_ram_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_2_0_debug_fsrc = fb_uop_ram_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_3_0_inst = fb_uop_ram_3_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_3_0_debug_inst = fb_uop_ram_3_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_is_rvc = fb_uop_ram_3_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_3_0_debug_pc = fb_uop_ram_3_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_is_sfb = fb_uop_ram_3_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_3_0_ftq_idx = fb_uop_ram_3_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_edge_inst = fb_uop_ram_3_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_3_0_pc_lob = fb_uop_ram_3_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_taken = fb_uop_ram_3_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_xcpt_pf_if = fb_uop_ram_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_xcpt_ae_if = fb_uop_ram_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_bp_debug_if = fb_uop_ram_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_3_0_bp_xcpt_if = fb_uop_ram_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_3_0_debug_fsrc = fb_uop_ram_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_4_0_inst = fb_uop_ram_4_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_4_0_debug_inst = fb_uop_ram_4_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_is_rvc = fb_uop_ram_4_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_4_0_debug_pc = fb_uop_ram_4_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_is_sfb = fb_uop_ram_4_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_4_0_ftq_idx = fb_uop_ram_4_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_edge_inst = fb_uop_ram_4_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_4_0_pc_lob = fb_uop_ram_4_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_taken = fb_uop_ram_4_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_xcpt_pf_if = fb_uop_ram_4_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_xcpt_ae_if = fb_uop_ram_4_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_bp_debug_if = fb_uop_ram_4_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_4_0_bp_xcpt_if = fb_uop_ram_4_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_4_0_debug_fsrc = fb_uop_ram_4_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_5_0_inst = fb_uop_ram_5_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_5_0_debug_inst = fb_uop_ram_5_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_is_rvc = fb_uop_ram_5_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_5_0_debug_pc = fb_uop_ram_5_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_is_sfb = fb_uop_ram_5_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_5_0_ftq_idx = fb_uop_ram_5_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_edge_inst = fb_uop_ram_5_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_5_0_pc_lob = fb_uop_ram_5_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_taken = fb_uop_ram_5_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_xcpt_pf_if = fb_uop_ram_5_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_xcpt_ae_if = fb_uop_ram_5_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_bp_debug_if = fb_uop_ram_5_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_5_0_bp_xcpt_if = fb_uop_ram_5_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_5_0_debug_fsrc = fb_uop_ram_5_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_6_0_inst = fb_uop_ram_6_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_6_0_debug_inst = fb_uop_ram_6_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_is_rvc = fb_uop_ram_6_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_6_0_debug_pc = fb_uop_ram_6_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_is_sfb = fb_uop_ram_6_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_6_0_ftq_idx = fb_uop_ram_6_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_edge_inst = fb_uop_ram_6_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_6_0_pc_lob = fb_uop_ram_6_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_taken = fb_uop_ram_6_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_xcpt_pf_if = fb_uop_ram_6_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_xcpt_ae_if = fb_uop_ram_6_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_bp_debug_if = fb_uop_ram_6_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_6_0_bp_xcpt_if = fb_uop_ram_6_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_6_0_debug_fsrc = fb_uop_ram_6_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_7_0_inst = fb_uop_ram_7_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [31:0] fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16]
wire [31:0] deq_vec_7_0_debug_inst = fb_uop_ram_7_debug_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_is_rvc = fb_uop_ram_7_is_rvc; // @[fetch-buffer.scala:57:16, :59:21]
reg [39:0] fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16]
wire [39:0] deq_vec_7_0_debug_pc = fb_uop_ram_7_debug_pc; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_is_sfb = fb_uop_ram_7_is_sfb; // @[fetch-buffer.scala:57:16, :59:21]
reg [3:0] fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16]
wire [3:0] deq_vec_7_0_ftq_idx = fb_uop_ram_7_ftq_idx; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_edge_inst = fb_uop_ram_7_edge_inst; // @[fetch-buffer.scala:57:16, :59:21]
reg [5:0] fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16]
wire [5:0] deq_vec_7_0_pc_lob = fb_uop_ram_7_pc_lob; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_taken = fb_uop_ram_7_taken; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_xcpt_pf_if = fb_uop_ram_7_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_xcpt_ae_if = fb_uop_ram_7_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_bp_debug_if = fb_uop_ram_7_bp_debug_if; // @[fetch-buffer.scala:57:16, :59:21]
reg fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16]
wire deq_vec_7_0_bp_xcpt_if = fb_uop_ram_7_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :59:21]
reg [1:0] fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16]
wire [1:0] deq_vec_7_0_debug_fsrc = fb_uop_ram_7_debug_fsrc; // @[fetch-buffer.scala:57:16, :59:21]
reg [7:0] head; // @[fetch-buffer.scala:61:21]
reg [7:0] tail; // @[fetch-buffer.scala:62:21]
wire [7:0] enq_idxs_0 = tail; // @[fetch-buffer.scala:62:21, :128:22]
reg maybe_full; // @[fetch-buffer.scala:64:27]
wire [6:0] _might_hit_head_T = tail[6:0]; // @[fetch-buffer.scala:62:21, :75:11]
wire _might_hit_head_T_1 = tail[7]; // @[fetch-buffer.scala:62:21, :75:24]
wire _at_head_T_7 = tail[7]; // @[fetch-buffer.scala:62:21, :75:24, :80:31]
wire [7:0] _might_hit_head_T_2 = {_might_hit_head_T, _might_hit_head_T_1}; // @[fetch-buffer.scala:75:{8,11,24}]
wire _might_hit_head_T_3 = _might_hit_head_T_2[0]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_0 = _might_hit_head_T_3; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_4 = _might_hit_head_T_2[1]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1 = _might_hit_head_T_4; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_5 = _might_hit_head_T_2[2]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2 = _might_hit_head_T_5; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_6 = _might_hit_head_T_2[3]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_3 = _might_hit_head_T_6; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_7 = _might_hit_head_T_2[4]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_4 = _might_hit_head_T_7; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_8 = _might_hit_head_T_2[5]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_5 = _might_hit_head_T_8; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_9 = _might_hit_head_T_2[6]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_6 = _might_hit_head_T_9; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_10 = _might_hit_head_T_2[7]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_7 = _might_hit_head_T_10; // @[fetch-buffer.scala:78:{61,82}]
wire [1:0] might_hit_head_lo_lo = {_might_hit_head_WIRE_1, _might_hit_head_WIRE_0}; // @[fetch-buffer.scala:78:61, :79:63]
wire [1:0] might_hit_head_lo_hi = {_might_hit_head_WIRE_3, _might_hit_head_WIRE_2}; // @[fetch-buffer.scala:78:61, :79:63]
wire [3:0] might_hit_head_lo = {might_hit_head_lo_hi, might_hit_head_lo_lo}; // @[fetch-buffer.scala:79:63]
wire [1:0] might_hit_head_hi_lo = {_might_hit_head_WIRE_5, _might_hit_head_WIRE_4}; // @[fetch-buffer.scala:78:61, :79:63]
wire [1:0] might_hit_head_hi_hi = {_might_hit_head_WIRE_7, _might_hit_head_WIRE_6}; // @[fetch-buffer.scala:78:61, :79:63]
wire [3:0] might_hit_head_hi = {might_hit_head_hi_hi, might_hit_head_hi_lo}; // @[fetch-buffer.scala:79:63]
wire [7:0] _might_hit_head_T_11 = {might_hit_head_hi, might_hit_head_lo}; // @[fetch-buffer.scala:79:63]
wire [5:0] _might_hit_head_T_12 = tail[5:0]; // @[fetch-buffer.scala:62:21, :75:11]
wire [1:0] _might_hit_head_T_13 = tail[7:6]; // @[fetch-buffer.scala:62:21, :75:24]
wire [7:0] _might_hit_head_T_14 = {_might_hit_head_T_12, _might_hit_head_T_13}; // @[fetch-buffer.scala:75:{8,11,24}]
wire _might_hit_head_T_15 = _might_hit_head_T_14[0]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_0 = _might_hit_head_T_15; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_16 = _might_hit_head_T_14[1]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_1 = _might_hit_head_T_16; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_17 = _might_hit_head_T_14[2]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_2 = _might_hit_head_T_17; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_18 = _might_hit_head_T_14[3]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_3 = _might_hit_head_T_18; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_19 = _might_hit_head_T_14[4]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_4 = _might_hit_head_T_19; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_20 = _might_hit_head_T_14[5]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_5 = _might_hit_head_T_20; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_21 = _might_hit_head_T_14[6]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_6 = _might_hit_head_T_21; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_22 = _might_hit_head_T_14[7]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_1_7 = _might_hit_head_T_22; // @[fetch-buffer.scala:78:{61,82}]
wire [1:0] might_hit_head_lo_lo_1 = {_might_hit_head_WIRE_1_1, _might_hit_head_WIRE_1_0}; // @[fetch-buffer.scala:78:61, :79:63]
wire [1:0] might_hit_head_lo_hi_1 = {_might_hit_head_WIRE_1_3, _might_hit_head_WIRE_1_2}; // @[fetch-buffer.scala:78:61, :79:63]
wire [3:0] might_hit_head_lo_1 = {might_hit_head_lo_hi_1, might_hit_head_lo_lo_1}; // @[fetch-buffer.scala:79:63]
wire [1:0] might_hit_head_hi_lo_1 = {_might_hit_head_WIRE_1_5, _might_hit_head_WIRE_1_4}; // @[fetch-buffer.scala:78:61, :79:63]
wire [1:0] might_hit_head_hi_hi_1 = {_might_hit_head_WIRE_1_7, _might_hit_head_WIRE_1_6}; // @[fetch-buffer.scala:78:61, :79:63]
wire [3:0] might_hit_head_hi_1 = {might_hit_head_hi_hi_1, might_hit_head_hi_lo_1}; // @[fetch-buffer.scala:79:63]
wire [7:0] _might_hit_head_T_23 = {might_hit_head_hi_1, might_hit_head_lo_1}; // @[fetch-buffer.scala:79:63]
wire [4:0] _might_hit_head_T_24 = tail[4:0]; // @[fetch-buffer.scala:62:21, :75:11]
wire [2:0] _might_hit_head_T_25 = tail[7:5]; // @[fetch-buffer.scala:62:21, :75:24]
wire [7:0] _might_hit_head_T_26 = {_might_hit_head_T_24, _might_hit_head_T_25}; // @[fetch-buffer.scala:75:{8,11,24}]
wire _might_hit_head_T_27 = _might_hit_head_T_26[0]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_0 = _might_hit_head_T_27; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_28 = _might_hit_head_T_26[1]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_1 = _might_hit_head_T_28; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_29 = _might_hit_head_T_26[2]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_2 = _might_hit_head_T_29; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_30 = _might_hit_head_T_26[3]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_3 = _might_hit_head_T_30; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_31 = _might_hit_head_T_26[4]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_4 = _might_hit_head_T_31; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_32 = _might_hit_head_T_26[5]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_5 = _might_hit_head_T_32; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_33 = _might_hit_head_T_26[6]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_6 = _might_hit_head_T_33; // @[fetch-buffer.scala:78:{61,82}]
wire _might_hit_head_T_34 = _might_hit_head_T_26[7]; // @[fetch-buffer.scala:75:8, :78:82]
wire _might_hit_head_WIRE_2_7 = _might_hit_head_T_34; // @[fetch-buffer.scala:78:{61,82}]
wire [1:0] might_hit_head_lo_lo_2 = {_might_hit_head_WIRE_2_1, _might_hit_head_WIRE_2_0}; // @[fetch-buffer.scala:78:61, :79:63]
wire [1:0] might_hit_head_lo_hi_2 = {_might_hit_head_WIRE_2_3, _might_hit_head_WIRE_2_2}; // @[fetch-buffer.scala:78:61, :79:63]
wire [3:0] might_hit_head_lo_2 = {might_hit_head_lo_hi_2, might_hit_head_lo_lo_2}; // @[fetch-buffer.scala:79:63]
wire [1:0] might_hit_head_hi_lo_2 = {_might_hit_head_WIRE_2_5, _might_hit_head_WIRE_2_4}; // @[fetch-buffer.scala:78:61, :79:63]
wire [1:0] might_hit_head_hi_hi_2 = {_might_hit_head_WIRE_2_7, _might_hit_head_WIRE_2_6}; // @[fetch-buffer.scala:78:61, :79:63]
wire [3:0] might_hit_head_hi_2 = {might_hit_head_hi_hi_2, might_hit_head_hi_lo_2}; // @[fetch-buffer.scala:79:63]
wire [7:0] _might_hit_head_T_35 = {might_hit_head_hi_2, might_hit_head_lo_2}; // @[fetch-buffer.scala:79:63]
wire [7:0] _might_hit_head_T_36 = head & _might_hit_head_T_11; // @[fetch-buffer.scala:61:21, :79:{63,88}]
wire [7:0] _might_hit_head_T_37 = head & _might_hit_head_T_23; // @[fetch-buffer.scala:61:21, :79:{63,88}]
wire [7:0] _might_hit_head_T_38 = head & _might_hit_head_T_35; // @[fetch-buffer.scala:61:21, :79:{63,88}]
wire [7:0] _might_hit_head_T_39 = _might_hit_head_T_36 | _might_hit_head_T_37; // @[fetch-buffer.scala:79:{88,104}]
wire [7:0] _might_hit_head_T_40 = _might_hit_head_T_39 | _might_hit_head_T_38; // @[fetch-buffer.scala:79:{88,104}]
wire might_hit_head = |_might_hit_head_T_40; // @[fetch-buffer.scala:79:{104,108}]
wire _at_head_T = tail[0]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_0 = _at_head_T; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_T_1 = tail[1]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_1 = _at_head_T_1; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_T_2 = tail[2]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_2 = _at_head_T_2; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_T_3 = tail[3]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_3 = _at_head_T_3; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_T_4 = tail[4]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_4 = _at_head_T_4; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_T_5 = tail[5]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_5 = _at_head_T_5; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_T_6 = tail[6]; // @[fetch-buffer.scala:62:21, :80:31]
wire _at_head_WIRE_6 = _at_head_T_6; // @[fetch-buffer.scala:80:{25,31}]
wire _at_head_WIRE_7 = _at_head_T_7; // @[fetch-buffer.scala:80:{25,31}]
wire [1:0] at_head_lo_lo = {_at_head_WIRE_1, _at_head_WIRE_0}; // @[fetch-buffer.scala:80:25, :81:29]
wire [1:0] at_head_lo_hi = {_at_head_WIRE_3, _at_head_WIRE_2}; // @[fetch-buffer.scala:80:25, :81:29]
wire [3:0] at_head_lo = {at_head_lo_hi, at_head_lo_lo}; // @[fetch-buffer.scala:81:29]
wire [1:0] at_head_hi_lo = {_at_head_WIRE_5, _at_head_WIRE_4}; // @[fetch-buffer.scala:80:25, :81:29]
wire [1:0] at_head_hi_hi = {_at_head_WIRE_7, _at_head_WIRE_6}; // @[fetch-buffer.scala:80:25, :81:29]
wire [3:0] at_head_hi = {at_head_hi_hi, at_head_hi_lo}; // @[fetch-buffer.scala:81:29]
wire [7:0] _at_head_T_8 = {at_head_hi, at_head_lo}; // @[fetch-buffer.scala:81:29]
wire [7:0] _at_head_T_9 = _at_head_T_8 & head; // @[fetch-buffer.scala:61:21, :81:{29,36}]
wire at_head = |_at_head_T_9; // @[fetch-buffer.scala:81:{36,44}]
wire _do_enq_T = at_head & maybe_full; // @[fetch-buffer.scala:64:27, :81:44, :82:26]
wire _do_enq_T_1 = _do_enq_T | might_hit_head; // @[fetch-buffer.scala:79:108, :82:{26,40}]
assign do_enq = ~_do_enq_T_1; // @[fetch-buffer.scala:82:{16,40}]
assign io_enq_ready_0 = do_enq; // @[fetch-buffer.scala:40:7, :82:16]
wire _in_mask_0_T_1; // @[fetch-buffer.scala:98:49]
wire _in_mask_1_T_1; // @[fetch-buffer.scala:98:49]
wire _in_mask_2_T_1; // @[fetch-buffer.scala:98:49]
wire _in_mask_3_T_1; // @[fetch-buffer.scala:98:49]
wire in_mask_0; // @[fetch-buffer.scala:87:21]
wire in_mask_1; // @[fetch-buffer.scala:87:21]
wire in_mask_2; // @[fetch-buffer.scala:87:21]
wire in_mask_3; // @[fetch-buffer.scala:87:21]
wire _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:115:62]
wire _in_uops_0_taken_T_1; // @[fetch-buffer.scala:116:69]
wire _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:115:62]
wire [39:0] pc_1; // @[fetch-buffer.scala:95:43]
wire _in_uops_1_taken_T_1; // @[fetch-buffer.scala:116:69]
wire _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:115:62]
wire [39:0] pc_2; // @[fetch-buffer.scala:95:43]
wire _in_uops_2_taken_T_1; // @[fetch-buffer.scala:116:69]
wire _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:115:62]
wire [39:0] pc_3; // @[fetch-buffer.scala:95:43]
wire _in_uops_3_taken_T_1; // @[fetch-buffer.scala:116:69]
wire in_uops_0_is_rvc; // @[fetch-buffer.scala:88:21]
wire [39:0] in_uops_0_debug_pc; // @[fetch-buffer.scala:88:21]
wire in_uops_0_is_sfb; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_0_pc_lob; // @[fetch-buffer.scala:88:21]
wire in_uops_0_taken; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_rvc; // @[fetch-buffer.scala:88:21]
wire [39:0] in_uops_1_debug_pc; // @[fetch-buffer.scala:88:21]
wire in_uops_1_is_sfb; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_1_pc_lob; // @[fetch-buffer.scala:88:21]
wire in_uops_1_taken; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_rvc; // @[fetch-buffer.scala:88:21]
wire [39:0] in_uops_2_debug_pc; // @[fetch-buffer.scala:88:21]
wire in_uops_2_is_sfb; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_2_pc_lob; // @[fetch-buffer.scala:88:21]
wire in_uops_2_taken; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_rvc; // @[fetch-buffer.scala:88:21]
wire [39:0] in_uops_3_debug_pc; // @[fetch-buffer.scala:88:21]
wire in_uops_3_is_sfb; // @[fetch-buffer.scala:88:21]
wire [5:0] in_uops_3_pc_lob; // @[fetch-buffer.scala:88:21]
wire in_uops_3_taken; // @[fetch-buffer.scala:88:21]
wire [39:0] _pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _pc_T_1 = {_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _pc_T_2 = ~_pc_T_1; // @[frontend.scala:160:{31,39}]
wire [40:0] _pc_T_3 = {1'h0, _pc_T_2}; // @[frontend.scala:160:31]
wire [39:0] pc = _pc_T_3[39:0]; // @[fetch-buffer.scala:95:43]
wire _in_mask_0_T = io_enq_bits_mask_0[0]; // @[fetch-buffer.scala:40:7, :98:68]
assign _in_mask_0_T_1 = io_enq_valid_0 & _in_mask_0_T; // @[fetch-buffer.scala:40:7, :98:{49,68}]
assign in_mask_0 = _in_mask_0_T_1; // @[fetch-buffer.scala:87:21, :98:49]
assign in_uops_0_is_sfb = _in_uops_0_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56]
wire [39:0] _in_uops_0_debug_pc_T = ~io_enq_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _in_uops_0_debug_pc_T_1 = {_in_uops_0_debug_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _in_uops_0_debug_pc_T_2 = ~_in_uops_0_debug_pc_T_1; // @[frontend.scala:160:{31,39}]
wire [40:0] _in_uops_0_debug_pc_T_3 = {1'h0, _in_uops_0_debug_pc_T_2}; // @[frontend.scala:160:31]
wire [39:0] _in_uops_0_debug_pc_T_4 = _in_uops_0_debug_pc_T_3[39:0]; // @[fetch-buffer.scala:107:61]
wire [40:0] _in_uops_0_debug_pc_T_5 = {1'h0, _in_uops_0_debug_pc_T_4} - 41'h2; // @[fetch-buffer.scala:107:{61,81}]
wire [39:0] _in_uops_0_debug_pc_T_6 = _in_uops_0_debug_pc_T_5[39:0]; // @[fetch-buffer.scala:107:81]
assign in_uops_0_debug_pc = io_enq_bits_edge_inst_0_0 ? _in_uops_0_debug_pc_T_6 : pc; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :100:33, :106:41, :107:{32,81}]
wire [39:0] _in_uops_0_pc_lob_T = ~io_enq_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _in_uops_0_pc_lob_T_1 = {_in_uops_0_pc_lob_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _in_uops_0_pc_lob_T_2 = ~_in_uops_0_pc_lob_T_1; // @[frontend.scala:160:{31,39}]
wire [40:0] _in_uops_0_pc_lob_T_3 = {1'h0, _in_uops_0_pc_lob_T_2}; // @[frontend.scala:160:31]
wire [39:0] _in_uops_0_pc_lob_T_4 = _in_uops_0_pc_lob_T_3[39:0]; // @[fetch-buffer.scala:108:61]
assign in_uops_0_pc_lob = io_enq_bits_edge_inst_0_0 ? _in_uops_0_pc_lob_T_4[5:0] : pc[5:0]; // @[fetch-buffer.scala:40:7, :88:21, :95:43, :101:33, :106:41, :108:{32,61}]
wire [1:0] _in_uops_0_is_rvc_T = io_enq_bits_insts_0_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56]
assign _in_uops_0_is_rvc_T_1 = _in_uops_0_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}]
assign in_uops_0_is_rvc = _in_uops_0_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62]
wire _in_uops_0_taken_T = io_enq_bits_cfi_idx_bits_0 == 2'h0; // @[fetch-buffer.scala:40:7, :116:61]
assign _in_uops_0_taken_T_1 = _in_uops_0_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}]
assign in_uops_0_taken = _in_uops_0_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69]
wire [39:0] _pc_T_4 = ~io_enq_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _pc_T_5 = {_pc_T_4[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _pc_T_6 = ~_pc_T_5; // @[frontend.scala:160:{31,39}]
wire [40:0] _pc_T_7 = {1'h0, _pc_T_6} + 41'h2; // @[frontend.scala:160:31]
assign pc_1 = _pc_T_7[39:0]; // @[fetch-buffer.scala:95:43]
assign in_uops_1_debug_pc = pc_1; // @[fetch-buffer.scala:88:21, :95:43]
wire _in_mask_1_T = io_enq_bits_mask_0[1]; // @[fetch-buffer.scala:40:7, :98:68]
assign _in_mask_1_T_1 = io_enq_valid_0 & _in_mask_1_T; // @[fetch-buffer.scala:40:7, :98:{49,68}]
assign in_mask_1 = _in_mask_1_T_1; // @[fetch-buffer.scala:87:21, :98:49]
assign in_uops_1_pc_lob = pc_1[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33]
assign in_uops_1_is_sfb = _in_uops_1_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56]
wire [1:0] _in_uops_1_is_rvc_T = io_enq_bits_insts_1_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56]
assign _in_uops_1_is_rvc_T_1 = _in_uops_1_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}]
assign in_uops_1_is_rvc = _in_uops_1_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62]
wire _in_uops_1_taken_T = io_enq_bits_cfi_idx_bits_0 == 2'h1; // @[fetch-buffer.scala:40:7, :116:61]
assign _in_uops_1_taken_T_1 = _in_uops_1_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}]
assign in_uops_1_taken = _in_uops_1_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69]
wire [39:0] _pc_T_8 = ~io_enq_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _pc_T_9 = {_pc_T_8[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _pc_T_10 = ~_pc_T_9; // @[frontend.scala:160:{31,39}]
wire [40:0] _pc_T_11 = {1'h0, _pc_T_10} + 41'h4; // @[frontend.scala:160:31]
assign pc_2 = _pc_T_11[39:0]; // @[fetch-buffer.scala:95:43]
assign in_uops_2_debug_pc = pc_2; // @[fetch-buffer.scala:88:21, :95:43]
wire _in_mask_2_T = io_enq_bits_mask_0[2]; // @[fetch-buffer.scala:40:7, :98:68]
assign _in_mask_2_T_1 = io_enq_valid_0 & _in_mask_2_T; // @[fetch-buffer.scala:40:7, :98:{49,68}]
assign in_mask_2 = _in_mask_2_T_1; // @[fetch-buffer.scala:87:21, :98:49]
assign in_uops_2_pc_lob = pc_2[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33]
assign in_uops_2_is_sfb = _in_uops_2_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56]
wire [1:0] _in_uops_2_is_rvc_T = io_enq_bits_insts_2_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56]
assign _in_uops_2_is_rvc_T_1 = _in_uops_2_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}]
assign in_uops_2_is_rvc = _in_uops_2_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62]
wire _in_uops_2_taken_T = io_enq_bits_cfi_idx_bits_0 == 2'h2; // @[fetch-buffer.scala:40:7, :116:61]
assign _in_uops_2_taken_T_1 = _in_uops_2_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}]
assign in_uops_2_taken = _in_uops_2_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69]
wire [39:0] _pc_T_12 = ~io_enq_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _pc_T_13 = {_pc_T_12[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _pc_T_14 = ~_pc_T_13; // @[frontend.scala:160:{31,39}]
wire [40:0] _pc_T_15 = {1'h0, _pc_T_14} + 41'h6; // @[frontend.scala:160:31]
assign pc_3 = _pc_T_15[39:0]; // @[fetch-buffer.scala:95:43]
assign in_uops_3_debug_pc = pc_3; // @[fetch-buffer.scala:88:21, :95:43]
wire _in_mask_3_T = io_enq_bits_mask_0[3]; // @[fetch-buffer.scala:40:7, :98:68]
assign _in_mask_3_T_1 = io_enq_valid_0 & _in_mask_3_T; // @[fetch-buffer.scala:40:7, :98:{49,68}]
assign in_mask_3 = _in_mask_3_T_1; // @[fetch-buffer.scala:87:21, :98:49]
assign in_uops_3_pc_lob = pc_3[5:0]; // @[fetch-buffer.scala:88:21, :95:43, :101:33]
assign in_uops_3_is_sfb = _in_uops_3_is_sfb_T; // @[fetch-buffer.scala:88:21, :103:56]
wire [1:0] _in_uops_3_is_rvc_T = io_enq_bits_insts_3_0[1:0]; // @[fetch-buffer.scala:40:7, :115:56]
assign _in_uops_3_is_rvc_T_1 = _in_uops_3_is_rvc_T != 2'h3; // @[fetch-buffer.scala:115:{56,62}]
assign in_uops_3_is_rvc = _in_uops_3_is_rvc_T_1; // @[fetch-buffer.scala:88:21, :115:62]
wire _in_uops_3_taken_T = &io_enq_bits_cfi_idx_bits_0; // @[fetch-buffer.scala:40:7, :116:61]
assign _in_uops_3_taken_T_1 = _in_uops_3_taken_T & io_enq_bits_cfi_idx_valid_0; // @[fetch-buffer.scala:40:7, :116:{61,69}]
assign in_uops_3_taken = _in_uops_3_taken_T_1; // @[fetch-buffer.scala:88:21, :116:69]
wire [7:0] enq_idxs_1; // @[fetch-buffer.scala:128:22]
wire [7:0] enq_idxs_2; // @[fetch-buffer.scala:128:22]
wire [7:0] enq_idxs_3; // @[fetch-buffer.scala:128:22]
wire [7:0] _T_2 = {_might_hit_head_T, tail[7]}; // @[fetch-buffer.scala:62:21, :75:{11,24}, :132:8]
assign enq_idxs_1 = in_mask_0 ? _T_2 : tail; // @[fetch-buffer.scala:62:21, :87:21, :128:22, :132:8, :138:18]
wire [7:0] _T_6 = {enq_idxs_1[6:0], enq_idxs_1[7]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}]
assign enq_idxs_2 = in_mask_1 ? _T_6 : enq_idxs_1; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18]
wire [7:0] _T_10 = {enq_idxs_2[6:0], enq_idxs_2[7]}; // @[fetch-buffer.scala:128:22, :132:{8,12,24}]
assign enq_idxs_3 = in_mask_2 ? _T_10 : enq_idxs_2; // @[fetch-buffer.scala:87:21, :128:22, :132:8, :138:18]
wire _tail_collisions_T = head[0]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_1 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_2 = _tail_collisions_T_1; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_3 = _tail_collisions_T & _tail_collisions_T_2; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_0 = _tail_collisions_T_3; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_4 = head[1]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_5 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_6 = _tail_collisions_T_5; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_7 = _tail_collisions_T_4 & _tail_collisions_T_6; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_1 = _tail_collisions_T_7; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_8 = head[2]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_9 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_10 = _tail_collisions_T_9; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_11 = _tail_collisions_T_8 & _tail_collisions_T_10; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_2 = _tail_collisions_T_11; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_12 = head[3]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_13 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_14 = _tail_collisions_T_13; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_15 = _tail_collisions_T_12 & _tail_collisions_T_14; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_3 = _tail_collisions_T_15; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_16 = head[4]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_17 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_18 = _tail_collisions_T_17; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_19 = _tail_collisions_T_16 & _tail_collisions_T_18; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_4 = _tail_collisions_T_19; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_20 = head[5]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_21 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_22 = _tail_collisions_T_21; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_23 = _tail_collisions_T_20 & _tail_collisions_T_22; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_5 = _tail_collisions_T_23; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_24 = head[6]; // @[fetch-buffer.scala:61:21, :155:31]
wire _tail_collisions_T_25 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_26 = _tail_collisions_T_25; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_27 = _tail_collisions_T_24 & _tail_collisions_T_26; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_6 = _tail_collisions_T_27; // @[fetch-buffer.scala:154:32, :155:45]
wire _tail_collisions_T_28 = head[7]; // @[fetch-buffer.scala:61:21, :155:31]
wire _head_T_1 = head[7]; // @[fetch-buffer.scala:61:21, :132:24, :155:31]
wire _tail_collisions_T_29 = ~maybe_full; // @[fetch-buffer.scala:64:27, :155:49]
wire _tail_collisions_T_30 = _tail_collisions_T_29; // @[fetch-buffer.scala:155:{49,61}]
wire _tail_collisions_T_31 = _tail_collisions_T_28 & _tail_collisions_T_30; // @[fetch-buffer.scala:155:{31,45,61}]
wire _tail_collisions_WIRE_7 = _tail_collisions_T_31; // @[fetch-buffer.scala:154:32, :155:45]
wire [1:0] tail_collisions_lo_lo = {_tail_collisions_WIRE_1, _tail_collisions_WIRE_0}; // @[fetch-buffer.scala:154:32, :155:90]
wire [1:0] tail_collisions_lo_hi = {_tail_collisions_WIRE_3, _tail_collisions_WIRE_2}; // @[fetch-buffer.scala:154:32, :155:90]
wire [3:0] tail_collisions_lo = {tail_collisions_lo_hi, tail_collisions_lo_lo}; // @[fetch-buffer.scala:155:90]
wire [1:0] tail_collisions_hi_lo = {_tail_collisions_WIRE_5, _tail_collisions_WIRE_4}; // @[fetch-buffer.scala:154:32, :155:90]
wire [1:0] tail_collisions_hi_hi = {_tail_collisions_WIRE_7, _tail_collisions_WIRE_6}; // @[fetch-buffer.scala:154:32, :155:90]
wire [3:0] tail_collisions_hi = {tail_collisions_hi_hi, tail_collisions_hi_lo}; // @[fetch-buffer.scala:155:90]
wire [7:0] _tail_collisions_T_32 = {tail_collisions_hi, tail_collisions_lo}; // @[fetch-buffer.scala:155:90]
wire [7:0] tail_collisions = _tail_collisions_T_32 & tail; // @[fetch-buffer.scala:62:21, :155:{90,97}]
wire _slot_will_hit_tail_T = tail_collisions[0]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_1 = tail_collisions[1]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_2 = tail_collisions[2]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_3 = tail_collisions[3]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_4 = tail_collisions[4]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_5 = tail_collisions[5]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_6 = tail_collisions[6]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_7 = tail_collisions[7]; // @[fetch-buffer.scala:155:97, :156:70]
wire _slot_will_hit_tail_T_8 = _slot_will_hit_tail_T | _slot_will_hit_tail_T_1; // @[fetch-buffer.scala:156:{70,112}]
wire _slot_will_hit_tail_T_9 = _slot_will_hit_tail_T_8 | _slot_will_hit_tail_T_2; // @[fetch-buffer.scala:156:{70,112}]
wire _slot_will_hit_tail_T_10 = _slot_will_hit_tail_T_9 | _slot_will_hit_tail_T_3; // @[fetch-buffer.scala:156:{70,112}]
wire _slot_will_hit_tail_T_11 = _slot_will_hit_tail_T_10 | _slot_will_hit_tail_T_4; // @[fetch-buffer.scala:156:{70,112}]
wire _slot_will_hit_tail_T_12 = _slot_will_hit_tail_T_11 | _slot_will_hit_tail_T_5; // @[fetch-buffer.scala:156:{70,112}]
wire _slot_will_hit_tail_T_13 = _slot_will_hit_tail_T_12 | _slot_will_hit_tail_T_6; // @[fetch-buffer.scala:156:{70,112}]
wire slot_will_hit_tail = _slot_will_hit_tail_T_13 | _slot_will_hit_tail_T_7; // @[fetch-buffer.scala:156:{70,112}]
wire will_hit_tail = slot_will_hit_tail; // @[fetch-buffer.scala:156:112, :157:42]
wire _do_deq_T = ~will_hit_tail; // @[fetch-buffer.scala:157:42, :159:32]
wire do_deq = io_deq_ready_0 & _do_deq_T; // @[fetch-buffer.scala:40:7, :159:{29,32}]
wire [1:0] _deq_valids_T = {1'h0, slot_will_hit_tail}; // @[util.scala:384:30]
wire _deq_valids_T_1 = _deq_valids_T[0]; // @[util.scala:384:{30,37}]
wire _deq_valids_T_2 = ~_deq_valids_T_1; // @[util.scala:384:37]
assign deq_valids_0 = _deq_valids_T_2; // @[fetch-buffer.scala:161:{21,53}]
assign io_deq_valid_0 = deq_valids_0; // @[fetch-buffer.scala:40:7, :161:53]
assign io_deq_bits_uops_0_bits_debug_fsrc_0 = (_tail_collisions_T ? deq_vec_0_0_debug_fsrc : 2'h0) | (_tail_collisions_T_4 ? deq_vec_1_0_debug_fsrc : 2'h0) | (_tail_collisions_T_8 ? deq_vec_2_0_debug_fsrc : 2'h0) | (_tail_collisions_T_12 ? deq_vec_3_0_debug_fsrc : 2'h0) | (_tail_collisions_T_16 ? deq_vec_4_0_debug_fsrc : 2'h0) | (_tail_collisions_T_20 ? deq_vec_5_0_debug_fsrc : 2'h0) | (_tail_collisions_T_24 ? deq_vec_6_0_debug_fsrc : 2'h0) | (head[7] ? deq_vec_7_0_debug_fsrc : 2'h0); // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_bp_xcpt_if_0 = _tail_collisions_T & deq_vec_0_0_bp_xcpt_if | _tail_collisions_T_4 & deq_vec_1_0_bp_xcpt_if | _tail_collisions_T_8 & deq_vec_2_0_bp_xcpt_if | _tail_collisions_T_12 & deq_vec_3_0_bp_xcpt_if | _tail_collisions_T_16 & deq_vec_4_0_bp_xcpt_if | _tail_collisions_T_20 & deq_vec_5_0_bp_xcpt_if | _tail_collisions_T_24 & deq_vec_6_0_bp_xcpt_if | head[7] & deq_vec_7_0_bp_xcpt_if; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_bp_debug_if_0 = _tail_collisions_T & deq_vec_0_0_bp_debug_if | _tail_collisions_T_4 & deq_vec_1_0_bp_debug_if | _tail_collisions_T_8 & deq_vec_2_0_bp_debug_if | _tail_collisions_T_12 & deq_vec_3_0_bp_debug_if | _tail_collisions_T_16 & deq_vec_4_0_bp_debug_if | _tail_collisions_T_20 & deq_vec_5_0_bp_debug_if | _tail_collisions_T_24 & deq_vec_6_0_bp_debug_if | head[7] & deq_vec_7_0_bp_debug_if; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_xcpt_ae_if_0 = _tail_collisions_T & deq_vec_0_0_xcpt_ae_if | _tail_collisions_T_4 & deq_vec_1_0_xcpt_ae_if | _tail_collisions_T_8 & deq_vec_2_0_xcpt_ae_if | _tail_collisions_T_12 & deq_vec_3_0_xcpt_ae_if | _tail_collisions_T_16 & deq_vec_4_0_xcpt_ae_if | _tail_collisions_T_20 & deq_vec_5_0_xcpt_ae_if | _tail_collisions_T_24 & deq_vec_6_0_xcpt_ae_if | head[7] & deq_vec_7_0_xcpt_ae_if; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_xcpt_pf_if_0 = _tail_collisions_T & deq_vec_0_0_xcpt_pf_if | _tail_collisions_T_4 & deq_vec_1_0_xcpt_pf_if | _tail_collisions_T_8 & deq_vec_2_0_xcpt_pf_if | _tail_collisions_T_12 & deq_vec_3_0_xcpt_pf_if | _tail_collisions_T_16 & deq_vec_4_0_xcpt_pf_if | _tail_collisions_T_20 & deq_vec_5_0_xcpt_pf_if | _tail_collisions_T_24 & deq_vec_6_0_xcpt_pf_if | head[7] & deq_vec_7_0_xcpt_pf_if; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_taken_0 = _tail_collisions_T & deq_vec_0_0_taken | _tail_collisions_T_4 & deq_vec_1_0_taken | _tail_collisions_T_8 & deq_vec_2_0_taken | _tail_collisions_T_12 & deq_vec_3_0_taken | _tail_collisions_T_16 & deq_vec_4_0_taken | _tail_collisions_T_20 & deq_vec_5_0_taken | _tail_collisions_T_24 & deq_vec_6_0_taken | head[7] & deq_vec_7_0_taken; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_pc_lob_0 = (_tail_collisions_T ? deq_vec_0_0_pc_lob : 6'h0) | (_tail_collisions_T_4 ? deq_vec_1_0_pc_lob : 6'h0) | (_tail_collisions_T_8 ? deq_vec_2_0_pc_lob : 6'h0) | (_tail_collisions_T_12 ? deq_vec_3_0_pc_lob : 6'h0) | (_tail_collisions_T_16 ? deq_vec_4_0_pc_lob : 6'h0) | (_tail_collisions_T_20 ? deq_vec_5_0_pc_lob : 6'h0) | (_tail_collisions_T_24 ? deq_vec_6_0_pc_lob : 6'h0) | (head[7] ? deq_vec_7_0_pc_lob : 6'h0); // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_edge_inst_0 = _tail_collisions_T & deq_vec_0_0_edge_inst | _tail_collisions_T_4 & deq_vec_1_0_edge_inst | _tail_collisions_T_8 & deq_vec_2_0_edge_inst | _tail_collisions_T_12 & deq_vec_3_0_edge_inst | _tail_collisions_T_16 & deq_vec_4_0_edge_inst | _tail_collisions_T_20 & deq_vec_5_0_edge_inst | _tail_collisions_T_24 & deq_vec_6_0_edge_inst | head[7] & deq_vec_7_0_edge_inst; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_ftq_idx_0 = (_tail_collisions_T ? deq_vec_0_0_ftq_idx : 4'h0) | (_tail_collisions_T_4 ? deq_vec_1_0_ftq_idx : 4'h0) | (_tail_collisions_T_8 ? deq_vec_2_0_ftq_idx : 4'h0) | (_tail_collisions_T_12 ? deq_vec_3_0_ftq_idx : 4'h0) | (_tail_collisions_T_16 ? deq_vec_4_0_ftq_idx : 4'h0) | (_tail_collisions_T_20 ? deq_vec_5_0_ftq_idx : 4'h0) | (_tail_collisions_T_24 ? deq_vec_6_0_ftq_idx : 4'h0) | (head[7] ? deq_vec_7_0_ftq_idx : 4'h0); // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_is_sfb_0 = _tail_collisions_T & deq_vec_0_0_is_sfb | _tail_collisions_T_4 & deq_vec_1_0_is_sfb | _tail_collisions_T_8 & deq_vec_2_0_is_sfb | _tail_collisions_T_12 & deq_vec_3_0_is_sfb | _tail_collisions_T_16 & deq_vec_4_0_is_sfb | _tail_collisions_T_20 & deq_vec_5_0_is_sfb | _tail_collisions_T_24 & deq_vec_6_0_is_sfb | head[7] & deq_vec_7_0_is_sfb; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_debug_pc_0 = (_tail_collisions_T ? deq_vec_0_0_debug_pc : 40'h0) | (_tail_collisions_T_4 ? deq_vec_1_0_debug_pc : 40'h0) | (_tail_collisions_T_8 ? deq_vec_2_0_debug_pc : 40'h0) | (_tail_collisions_T_12 ? deq_vec_3_0_debug_pc : 40'h0) | (_tail_collisions_T_16 ? deq_vec_4_0_debug_pc : 40'h0) | (_tail_collisions_T_20 ? deq_vec_5_0_debug_pc : 40'h0) | (_tail_collisions_T_24 ? deq_vec_6_0_debug_pc : 40'h0) | (head[7] ? deq_vec_7_0_debug_pc : 40'h0); // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_is_rvc_0 = _tail_collisions_T & deq_vec_0_0_is_rvc | _tail_collisions_T_4 & deq_vec_1_0_is_rvc | _tail_collisions_T_8 & deq_vec_2_0_is_rvc | _tail_collisions_T_12 & deq_vec_3_0_is_rvc | _tail_collisions_T_16 & deq_vec_4_0_is_rvc | _tail_collisions_T_20 & deq_vec_5_0_is_rvc | _tail_collisions_T_24 & deq_vec_6_0_is_rvc | head[7] & deq_vec_7_0_is_rvc; // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_debug_inst_0 = (_tail_collisions_T ? deq_vec_0_0_debug_inst : 32'h0) | (_tail_collisions_T_4 ? deq_vec_1_0_debug_inst : 32'h0) | (_tail_collisions_T_8 ? deq_vec_2_0_debug_inst : 32'h0) | (_tail_collisions_T_12 ? deq_vec_3_0_debug_inst : 32'h0) | (_tail_collisions_T_16 ? deq_vec_4_0_debug_inst : 32'h0) | (_tail_collisions_T_20 ? deq_vec_5_0_debug_inst : 32'h0) | (_tail_collisions_T_24 ? deq_vec_6_0_debug_inst : 32'h0) | (head[7] ? deq_vec_7_0_debug_inst : 32'h0); // @[Mux.scala:30:73]
assign io_deq_bits_uops_0_bits_inst_0 = (_tail_collisions_T ? deq_vec_0_0_inst : 32'h0) | (_tail_collisions_T_4 ? deq_vec_1_0_inst : 32'h0) | (_tail_collisions_T_8 ? deq_vec_2_0_inst : 32'h0) | (_tail_collisions_T_12 ? deq_vec_3_0_inst : 32'h0) | (_tail_collisions_T_16 ? deq_vec_4_0_inst : 32'h0) | (_tail_collisions_T_20 ? deq_vec_5_0_inst : 32'h0) | (_tail_collisions_T_24 ? deq_vec_6_0_inst : 32'h0) | (head[7] ? deq_vec_7_0_inst : 32'h0); // @[Mux.scala:30:73]
wire [6:0] _head_T = head[6:0]; // @[fetch-buffer.scala:61:21, :132:12]
wire [7:0] _head_T_2 = {_head_T, _head_T_1}; // @[fetch-buffer.scala:132:{8,12,24}]
assign io_deq_bits_uops_0_valid_0 = ~reset & deq_valids_0; // @[fetch-buffer.scala:40:7, :161:53, :168:72, :195:23, :196:41]
wire _T_37 = do_enq & in_mask_0; // @[fetch-buffer.scala:82:16, :87:21, :144:20]
wire _T_18 = _T_37 & enq_idxs_0[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_21 = _T_37 & enq_idxs_0[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_24 = _T_37 & enq_idxs_0[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_27 = _T_37 & enq_idxs_0[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_30 = _T_37 & enq_idxs_0[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_33 = _T_37 & enq_idxs_0[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_36 = _T_37 & enq_idxs_0[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_39 = _T_37 & enq_idxs_0[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_61 = do_enq & in_mask_1; // @[fetch-buffer.scala:82:16, :87:21, :144:20]
wire _T_42 = _T_61 & enq_idxs_1[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_45 = _T_61 & enq_idxs_1[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_48 = _T_61 & enq_idxs_1[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_51 = _T_61 & enq_idxs_1[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_54 = _T_61 & enq_idxs_1[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_57 = _T_61 & enq_idxs_1[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_60 = _T_61 & enq_idxs_1[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_63 = _T_61 & enq_idxs_1[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_85 = do_enq & in_mask_2; // @[fetch-buffer.scala:82:16, :87:21, :144:20]
wire _T_66 = _T_85 & enq_idxs_2[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_69 = _T_85 & enq_idxs_2[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_72 = _T_85 & enq_idxs_2[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_75 = _T_85 & enq_idxs_2[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_78 = _T_85 & enq_idxs_2[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_81 = _T_85 & enq_idxs_2[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_84 = _T_85 & enq_idxs_2[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_87 = _T_85 & enq_idxs_2[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_109 = do_enq & in_mask_3; // @[fetch-buffer.scala:82:16, :87:21, :144:20]
wire _T_90 = _T_109 & enq_idxs_3[0]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_93 = _T_109 & enq_idxs_3[1]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_96 = _T_109 & enq_idxs_3[2]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_99 = _T_109 & enq_idxs_3[3]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_102 = _T_109 & enq_idxs_3[4]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_105 = _T_109 & enq_idxs_3[5]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_108 = _T_109 & enq_idxs_3[6]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
wire _T_111 = _T_109 & enq_idxs_3[7]; // @[fetch-buffer.scala:128:22, :144:{20,34,48}]
always @(posedge clock) begin // @[fetch-buffer.scala:40:7]
if (_T_90) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_0_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_66) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_0_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_42) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_0_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_18) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_0_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_0_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_0_edge_inst <= ~(_T_90 | _T_66 | _T_42) & (_T_18 ? in_uops_0_edge_inst : fb_uop_ram_0_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_93) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_1_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_69) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_1_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_45) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_1_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_21) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_1_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_1_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_1_edge_inst <= ~(_T_93 | _T_69 | _T_45) & (_T_21 ? in_uops_0_edge_inst : fb_uop_ram_1_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_96) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_2_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_72) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_2_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_48) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_2_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_24) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_2_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_2_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_2_edge_inst <= ~(_T_96 | _T_72 | _T_48) & (_T_24 ? in_uops_0_edge_inst : fb_uop_ram_2_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_99) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_3_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_75) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_3_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_51) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_3_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_27) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_3_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_3_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_3_edge_inst <= ~(_T_99 | _T_75 | _T_51) & (_T_27 ? in_uops_0_edge_inst : fb_uop_ram_3_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_102) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_4_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_78) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_4_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_54) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_4_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_30) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_4_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_4_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_4_edge_inst <= ~(_T_102 | _T_78 | _T_54) & (_T_30 ? in_uops_0_edge_inst : fb_uop_ram_4_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_105) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_5_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_81) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_5_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_57) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_5_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_33) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_5_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_5_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_5_edge_inst <= ~(_T_105 | _T_81 | _T_57) & (_T_33 ? in_uops_0_edge_inst : fb_uop_ram_5_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_108) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_6_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_84) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_6_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_60) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_6_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_36) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_6_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_6_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_6_edge_inst <= ~(_T_108 | _T_84 | _T_60) & (_T_36 ? in_uops_0_edge_inst : fb_uop_ram_6_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (_T_111) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_7_inst <= in_uops_3_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_inst <= in_uops_3_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_rvc <= in_uops_3_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_pc <= in_uops_3_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_sfb <= in_uops_3_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_ftq_idx <= in_uops_3_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_pc_lob <= in_uops_3_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_taken <= in_uops_3_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_pf_if <= in_uops_3_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_ae_if <= in_uops_3_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_debug_if <= in_uops_3_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_xcpt_if <= in_uops_3_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_fsrc <= in_uops_3_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_87) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_7_inst <= in_uops_2_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_inst <= in_uops_2_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_rvc <= in_uops_2_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_pc <= in_uops_2_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_sfb <= in_uops_2_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_ftq_idx <= in_uops_2_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_pc_lob <= in_uops_2_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_taken <= in_uops_2_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_pf_if <= in_uops_2_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_ae_if <= in_uops_2_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_debug_if <= in_uops_2_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_xcpt_if <= in_uops_2_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_fsrc <= in_uops_2_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_63) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_7_inst <= in_uops_1_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_inst <= in_uops_1_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_rvc <= in_uops_1_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_pc <= in_uops_1_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_sfb <= in_uops_1_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_ftq_idx <= in_uops_1_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_pc_lob <= in_uops_1_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_taken <= in_uops_1_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_pf_if <= in_uops_1_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_ae_if <= in_uops_1_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_debug_if <= in_uops_1_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_xcpt_if <= in_uops_1_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_fsrc <= in_uops_1_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
else if (_T_39) begin // @[fetch-buffer.scala:144:34]
fb_uop_ram_7_inst <= in_uops_0_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_inst <= in_uops_0_debug_inst; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_rvc <= in_uops_0_is_rvc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_pc <= in_uops_0_debug_pc; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_is_sfb <= in_uops_0_is_sfb; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_ftq_idx <= in_uops_0_ftq_idx; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_pc_lob <= in_uops_0_pc_lob; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_taken <= in_uops_0_taken; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_pf_if <= in_uops_0_xcpt_pf_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_xcpt_ae_if <= in_uops_0_xcpt_ae_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_debug_if <= in_uops_0_bp_debug_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_bp_xcpt_if <= in_uops_0_bp_xcpt_if; // @[fetch-buffer.scala:57:16, :88:21]
fb_uop_ram_7_debug_fsrc <= in_uops_0_debug_fsrc; // @[fetch-buffer.scala:57:16, :88:21]
end
fb_uop_ram_7_edge_inst <= ~(_T_111 | _T_87 | _T_63) & (_T_39 ? in_uops_0_edge_inst : fb_uop_ram_7_edge_inst); // @[fetch-buffer.scala:57:16, :88:21, :144:{34,53}, :145:16]
if (reset) begin // @[fetch-buffer.scala:40:7]
head <= 8'h1; // @[fetch-buffer.scala:61:21]
tail <= 8'h1; // @[fetch-buffer.scala:62:21]
maybe_full <= 1'h0; // @[fetch-buffer.scala:64:27]
end
else begin // @[fetch-buffer.scala:40:7]
if (io_clear_0) begin // @[fetch-buffer.scala:40:7]
head <= 8'h1; // @[fetch-buffer.scala:61:21]
tail <= 8'h1; // @[fetch-buffer.scala:62:21]
end
else begin // @[fetch-buffer.scala:40:7]
if (do_deq) // @[fetch-buffer.scala:159:29]
head <= _head_T_2; // @[fetch-buffer.scala:61:21, :132:8]
if (do_enq) begin // @[fetch-buffer.scala:82:16]
if (in_mask_3) // @[fetch-buffer.scala:87:21]
tail <= {enq_idxs_3[6:0], enq_idxs_3[7]}; // @[fetch-buffer.scala:62:21, :128:22, :132:{8,12,24}]
else if (in_mask_2) // @[fetch-buffer.scala:87:21]
tail <= _T_10; // @[fetch-buffer.scala:62:21, :132:8]
else if (in_mask_1) // @[fetch-buffer.scala:87:21]
tail <= _T_6; // @[fetch-buffer.scala:62:21, :132:8]
else if (in_mask_0) // @[fetch-buffer.scala:87:21]
tail <= _T_2; // @[fetch-buffer.scala:62:21, :132:8]
end
end
maybe_full <= ~(io_clear_0 | do_deq) & (do_enq & (in_mask_0 | in_mask_1 | in_mask_2 | in_mask_3) | maybe_full); // @[fetch-buffer.scala:40:7, :64:27, :82:16, :87:21, :159:29, :176:17, :178:{27,33}, :179:18, :183:17, :185:16, :188:19, :191:16]
end
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[fetch-buffer.scala:40:7]
assign io_deq_valid = io_deq_valid_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_valid = io_deq_bits_uops_0_valid_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_inst = io_deq_bits_uops_0_bits_inst_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_debug_inst = io_deq_bits_uops_0_bits_debug_inst_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_is_rvc = io_deq_bits_uops_0_bits_is_rvc_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_debug_pc = io_deq_bits_uops_0_bits_debug_pc_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_is_sfb = io_deq_bits_uops_0_bits_is_sfb_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_ftq_idx = io_deq_bits_uops_0_bits_ftq_idx_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_edge_inst = io_deq_bits_uops_0_bits_edge_inst_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_pc_lob = io_deq_bits_uops_0_bits_pc_lob_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_taken = io_deq_bits_uops_0_bits_taken_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_xcpt_pf_if = io_deq_bits_uops_0_bits_xcpt_pf_if_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_xcpt_ae_if = io_deq_bits_uops_0_bits_xcpt_ae_if_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_bp_debug_if = io_deq_bits_uops_0_bits_bp_debug_if_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_bp_xcpt_if = io_deq_bits_uops_0_bits_bp_xcpt_if_0; // @[fetch-buffer.scala:40:7]
assign io_deq_bits_uops_0_bits_debug_fsrc = io_deq_bits_uops_0_bits_debug_fsrc_0; // @[fetch-buffer.scala:40:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_21( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_37 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Serdes.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(t))
val out = Decoupled(new Flit(flitWidth))
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))
data(0) := DontCare // unused, DCE this
}
}
io.busy := io.out.valid
}
class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {
override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(t)
val busy = Output(Bool())
})
val dataBits = t.getWidth.max(flitWidth)
val dataBeats = (dataBits - 1) / flitWidth + 1
require(dataBeats >= 1)
val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits := (if (dataBeats == 1) {
io.in.bits.flit.asTypeOf(t)
} else {
Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)
})
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit
}
}
}
io.busy := beat =/= 0.U
}
class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Phit(phitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready && beat === 0.U
io.out.valid := io.in.valid || beat =/= 0.U
io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))
when (io.out.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) {
data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail
}
}
}
object FlitToPhit {
def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {
val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))
flit2phit.io.in <> flit
flit2phit.io.out
}
}
class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {
override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Decoupled(new Flit(flitWidth))
})
require(flitWidth >= phitWidth)
val dataBeats = (flitWidth - 1) / phitWidth + 1
val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))
val beat = RegInit(0.U(log2Ceil(dataBeats).W))
io.in.ready := io.out.ready || beat =/= (dataBeats-1).U
io.out.valid := io.in.valid && beat === (dataBeats-1).U
io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))
when (io.in.fire) {
beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)
if (dataBeats > 1) {
when (beat =/= (dataBeats-1).U) {
data(beat) := io.in.bits.phit
}
}
}
}
object PhitToFlit {
def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in <> phit
phit2flit.io.out
}
def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {
val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))
phit2flit.io.in.valid := phit.valid
phit2flit.io.in.bits := phit.bits
when (phit.valid) { assert(phit2flit.io.in.ready) }
val out = Wire(Valid(new Flit(flitWidth)))
out.valid := phit2flit.io.out.valid
out.bits := phit2flit.io.out.bits
phit2flit.io.out.ready := true.B
out
}
}
class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))
val out = Decoupled(new Phit(phitWidth))
})
if (channels == 1) {
io.out <> io.in(0)
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val chosen_reg = Reg(UInt(headerWidth.W))
val chosen_prio = PriorityEncoder(io.in.map(_.valid))
val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.out.valid := VecInit(io.in.map(_.valid))(chosen)
io.out.bits.phit := Mux(beat < headerBeats.U,
chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),
VecInit(io.in.map(_.bits.phit))(chosen))
for (i <- 0 until channels) {
io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U
}
when (io.out.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat === 0.U) { chosen_reg := chosen_prio }
}
}
}
class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {
override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Phit(phitWidth)))
val out = Vec(channels, Decoupled(new Phit(phitWidth)))
})
if (channels == 1) {
io.out(0) <> io.in
} else {
val headerWidth = log2Ceil(channels)
val headerBeats = (headerWidth - 1) / phitWidth + 1
val flitBeats = (flitWidth - 1) / phitWidth + 1
val beats = headerBeats + flitBeats
val beat = RegInit(0.U(log2Ceil(beats).W))
val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))
val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)
val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)
io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)
for (c <- 0 until channels) {
io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U
io.out(c).bits.phit := io.in.bits.phit
}
when (io.in.fire) {
beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)
when (beat < headerBeats.U) {
channel_vec(header_idx) := io.in.bits.phit
}
}
}
}
class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Flipped(Decoupled(new Flit(flitWidth)))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = io.out.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)
}
io.out.valid := io.in.valid && credits < bufferSz.U
io.out.bits.flit := io.in.bits.flit
io.in.ready := io.out.ready && credits < bufferSz.U
io.credit.ready := true.B
}
class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {
override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}"
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Flit(flitWidth)))
val out = Decoupled(new Flit(flitWidth))
val credit = Decoupled(new Flit(flitWidth))
})
val creditWidth = log2Ceil(bufferSz)
require(creditWidth <= flitWidth)
val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))
val credits = RegInit(0.U((creditWidth+1).W))
val credit_incr = buffer.io.deq.fire
val credit_decr = io.credit.fire
when (credit_incr || credit_decr) {
credits := credit_incr + Mux(credit_decr, 0.U, credits)
}
buffer.io.enq.valid := io.in.valid
buffer.io.enq.bits := io.in.bits
io.in.ready := true.B
when (io.in.valid) { assert(buffer.io.enq.ready) }
io.out <> buffer.io.deq
io.credit.valid := credits =/= 0.U
io.credit.bits.flit := credits - 1.U
}
| module FlitToPhit_f32_p32_5( // @[Serdes.scala:71:7]
input clock, // @[Serdes.scala:71:7]
input reset, // @[Serdes.scala:71:7]
output io_in_ready, // @[Serdes.scala:73:14]
input io_in_valid, // @[Serdes.scala:73:14]
input [31:0] io_in_bits_flit, // @[Serdes.scala:73:14]
input io_out_ready, // @[Serdes.scala:73:14]
output io_out_valid, // @[Serdes.scala:73:14]
output [31:0] io_out_bits_phit // @[Serdes.scala:73:14]
);
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:71:7]
wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:71:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:71:7]
wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:88:53]
wire _io_in_ready_T = 1'h1; // @[Serdes.scala:83:39]
wire _beat_T = 1'h1; // @[Serdes.scala:88:22]
wire _beat_T_2 = 1'h1; // @[Serdes.scala:88:53]
wire _io_in_ready_T_1; // @[Serdes.scala:83:31]
wire _io_out_valid_T = 1'h0; // @[Serdes.scala:84:39]
wire _beat_T_3 = 1'h0; // @[Serdes.scala:88:16]
wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:71:7, :84:31]
wire [31:0] io_out_bits_phit_0 = io_in_bits_flit_0; // @[Serdes.scala:71:7]
assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:71:7, :83:31]
wire io_in_ready_0; // @[Serdes.scala:71:7]
wire io_out_valid_0; // @[Serdes.scala:71:7]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:71:7, :83:31]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:71:7, :84:31]
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:71:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:71:7]
assign io_out_bits_phit = io_out_bits_phit_0; // @[Serdes.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File fdiv.scala:
//******************************************************************************
// Copyright (c) 2016 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// FDiv/FSqrt Unit
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.FPConstants._
import freechips.rocketchip.tile
import boom.v3.common._
import boom.v3.util._
import freechips.rocketchip.tile.HasFPUParameters
import freechips.rocketchip.util.uintToBitPat
/**
* Decoder for FPU divide and square root signals
*/
class UOPCodeFDivDecoder(implicit p: Parameters) extends BoomModule
with HasFPUParameters
{
val io = IO(new Bundle {
val uopc = Input(Bits(UOPC_SZ.W))
val sigs = Output(new tile.FPUCtrlSigs())
})
val N = BitPat("b0")
val Y = BitPat("b1")
val X = BitPat("b?")
val decoder = freechips.rocketchip.rocket.DecodeLogic(io.uopc,
// Note: not all of these signals are used or necessary, but we're
// constrained by the need to fit the rocket.FPU units' ctrl signals.
// swap12 fma
// | swap32 | div
// | | typeTagIn | | sqrt
// ldst | | | typeTagOut | | wflags
// | wen | | | | from_int | | |
// | | ren1 | | | | | to_int | | |
// | | | ren2 | | | | | | fast | | |
// | | | | ren3 | | | | | | | | | |
// | | | | | | | | | | | | | | | |
/* Default */ List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X),
Array(
BitPat(uopFDIV_S) -> List(X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y),
BitPat(uopFDIV_D) -> List(X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y),
BitPat(uopFSQRT_S) -> List(X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y),
BitPat(uopFSQRT_D) -> List(X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y)
): Array[(BitPat, List[BitPat])])
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.wflags)
s.vec := false.B
sigs zip decoder map {case(s,d) => s := d}
}
/**
* fdiv/fsqrt is douple-precision. Must upconvert inputs and downconvert outputs
* as necessary. Must wait till killed uop finishes before we're ready again.
* fdiv/fsqrt unit uses an unstable FIFO interface, and thus we must spend a
* cycle buffering up an uop to provide slack between the issue queue and the
* fdiv/fsqrt unit. FDivUnit inherents directly from FunctionalUnit, because
* UnpipelinedFunctionalUnit can only handle 1 inflight uop, whereas FDivUnit
* contains up to 2 inflight uops due to the need to buffer the input as the
* fdiv unit uses an unstable FIFO interface.
* TODO extend UnpipelinedFunctionalUnit to handle a >1 uops inflight.
*
* @param isPipelined is the functional unit pipelined
* @param numStages number of stages for the functional unit
* @param numBypassStages number of bypass stages
* @param dataWidth width of the data out of the functional unit
*/
class FDivSqrtUnit(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
//--------------------------------------
// buffer inputs and upconvert as needed
// provide a one-entry queue to store incoming uops while waiting for the fdiv/fsqrt unit to become available.
val r_buffer_val = RegInit(false.B)
val r_buffer_req = Reg(new FuncUnitReq(dataWidth=65))
val r_buffer_fin = Reg(new tile.FPInput)
val fdiv_decoder = Module(new UOPCodeFDivDecoder)
fdiv_decoder.io.uopc := io.req.bits.uop.uopc
// handle branch kill on queued entry
r_buffer_val := !IsKilledByBranch(io.brupdate, r_buffer_req.uop) && !io.req.bits.kill && r_buffer_val
r_buffer_req.uop.br_mask := GetNewBrMask(io.brupdate, r_buffer_req.uop)
// handle incoming uop, including upconversion as needed, and push back if our input queue is already occupied
io.req.ready := !r_buffer_val
def upconvert(x: UInt) = {
val s2d = Module(new hardfloat.RecFNToRecFN(inExpWidth = 8, inSigWidth = 24, outExpWidth = 11, outSigWidth = 53))
s2d.io.in := x
s2d.io.roundingMode := 0.U
s2d.io.detectTininess := DontCare
s2d.io.out
}
val in1_upconvert = upconvert(unbox(io.req.bits.rs1_data, false.B, Some(tile.FType.S)))
val in2_upconvert = upconvert(unbox(io.req.bits.rs2_data, false.B, Some(tile.FType.S)))
when (io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill) {
r_buffer_val := true.B
r_buffer_req := io.req.bits
r_buffer_req.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
r_buffer_fin.viewAsSupertype(new tile.FPUCtrlSigs) := fdiv_decoder.io.sigs
r_buffer_fin.rm := Mux(ImmGenRm(io.req.bits.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io.req.bits.uop.imm_packed))
r_buffer_fin.typ := 0.U // unused for fdivsqrt
val tag = fdiv_decoder.io.sigs.typeTagIn
r_buffer_fin.in1 := unbox(io.req.bits.rs1_data, tag, Some(tile.FType.D))
r_buffer_fin.in2 := unbox(io.req.bits.rs2_data, tag, Some(tile.FType.D))
when (tag === S) {
r_buffer_fin.in1 := in1_upconvert
r_buffer_fin.in2 := in2_upconvert
}
}
assert (!(r_buffer_val && io.req.valid), "[fdiv] a request is incoming while the buffer is already full.")
//-----------
// fdiv/fsqrt
val divsqrt = Module(new hardfloat.DivSqrtRecF64)
val r_divsqrt_val = RegInit(false.B) // inflight uop?
val r_divsqrt_killed = Reg(Bool()) // has inflight uop been killed?
val r_divsqrt_fin = Reg(new tile.FPInput)
val r_divsqrt_uop = Reg(new MicroOp)
// Need to buffer output until RF writeport is available.
val output_buffer_available = Wire(Bool())
val may_fire_input =
r_buffer_val &&
(r_buffer_fin.div || r_buffer_fin.sqrt) &&
!r_divsqrt_val &&
output_buffer_available
val divsqrt_ready = Mux(divsqrt.io.sqrtOp, divsqrt.io.inReady_sqrt, divsqrt.io.inReady_div)
divsqrt.io.inValid := may_fire_input // must be setup early
divsqrt.io.sqrtOp := r_buffer_fin.sqrt
divsqrt.io.a := r_buffer_fin.in1
divsqrt.io.b := Mux(divsqrt.io.sqrtOp, r_buffer_fin.in1, r_buffer_fin.in2)
divsqrt.io.roundingMode := r_buffer_fin.rm
divsqrt.io.detectTininess := DontCare
r_divsqrt_killed := r_divsqrt_killed || IsKilledByBranch(io.brupdate, r_divsqrt_uop) || io.req.bits.kill
r_divsqrt_uop.br_mask := GetNewBrMask(io.brupdate, r_divsqrt_uop)
when (may_fire_input && divsqrt_ready) {
// Remove entry from the input buffer.
// We don't have time to kill divsqrt request so must track if killed on entry.
r_buffer_val := false.B
r_divsqrt_val := true.B
r_divsqrt_fin := r_buffer_fin
r_divsqrt_uop := r_buffer_req.uop
r_divsqrt_killed := IsKilledByBranch(io.brupdate, r_buffer_req.uop) || io.req.bits.kill
r_divsqrt_uop.br_mask := GetNewBrMask(io.brupdate, r_buffer_req.uop)
}
//-----------------------------------------
// buffer output and down-convert as needed
val r_out_val = RegInit(false.B)
val r_out_uop = Reg(new MicroOp)
val r_out_flags_double = Reg(Bits())
val r_out_wdata_double = Reg(Bits())
output_buffer_available := !r_out_val
r_out_uop.br_mask := GetNewBrMask(io.brupdate, r_out_uop)
when (io.resp.ready || IsKilledByBranch(io.brupdate, r_out_uop) || io.req.bits.kill) {
r_out_val := false.B
}
when (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt) {
r_divsqrt_val := false.B
r_out_val := !r_divsqrt_killed && !IsKilledByBranch(io.brupdate, r_divsqrt_uop) && !io.req.bits.kill
r_out_uop := r_divsqrt_uop
r_out_uop.br_mask := GetNewBrMask(io.brupdate, r_divsqrt_uop)
r_out_wdata_double := sanitizeNaN(divsqrt.io.out, tile.FType.D)
r_out_flags_double := divsqrt.io.exceptionFlags
assert (r_divsqrt_val, "[fdiv] a response is being generated for no request.")
}
assert (!(r_out_val && (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt)),
"[fdiv] Buffered output being overwritten by another output from the fdiv/fsqrt unit.")
val downvert_d2s = Module(new hardfloat.RecFNToRecFN(
inExpWidth = 11, inSigWidth = 53, outExpWidth = 8, outSigWidth = 24))
downvert_d2s.io.in := r_out_wdata_double
downvert_d2s.io.roundingMode := r_divsqrt_fin.rm
downvert_d2s.io.detectTininess := DontCare
val out_flags = r_out_flags_double | Mux(r_divsqrt_fin.typeTagIn === S, downvert_d2s.io.exceptionFlags, 0.U)
io.resp.valid := r_out_val && !IsKilledByBranch(io.brupdate, r_out_uop)
io.resp.bits.uop := r_out_uop
io.resp.bits.data :=
Mux(r_divsqrt_fin.typeTagIn === S,
box(downvert_d2s.io.out, false.B),
box(r_out_wdata_double, true.B))
io.resp.bits.fflags.valid := io.resp.valid
io.resp.bits.fflags.bits.uop := r_out_uop
io.resp.bits.fflags.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_out_uop)
io.resp.bits.fflags.bits.flags := out_flags
}
File functional-unit.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// If regfile bypassing is disabled, then the functional unit must do its own
// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)
//
// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.tile
import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}
import boom.v3.common._
import boom.v3.ifu._
import boom.v3.util._
/**t
* Functional unit constants
*/
object FUConstants
{
// bit mask, since a given execution pipeline may support multiple functional units
val FUC_SZ = 10
val FU_X = BitPat.dontCare(FUC_SZ)
val FU_ALU = 1.U(FUC_SZ.W)
val FU_JMP = 2.U(FUC_SZ.W)
val FU_MEM = 4.U(FUC_SZ.W)
val FU_MUL = 8.U(FUC_SZ.W)
val FU_DIV = 16.U(FUC_SZ.W)
val FU_CSR = 32.U(FUC_SZ.W)
val FU_FPU = 64.U(FUC_SZ.W)
val FU_FDV = 128.U(FUC_SZ.W)
val FU_I2F = 256.U(FUC_SZ.W)
val FU_F2I = 512.U(FUC_SZ.W)
// FP stores generate data through FP F2I, and generate address through MemAddrCalc
val FU_F2IMEM = 516.U(FUC_SZ.W)
}
import FUConstants._
/**
* Class to tell the FUDecoders what units it needs to support
*
* @param alu support alu unit?
* @param bru support br unit?
* @param mem support mem unit?
* @param muld support multiple div unit?
* @param fpu support FP unit?
* @param csr support csr writing unit?
* @param fdiv support FP div unit?
* @param ifpu support int to FP unit?
*/
class SupportedFuncUnits(
val alu: Boolean = false,
val jmp: Boolean = false,
val mem: Boolean = false,
val muld: Boolean = false,
val fpu: Boolean = false,
val csr: Boolean = false,
val fdiv: Boolean = false,
val ifpu: Boolean = false)
{
}
/**
* Bundle for signals sent to the functional unit
*
* @param dataWidth width of the data sent to the functional unit
*/
class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val numOperands = 3
val rs1_data = UInt(dataWidth.W)
val rs2_data = UInt(dataWidth.W)
val rs3_data = UInt(dataWidth.W) // only used for FMA units
val pred_data = Bool()
val kill = Bool() // kill everything
}
/**
* Bundle for the signals sent out of the function unit
*
* @param dataWidth data sent from the functional unit
*/
class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val predicated = Bool() // Was this response from a predicated-off instruction
val data = UInt(dataWidth.W)
val fflags = new ValidIO(new FFlagsResp)
val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU
val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
}
/**
* Branch resolution information given from the branch unit
*/
class BrResolutionInfo(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp
val valid = Bool()
val mispredict = Bool()
val taken = Bool() // which direction did the branch go?
val cfi_type = UInt(CFI_SZ.W)
// Info for recalculating the pc for this branch
val pc_sel = UInt(2.W)
val jalr_target = UInt(vaddrBitsExtended.W)
val target_offset = SInt()
}
class BrUpdateInfo(implicit p: Parameters) extends BoomBundle
{
// On the first cycle we get masks to kill registers
val b1 = new BrUpdateMasks
// On the second cycle we get indices to reset pointers
val b2 = new BrResolutionInfo
}
class BrUpdateMasks(implicit p: Parameters) extends BoomBundle
{
val resolve_mask = UInt(maxBrCount.W)
val mispredict_mask = UInt(maxBrCount.W)
}
/**
* Abstract top level functional unit class that wraps a lower level hand made functional unit
*
* @param isPipelined is the functional unit pipelined?
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class FunctionalUnit(
val isPipelined: Boolean,
val numStages: Int,
val numBypassStages: Int,
val dataWidth: Int,
val isJmpUnit: Boolean = false,
val isAluUnit: Boolean = false,
val isMemAddrCalcUnit: Boolean = false,
val needsFcsr: Boolean = false)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))
val brupdate = Input(new BrUpdateInfo())
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
// only used by the fpu unit
val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null
// only used by branch unit
val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null
// only used by memaddr calc unit
val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
})
io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }
io.resp.valid := false.B
io.resp.bits := DontCare
if (isJmpUnit) {
io.get_ftq_pc.ftq_idx := DontCare
}
}
/**
* Abstract top level pipelined functional unit
*
* Note: this helps track which uops get killed while in intermediate stages,
* but it is the job of the consumer to check for kills on the same cycle as consumption!!!
*
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param earliestBypassStage first stage that you can start bypassing from
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class PipelinedFunctionalUnit(
numStages: Int,
numBypassStages: Int,
earliestBypassStage: Int,
dataWidth: Int,
isJmpUnit: Boolean = false,
isAluUnit: Boolean = false,
isMemAddrCalcUnit: Boolean = false,
needsFcsr: Boolean = false
)(implicit p: Parameters) extends FunctionalUnit(
isPipelined = true,
numStages = numStages,
numBypassStages = numBypassStages,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit,
isAluUnit = isAluUnit,
isMemAddrCalcUnit = isMemAddrCalcUnit,
needsFcsr = needsFcsr)
{
// Pipelined functional unit is always ready.
io.req.ready := true.B
if (numStages > 0) {
val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_uops = Reg(Vec(numStages, new MicroOp()))
// handle incoming request
r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill
r_uops(0) := io.req.bits.uop
r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
// handle middle of the pipeline
for (i <- 1 until numStages) {
r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill
r_uops(i) := r_uops(i-1)
r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))
if (numBypassStages > 0) {
io.bypass(i-1).bits.uop := r_uops(i-1)
}
}
// handle outgoing (branch could still kill it)
// consumer must also check for pipeline flushes (kills)
io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))
io.resp.bits.predicated := false.B
io.resp.bits.uop := r_uops(numStages-1)
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))
// bypassing (TODO allow bypass vector to have a different size from numStages)
if (numBypassStages > 0 && earliestBypassStage == 0) {
io.bypass(0).bits.uop := io.req.bits.uop
for (i <- 1 until numBypassStages) {
io.bypass(i).bits.uop := r_uops(i-1)
}
}
} else {
require (numStages == 0)
// pass req straight through to response
// valid doesn't check kill signals, let consumer deal with it.
// The LSU already handles it and this hurts critical path.
io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
io.resp.bits.predicated := false.B
io.resp.bits.uop := io.req.bits.uop
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
}
}
/**
* Functional unit that wraps RocketChips ALU
*
* @param isBranchUnit is this a branch unit?
* @param numStages how many pipeline stages does the functional unit have
* @param dataWidth width of the data being operated on in the functional unit
*/
class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = numStages,
isAluUnit = true,
earliestBypassStage = 0,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit)
with boom.v3.ifu.HasBoomFrontendParameters
{
val uop = io.req.bits.uop
// immediate generation
val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)
// operand 1 select
var op1_data: UInt = null
if (isJmpUnit) {
// Get the uop PC for jumps
val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)
val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),
0.U))
} else {
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
0.U)
}
// operand 2 select
val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),
Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),
Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,
Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),
0.U))))
val alu = Module(new freechips.rocketchip.rocket.ALU())
alu.io.in1 := op1_data.asUInt
alu.io.in2 := op2_data.asUInt
alu.io.fn := uop.ctrl.op_fcn
alu.io.dw := uop.ctrl.fcn_dw
// Did I just get killed by the previous cycle's branch,
// or by a flush pipeline?
val killed = WireInit(false.B)
when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {
killed := true.B
}
val rs1 = io.req.bits.rs1_data
val rs2 = io.req.bits.rs2_data
val br_eq = (rs1 === rs2)
val br_ltu = (rs1.asUInt < rs2.asUInt)
val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |
rs1(xLen-1) & ~rs2(xLen-1)).asBool
val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(
Seq( BR_N -> PC_PLUS4,
BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),
BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),
BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),
BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),
BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),
BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),
BR_J -> PC_BRJMP,
BR_JR -> PC_JALR
))
val is_taken = io.req.valid &&
!killed &&
(uop.is_br || uop.is_jalr || uop.is_jal) &&
(pc_sel =/= PC_PLUS4)
// "mispredict" means that a branch has been resolved and it must be killed
val mispredict = WireInit(false.B)
val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb
val is_jal = io.req.valid && !killed && uop.is_jal
val is_jalr = io.req.valid && !killed && uop.is_jalr
when (is_br || is_jalr) {
if (!isJmpUnit) {
assert (pc_sel =/= PC_JALR)
}
when (pc_sel === PC_PLUS4) {
mispredict := uop.taken
}
when (pc_sel === PC_BRJMP) {
mispredict := !uop.taken
}
}
val brinfo = Wire(new BrResolutionInfo)
// note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
brinfo.valid := is_br || is_jalr
brinfo.mispredict := mispredict
brinfo.uop := uop
brinfo.cfi_type := Mux(is_jalr, CFI_JALR,
Mux(is_br , CFI_BR, CFI_X))
brinfo.taken := is_taken
brinfo.pc_sel := pc_sel
brinfo.jalr_target := DontCare
// Branch/Jump Target Calculation
// For jumps we read the FTQ, and can calculate the target
// For branches we emit the offset for the core to redirect if necessary
val target_offset = imm_xprlen(20,0).asSInt
brinfo.jalr_target := DontCare
if (isJmpUnit) {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
val jalr_target_base = io.req.bits.rs1_data.asSInt
val jalr_target_xlen = Wire(UInt(xLen.W))
jalr_target_xlen := (jalr_target_base + target_offset).asUInt
val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt
brinfo.jalr_target := jalr_target
val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)
when (pc_sel === PC_JALR) {
mispredict := !io.get_ftq_pc.next_val ||
(io.get_ftq_pc.next_pc =/= jalr_target) ||
!io.get_ftq_pc.entry.cfi_idx.valid ||
(io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)
}
}
brinfo.target_offset := target_offset
io.brinfo := brinfo
// Response
// TODO add clock gate on resp bits from functional units
// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)
// val reg_data = Reg(outType = Bits(width = xLen))
// reg_data := alu.io.out
// io.resp.bits.data := reg_data
val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_data = Reg(Vec(numStages, UInt(xLen.W)))
val r_pred = Reg(Vec(numStages, Bool()))
val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,
Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),
Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))
r_val (0) := io.req.valid
r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data
for (i <- 1 until numStages) {
r_val(i) := r_val(i-1)
r_data(i) := r_data(i-1)
r_pred(i) := r_pred(i-1)
}
io.resp.bits.data := r_data(numStages-1)
io.resp.bits.predicated := r_pred(numStages-1)
// Bypass
// for the ALU, we can bypass same cycle as compute
require (numStages >= 1)
require (numBypassStages >= 1)
io.bypass(0).valid := io.req.valid
io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
for (i <- 1 until numStages) {
io.bypass(i).valid := r_val(i-1)
io.bypass(i).bits.data := r_data(i-1)
}
// Exceptions
io.resp.bits.fflags.valid := false.B
}
/**
* Functional unit that passes in base+imm to calculate addresses, and passes store data
* to the LSU.
* For floating point, 65bit FP store-data needs to be decoded into 64bit FP form
*/
class MemAddrCalcUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = 0,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65, // TODO enable this only if FP is enabled?
isMemAddrCalcUnit = true)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
// perform address calculation
val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt
val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,
sum(63,vaddrBits) =/= 0.U)
val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt
val store_data = io.req.bits.rs2_data
io.resp.bits.addr := effective_address
io.resp.bits.data := store_data
if (dataWidth > 63) {
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&
io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.")
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),
"FP store-data should now be going through a different unit.")
}
assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=
uopLD && io.req.bits.uop.uopc =/= uopSTA),
"[maddrcalc] assert we never get store data in here.")
// Handle misaligned exceptions
val size = io.req.bits.uop.mem_size
val misaligned =
(size === 1.U && (effective_address(0) =/= 0.U)) ||
(size === 2.U && (effective_address(1,0) =/= 0.U)) ||
(size === 3.U && (effective_address(2,0) =/= 0.U))
val bkptu = Module(new BreakpointUnit(nBreakpoints))
bkptu.io.status := io.status
bkptu.io.bp := io.bp
bkptu.io.pc := DontCare
bkptu.io.ea := effective_address
bkptu.io.mcontext := io.mcontext
bkptu.io.scontext := io.scontext
val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned
val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))
val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_val, xcpt_cause) = checkExceptions(List(
(ma_ld, (Causes.misaligned_load).U),
(ma_st, (Causes.misaligned_store).U),
(dbg_bp, (CSR.debugTriggerCause).U),
(bp, (Causes.breakpoint).U)))
io.resp.bits.mxcpt.valid := xcpt_val
io.resp.bits.mxcpt.bits := xcpt_cause
assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.")
io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE
io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)
io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)
io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data
io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data
}
/**
* Functional unit to wrap lower level FPU
*
* Currently, bypassing is unsupported!
* All FP instructions are padded out to the max latency unit for easy
* write-port scheduling.
*/
class FPUUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
{
val fpu = Module(new FPU())
fpu.io.req.valid := io.req.valid
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.fcsr_rm := io.fcsr_rm
io.resp.bits.data := fpu.io.resp.bits.data
io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now
}
/**
* Int to FP conversion functional unit
*
* @param latency the amount of stages to delay by
*/
class IntToFPUnit(latency: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = latency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder
val io_req = io.req.bits
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, None)
req.in2 := unbox(io_req.rs2_data, tag, None)
req.in3 := DontCare
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := DontCare // FIXME: this may not be the right thing to do here
req.fmaCmd := DontCare
assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),
"[func] IntToFP integer input has 65th high-order bit set!")
assert (!(io.req.valid && !fp_ctrl.fromint),
"[func] Only support fromInt micro-ops.")
val ifpu = Module(new tile.IntToFP(intToFpLatency))
ifpu.io.in.valid := io.req.valid
ifpu.io.in.bits := req
ifpu.io.in.bits.in1 := io_req.rs1_data
val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits
//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)
io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)
io.resp.bits.fflags.valid := ifpu.io.out.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc
}
/**
* Iterative/unpipelined functional unit, can only hold a single MicroOp at a time
* assumes at least one register between request and response
*
* TODO allow up to N micro-ops simultaneously.
*
* @param dataWidth width of the data to be passed into the functional unit
*/
abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = dataWidth)
{
val r_uop = Reg(new MicroOp())
val do_kill = Wire(Bool())
do_kill := io.req.bits.kill // irrelevant default
when (io.req.fire) {
// update incoming uop
do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill
r_uop := io.req.bits.uop
r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
} .otherwise {
do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill
r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)
}
// assumes at least one pipeline register between request and response
io.resp.bits.uop := r_uop
}
/**
* Divide functional unit.
*
* @param dataWidth data to be passed into the functional unit
*/
class DivUnit(dataWidth: Int)(implicit p: Parameters)
extends IterativeFunctionalUnit(dataWidth)
{
// We don't use the iterative multiply functionality here.
// Instead we use the PipelinedMultiplier
val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))
// request
div.io.req.valid := io.req.valid && !this.do_kill
div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
div.io.req.bits.in1 := io.req.bits.rs1_data
div.io.req.bits.in2 := io.req.bits.rs2_data
div.io.req.bits.tag := DontCare
io.req.ready := div.io.req.ready
// handle pipeline kills and branch misspeculations
div.io.kill := this.do_kill
// response
io.resp.valid := div.io.resp.valid && !this.do_kill
div.io.resp.ready := io.resp.ready
io.resp.bits.data := div.io.resp.bits.data
}
/**
* Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier
*
* @param numStages number of pipeline stages
* @param dataWidth size of the data being passed into the functional unit
*/
class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = dataWidth)
{
val imul = Module(new PipelinedMultiplier(xLen, numStages))
// request
imul.io.req.valid := io.req.valid
imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
imul.io.req.bits.in1 := io.req.bits.rs1_data
imul.io.req.bits.in2 := io.req.bits.rs2_data
imul.io.req.bits.tag := DontCare
// response
io.resp.bits.data := imul.io.resp.bits.data
}
| module FDivSqrtUnit_1( // @[fdiv.scala:84:7]
input clock, // @[fdiv.scala:84:7]
input reset, // @[fdiv.scala:84:7]
output io_req_ready, // @[functional-unit.scala:168:14]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
input io_resp_ready, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14]
input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14]
);
wire io_resp_valid_0; // @[fdiv.scala:84:7]
wire [32:0] _downvert_d2s_io_out; // @[fdiv.scala:211:28]
wire [4:0] _downvert_d2s_io_exceptionFlags; // @[fdiv.scala:211:28]
wire _divsqrt_io_inReady_div; // @[fdiv.scala:143:23]
wire _divsqrt_io_inReady_sqrt; // @[fdiv.scala:143:23]
wire _divsqrt_io_outValid_div; // @[fdiv.scala:143:23]
wire _divsqrt_io_outValid_sqrt; // @[fdiv.scala:143:23]
wire [64:0] _divsqrt_io_out; // @[fdiv.scala:143:23]
wire [4:0] _divsqrt_io_exceptionFlags; // @[fdiv.scala:143:23]
wire [64:0] _in2_upconvert_s2d_io_out; // @[fdiv.scala:112:21]
wire [64:0] _in1_upconvert_s2d_io_out; // @[fdiv.scala:112:21]
wire _fdiv_decoder_io_sigs_ldst; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_wen; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_ren1; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_ren2; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_ren3; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_swap12; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_swap23; // @[fdiv.scala:101:28]
wire [1:0] _fdiv_decoder_io_sigs_typeTagIn; // @[fdiv.scala:101:28]
wire [1:0] _fdiv_decoder_io_sigs_typeTagOut; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_fromint; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_toint; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_fastpipe; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_fma; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_div; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_sqrt; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_wflags; // @[fdiv.scala:101:28]
wire io_req_valid_0 = io_req_valid; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[fdiv.scala:84:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fdiv.scala:84:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fdiv.scala:84:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[fdiv.scala:84:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[fdiv.scala:84:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[fdiv.scala:84:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[fdiv.scala:84:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fdiv.scala:84:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fdiv.scala:84:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fdiv.scala:84:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fdiv.scala:84:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fdiv.scala:84:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fdiv.scala:84:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fdiv.scala:84:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fdiv.scala:84:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fdiv.scala:84:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fdiv.scala:84:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fdiv.scala:84:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fdiv.scala:84:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fdiv.scala:84:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fdiv.scala:84:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fdiv.scala:84:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fdiv.scala:84:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fdiv.scala:84:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fdiv.scala:84:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fdiv.scala:84:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fdiv.scala:84:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[fdiv.scala:84:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fdiv.scala:84:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fdiv.scala:84:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fdiv.scala:84:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[fdiv.scala:84:7]
wire io_resp_ready_0 = io_resp_ready; // @[fdiv.scala:84:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[fdiv.scala:84:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[fdiv.scala:84:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[fdiv.scala:84:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[fdiv.scala:84:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[fdiv.scala:84:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[fdiv.scala:84:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[fdiv.scala:84:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[fdiv.scala:84:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[fdiv.scala:84:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[fdiv.scala:84:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[fdiv.scala:84:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[fdiv.scala:84:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[fdiv.scala:84:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[fdiv.scala:84:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[fdiv.scala:84:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[fdiv.scala:84:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[fdiv.scala:84:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[fdiv.scala:84:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[fdiv.scala:84:7]
wire io_req_bits_pred_data = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_predicated = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[fdiv.scala:84:7]
wire _io_resp_bits_data_T_1 = 1'h0; // @[package.scala:39:86]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[fdiv.scala:84:7]
wire [64:0] _r_buffer_fin_in1_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _r_buffer_fin_in2_T = 65'h0; // @[FPU.scala:372:31]
wire [39:0] io_resp_bits_addr = 40'h0; // @[fdiv.scala:84:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[fdiv.scala:84:7]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[fdiv.scala:84:7]
wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42]
wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56]
wire _io_resp_bits_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42]
wire _io_resp_bits_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56]
wire _io_resp_bits_data_T_3 = 1'h1; // @[package.scala:39:86]
wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26]
wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26]
wire [64:0] _r_out_wdata_double_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27]
wire _io_req_ready_T; // @[fdiv.scala:109:19]
wire [64:0] _r_buffer_fin_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26]
wire [64:0] _r_buffer_fin_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26]
wire _io_resp_valid_T_3; // @[fdiv.scala:218:30]
wire io_resp_bits_fflags_valid_0 = io_resp_valid_0; // @[fdiv.scala:84:7]
wire [64:0] _io_resp_bits_data_T_5; // @[fdiv.scala:221:8]
wire [7:0] _io_resp_bits_fflags_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [4:0] out_flags; // @[fdiv.scala:216:38]
wire io_req_ready_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_rvc_0; // @[fdiv.scala:84:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[fdiv.scala:84:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_br_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_jalr_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_jal_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_sfb_0; // @[fdiv.scala:84:7]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_br_tag_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_edge_inst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_taken_0; // @[fdiv.scala:84:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[fdiv.scala:84:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_stq_idx_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_prs1_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_prs2_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_prs3_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ppred_busy_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_exception_0; // @[fdiv.scala:84:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_bypassable_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_mem_signed_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_fence_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_fencei_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_amo_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_uses_ldq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_uses_stq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_unique_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ldst_val_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_frs3_en_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_fp_val_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_fp_single_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_rvc_0; // @[fdiv.scala:84:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0; // @[fdiv.scala:84:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_br_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_jalr_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_jal_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_sfb_0; // @[fdiv.scala:84:7]
wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_edge_inst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_taken_0; // @[fdiv.scala:84:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0; // @[fdiv.scala:84:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_exception_0; // @[fdiv.scala:84:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_bypassable_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_mem_signed_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_fence_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_fencei_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_amo_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_uses_stq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_unique_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ldst_val_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_frs3_en_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_fp_val_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_fp_single_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[fdiv.scala:84:7]
wire [64:0] io_resp_bits_data_0; // @[fdiv.scala:84:7]
reg r_buffer_val; // @[fdiv.scala:97:29]
reg [6:0] r_buffer_req_uop_uopc; // @[fdiv.scala:98:25]
reg [31:0] r_buffer_req_uop_inst; // @[fdiv.scala:98:25]
reg [31:0] r_buffer_req_uop_debug_inst; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_rvc; // @[fdiv.scala:98:25]
reg [39:0] r_buffer_req_uop_debug_pc; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_iq_type; // @[fdiv.scala:98:25]
reg [9:0] r_buffer_req_uop_fu_code; // @[fdiv.scala:98:25]
reg [3:0] r_buffer_req_uop_ctrl_br_type; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_ctrl_op1_sel; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ctrl_op2_sel; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ctrl_imm_sel; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_ctrl_op_fcn; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_fcn_dw; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ctrl_csr_cmd; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_is_load; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_is_sta; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_is_std; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_iw_state; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_iw_p1_poisoned; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_iw_p2_poisoned; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_br; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_jalr; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_jal; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_sfb; // @[fdiv.scala:98:25]
reg [7:0] r_buffer_req_uop_br_mask; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_br_tag; // @[fdiv.scala:98:25]
reg [3:0] r_buffer_req_uop_ftq_idx; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_edge_inst; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_pc_lob; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_taken; // @[fdiv.scala:98:25]
reg [19:0] r_buffer_req_uop_imm_packed; // @[fdiv.scala:98:25]
reg [11:0] r_buffer_req_uop_csr_addr; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_rob_idx; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ldq_idx; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_stq_idx; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_rxq_idx; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_pdst; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_prs1; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_prs2; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_prs3; // @[fdiv.scala:98:25]
reg [3:0] r_buffer_req_uop_ppred; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_prs1_busy; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_prs2_busy; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_prs3_busy; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ppred_busy; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_stale_pdst; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_exception; // @[fdiv.scala:98:25]
reg [63:0] r_buffer_req_uop_exc_cause; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_bypassable; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_mem_cmd; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_mem_size; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_mem_signed; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_fence; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_fencei; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_amo; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_uses_ldq; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_uses_stq; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_sys_pc2epc; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_unique; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_flush_on_commit; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ldst_is_rs1; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_ldst; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_lrs1; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_lrs2; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_lrs3; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ldst_val; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_dst_rtype; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_lrs1_rtype; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_lrs2_rtype; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_frs3_en; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_fp_val; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_fp_single; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_xcpt_pf_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_xcpt_ae_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_xcpt_ma_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_bp_debug_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_bp_xcpt_if; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_debug_fsrc; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_debug_tsrc; // @[fdiv.scala:98:25]
reg [64:0] r_buffer_req_rs1_data; // @[fdiv.scala:98:25]
reg [64:0] r_buffer_req_rs2_data; // @[fdiv.scala:98:25]
reg r_buffer_req_kill; // @[fdiv.scala:98:25]
reg r_buffer_fin_ldst; // @[fdiv.scala:99:25]
reg r_buffer_fin_wen; // @[fdiv.scala:99:25]
reg r_buffer_fin_ren1; // @[fdiv.scala:99:25]
reg r_buffer_fin_ren2; // @[fdiv.scala:99:25]
reg r_buffer_fin_ren3; // @[fdiv.scala:99:25]
reg r_buffer_fin_swap12; // @[fdiv.scala:99:25]
reg r_buffer_fin_swap23; // @[fdiv.scala:99:25]
reg [1:0] r_buffer_fin_typeTagIn; // @[fdiv.scala:99:25]
reg [1:0] r_buffer_fin_typeTagOut; // @[fdiv.scala:99:25]
reg r_buffer_fin_fromint; // @[fdiv.scala:99:25]
reg r_buffer_fin_toint; // @[fdiv.scala:99:25]
reg r_buffer_fin_fastpipe; // @[fdiv.scala:99:25]
reg r_buffer_fin_fma; // @[fdiv.scala:99:25]
reg r_buffer_fin_div; // @[fdiv.scala:99:25]
reg r_buffer_fin_sqrt; // @[fdiv.scala:99:25]
reg r_buffer_fin_wflags; // @[fdiv.scala:99:25]
reg [2:0] r_buffer_fin_rm; // @[fdiv.scala:99:25]
reg [64:0] r_buffer_fin_in1; // @[fdiv.scala:99:25]
reg [64:0] r_buffer_fin_in2; // @[fdiv.scala:99:25]
wire [7:0] _GEN = io_brupdate_b1_mispredict_mask_0 & r_buffer_req_uop_br_mask; // @[util.scala:118:51]
wire [7:0] _r_buffer_val_T; // @[util.scala:118:51]
assign _r_buffer_val_T = _GEN; // @[util.scala:118:51]
wire [7:0] _r_divsqrt_killed_T_4; // @[util.scala:118:51]
assign _r_divsqrt_killed_T_4 = _GEN; // @[util.scala:118:51]
wire _r_buffer_val_T_1 = |_r_buffer_val_T; // @[util.scala:118:{51,59}]
wire _r_buffer_val_T_2 = ~_r_buffer_val_T_1; // @[util.scala:118:59]
wire _r_buffer_val_T_3 = ~io_req_bits_kill_0; // @[fdiv.scala:84:7, :105:71]
wire _r_buffer_val_T_4 = _r_buffer_val_T_2 & _r_buffer_val_T_3; // @[fdiv.scala:105:{19,68,71}]
wire _r_buffer_val_T_5 = _r_buffer_val_T_4 & r_buffer_val; // @[fdiv.scala:97:29, :105:{68,89}]
wire [7:0] _r_buffer_req_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_buffer_req_uop_br_mask_T_1 = r_buffer_req_uop_br_mask & _r_buffer_req_uop_br_mask_T; // @[util.scala:85:{25,27}]
assign _io_req_ready_T = ~r_buffer_val; // @[fdiv.scala:97:29, :109:19]
assign io_req_ready_0 = _io_req_ready_T; // @[fdiv.scala:84:7, :109:19]
wire _in1_upconvert_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _r_buffer_fin_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _in1_upconvert_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire _r_buffer_fin_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _in1_upconvert_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _r_buffer_fin_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] in1_upconvert_prev_unswizzled_hi = {_in1_upconvert_prev_unswizzled_T, _in1_upconvert_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] in1_upconvert_floats_0 = {in1_upconvert_prev_unswizzled_hi, _in1_upconvert_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _in1_upconvert_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _r_buffer_fin_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire in1_upconvert_prev_isbox = &_in1_upconvert_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire in1_upconvert_oks_0 = in1_upconvert_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire in1_upconvert_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] in1_upconvert_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] in1_upconvert_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _in1_upconvert_fractOut_T = {in1_upconvert_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] in1_upconvert_fractOut = _in1_upconvert_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] in1_upconvert_expOut_expCode = in1_upconvert_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _in1_upconvert_expOut_commonCase_T = {1'h0, in1_upconvert_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _in1_upconvert_expOut_commonCase_T_1 = _in1_upconvert_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _in1_upconvert_expOut_commonCase_T_2 = {1'h0, _in1_upconvert_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] in1_upconvert_expOut_commonCase = _in1_upconvert_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _in1_upconvert_expOut_T = in1_upconvert_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _in1_upconvert_expOut_T_1 = in1_upconvert_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _in1_upconvert_expOut_T_2 = _in1_upconvert_expOut_T | _in1_upconvert_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _in1_upconvert_expOut_T_3 = in1_upconvert_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _in1_upconvert_expOut_T_4 = {in1_upconvert_expOut_expCode, _in1_upconvert_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _in1_upconvert_expOut_T_5 = in1_upconvert_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] in1_upconvert_expOut = _in1_upconvert_expOut_T_2 ? _in1_upconvert_expOut_T_4 : _in1_upconvert_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] in1_upconvert_hi = {in1_upconvert_sign, in1_upconvert_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] in1_upconvert_floats_1 = {in1_upconvert_hi, in1_upconvert_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _in1_upconvert_T = in1_upconvert_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _in1_upconvert_T_1 = in1_upconvert_floats_0 | _in1_upconvert_T; // @[FPU.scala:356:31, :372:{26,31}]
wire _in2_upconvert_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _r_buffer_fin_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _in2_upconvert_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire _r_buffer_fin_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _in2_upconvert_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _r_buffer_fin_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] in2_upconvert_prev_unswizzled_hi = {_in2_upconvert_prev_unswizzled_T, _in2_upconvert_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] in2_upconvert_floats_0 = {in2_upconvert_prev_unswizzled_hi, _in2_upconvert_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _in2_upconvert_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _r_buffer_fin_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire in2_upconvert_prev_isbox = &_in2_upconvert_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire in2_upconvert_oks_0 = in2_upconvert_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire in2_upconvert_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] in2_upconvert_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] in2_upconvert_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _in2_upconvert_fractOut_T = {in2_upconvert_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] in2_upconvert_fractOut = _in2_upconvert_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] in2_upconvert_expOut_expCode = in2_upconvert_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _in2_upconvert_expOut_commonCase_T = {1'h0, in2_upconvert_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _in2_upconvert_expOut_commonCase_T_1 = _in2_upconvert_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _in2_upconvert_expOut_commonCase_T_2 = {1'h0, _in2_upconvert_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] in2_upconvert_expOut_commonCase = _in2_upconvert_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _in2_upconvert_expOut_T = in2_upconvert_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _in2_upconvert_expOut_T_1 = in2_upconvert_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _in2_upconvert_expOut_T_2 = _in2_upconvert_expOut_T | _in2_upconvert_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _in2_upconvert_expOut_T_3 = in2_upconvert_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _in2_upconvert_expOut_T_4 = {in2_upconvert_expOut_expCode, _in2_upconvert_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _in2_upconvert_expOut_T_5 = in2_upconvert_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] in2_upconvert_expOut = _in2_upconvert_expOut_T_2 ? _in2_upconvert_expOut_T_4 : _in2_upconvert_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] in2_upconvert_hi = {in2_upconvert_sign, in2_upconvert_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] in2_upconvert_floats_1 = {in2_upconvert_hi, in2_upconvert_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _in2_upconvert_T = in2_upconvert_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _in2_upconvert_T_1 = in2_upconvert_floats_0 | _in2_upconvert_T; // @[FPU.scala:356:31, :372:{26,31}]
wire [7:0] _r_buffer_req_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_buffer_req_uop_br_mask_T_3 = io_req_bits_uop_br_mask_0 & _r_buffer_req_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
wire [2:0] _r_buffer_fin_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58]
wire [2:0] _r_buffer_fin_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58]
wire _r_buffer_fin_rm_T_1 = &_r_buffer_fin_rm_T; // @[util.scala:289:58]
wire [2:0] _r_buffer_fin_rm_T_3 = _r_buffer_fin_rm_T_1 ? io_fcsr_rm_0 : _r_buffer_fin_rm_T_2; // @[util.scala:289:58]
wire [1:0] r_buffer_fin_in1_prev_unswizzled_hi = {_r_buffer_fin_in1_prev_unswizzled_T, _r_buffer_fin_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] r_buffer_fin_in1_prev_unswizzled = {r_buffer_fin_in1_prev_unswizzled_hi, _r_buffer_fin_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire r_buffer_fin_in1_prev_prev_sign = r_buffer_fin_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] r_buffer_fin_in1_prev_prev_fractIn = r_buffer_fin_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] r_buffer_fin_in1_prev_prev_expIn = r_buffer_fin_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _r_buffer_fin_in1_prev_prev_fractOut_T = {r_buffer_fin_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] r_buffer_fin_in1_prev_prev_fractOut = _r_buffer_fin_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] r_buffer_fin_in1_prev_prev_expOut_expCode = r_buffer_fin_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T = {4'h0, r_buffer_fin_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1 = _r_buffer_fin_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] r_buffer_fin_in1_prev_prev_expOut_commonCase = _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_T_5 = r_buffer_fin_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _r_buffer_fin_in1_prev_prev_expOut_T = r_buffer_fin_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _r_buffer_fin_in1_prev_prev_expOut_T_1 = r_buffer_fin_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _r_buffer_fin_in1_prev_prev_expOut_T_2 = _r_buffer_fin_in1_prev_prev_expOut_T | _r_buffer_fin_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _r_buffer_fin_in1_prev_prev_expOut_T_3 = r_buffer_fin_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_T_4 = {r_buffer_fin_in1_prev_prev_expOut_expCode, _r_buffer_fin_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] r_buffer_fin_in1_prev_prev_expOut = _r_buffer_fin_in1_prev_prev_expOut_T_2 ? _r_buffer_fin_in1_prev_prev_expOut_T_4 : _r_buffer_fin_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] r_buffer_fin_in1_prev_prev_hi = {r_buffer_fin_in1_prev_prev_sign, r_buffer_fin_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] r_buffer_fin_in1_floats_0 = {r_buffer_fin_in1_prev_prev_hi, r_buffer_fin_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire r_buffer_fin_in1_prev_isbox = &_r_buffer_fin_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire r_buffer_fin_in1_oks_0 = r_buffer_fin_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [1:0] r_buffer_fin_in2_prev_unswizzled_hi = {_r_buffer_fin_in2_prev_unswizzled_T, _r_buffer_fin_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] r_buffer_fin_in2_prev_unswizzled = {r_buffer_fin_in2_prev_unswizzled_hi, _r_buffer_fin_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire r_buffer_fin_in2_prev_prev_sign = r_buffer_fin_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] r_buffer_fin_in2_prev_prev_fractIn = r_buffer_fin_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] r_buffer_fin_in2_prev_prev_expIn = r_buffer_fin_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _r_buffer_fin_in2_prev_prev_fractOut_T = {r_buffer_fin_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] r_buffer_fin_in2_prev_prev_fractOut = _r_buffer_fin_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] r_buffer_fin_in2_prev_prev_expOut_expCode = r_buffer_fin_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T = {4'h0, r_buffer_fin_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1 = _r_buffer_fin_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] r_buffer_fin_in2_prev_prev_expOut_commonCase = _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_T_5 = r_buffer_fin_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _r_buffer_fin_in2_prev_prev_expOut_T = r_buffer_fin_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _r_buffer_fin_in2_prev_prev_expOut_T_1 = r_buffer_fin_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _r_buffer_fin_in2_prev_prev_expOut_T_2 = _r_buffer_fin_in2_prev_prev_expOut_T | _r_buffer_fin_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _r_buffer_fin_in2_prev_prev_expOut_T_3 = r_buffer_fin_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_T_4 = {r_buffer_fin_in2_prev_prev_expOut_expCode, _r_buffer_fin_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] r_buffer_fin_in2_prev_prev_expOut = _r_buffer_fin_in2_prev_prev_expOut_T_2 ? _r_buffer_fin_in2_prev_prev_expOut_T_4 : _r_buffer_fin_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] r_buffer_fin_in2_prev_prev_hi = {r_buffer_fin_in2_prev_prev_sign, r_buffer_fin_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] r_buffer_fin_in2_floats_0 = {r_buffer_fin_in2_prev_prev_hi, r_buffer_fin_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire r_buffer_fin_in2_prev_isbox = &_r_buffer_fin_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire r_buffer_fin_in2_oks_0 = r_buffer_fin_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
reg r_divsqrt_val; // @[fdiv.scala:145:30]
reg r_divsqrt_killed; // @[fdiv.scala:146:29]
reg r_divsqrt_fin_ldst; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_wen; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_ren1; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_ren2; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_ren3; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_swap12; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_swap23; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_typeTagIn; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_typeTagOut; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_fromint; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_toint; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_fastpipe; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_fma; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_div; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_sqrt; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_wflags; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_vec; // @[fdiv.scala:147:26]
reg [2:0] r_divsqrt_fin_rm; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_fmaCmd; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_typ; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_fmt; // @[fdiv.scala:147:26]
reg [64:0] r_divsqrt_fin_in1; // @[fdiv.scala:147:26]
reg [64:0] r_divsqrt_fin_in2; // @[fdiv.scala:147:26]
reg [64:0] r_divsqrt_fin_in3; // @[fdiv.scala:147:26]
reg [6:0] r_divsqrt_uop_uopc; // @[fdiv.scala:148:26]
reg [31:0] r_divsqrt_uop_inst; // @[fdiv.scala:148:26]
reg [31:0] r_divsqrt_uop_debug_inst; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_rvc; // @[fdiv.scala:148:26]
reg [39:0] r_divsqrt_uop_debug_pc; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_iq_type; // @[fdiv.scala:148:26]
reg [9:0] r_divsqrt_uop_fu_code; // @[fdiv.scala:148:26]
reg [3:0] r_divsqrt_uop_ctrl_br_type; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_ctrl_op1_sel; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ctrl_op2_sel; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ctrl_imm_sel; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_ctrl_op_fcn; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_fcn_dw; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ctrl_csr_cmd; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_is_load; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_is_sta; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_is_std; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_iw_state; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_iw_p1_poisoned; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_iw_p2_poisoned; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_br; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_jalr; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_jal; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_sfb; // @[fdiv.scala:148:26]
reg [7:0] r_divsqrt_uop_br_mask; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_br_tag; // @[fdiv.scala:148:26]
reg [3:0] r_divsqrt_uop_ftq_idx; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_edge_inst; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_pc_lob; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_taken; // @[fdiv.scala:148:26]
reg [19:0] r_divsqrt_uop_imm_packed; // @[fdiv.scala:148:26]
reg [11:0] r_divsqrt_uop_csr_addr; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_rob_idx; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ldq_idx; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_stq_idx; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_rxq_idx; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_pdst; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_prs1; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_prs2; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_prs3; // @[fdiv.scala:148:26]
reg [3:0] r_divsqrt_uop_ppred; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_prs1_busy; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_prs2_busy; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_prs3_busy; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ppred_busy; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_stale_pdst; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_exception; // @[fdiv.scala:148:26]
reg [63:0] r_divsqrt_uop_exc_cause; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_bypassable; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_mem_cmd; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_mem_size; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_mem_signed; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_fence; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_fencei; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_amo; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_uses_ldq; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_uses_stq; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_sys_pc2epc; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_unique; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_flush_on_commit; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ldst_is_rs1; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_ldst; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_lrs1; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_lrs2; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_lrs3; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ldst_val; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_dst_rtype; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_lrs1_rtype; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_lrs2_rtype; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_frs3_en; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_fp_val; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_fp_single; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_xcpt_pf_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_xcpt_ae_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_xcpt_ma_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_bp_debug_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_bp_xcpt_if; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_debug_fsrc; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_debug_tsrc; // @[fdiv.scala:148:26]
wire _output_buffer_available_T; // @[fdiv.scala:189:30]
wire output_buffer_available; // @[fdiv.scala:151:37]
wire _may_fire_input_T = r_buffer_fin_div | r_buffer_fin_sqrt; // @[fdiv.scala:99:25, :155:23]
wire _may_fire_input_T_1 = r_buffer_val & _may_fire_input_T; // @[fdiv.scala:97:29, :154:18, :155:23]
wire _may_fire_input_T_2 = ~r_divsqrt_val; // @[fdiv.scala:145:30, :156:5]
wire _may_fire_input_T_3 = _may_fire_input_T_1 & _may_fire_input_T_2; // @[fdiv.scala:154:18, :155:45, :156:5]
wire may_fire_input = _may_fire_input_T_3 & output_buffer_available; // @[fdiv.scala:151:37, :155:45, :156:20]
wire divsqrt_ready = r_buffer_fin_sqrt ? _divsqrt_io_inReady_sqrt : _divsqrt_io_inReady_div; // @[fdiv.scala:99:25, :143:23, :159:26]
wire [64:0] _divsqrt_io_b_T = r_buffer_fin_sqrt ? r_buffer_fin_in1 : r_buffer_fin_in2; // @[fdiv.scala:99:25, :163:22]
wire [7:0] _GEN_0 = io_brupdate_b1_mispredict_mask_0 & r_divsqrt_uop_br_mask; // @[util.scala:118:51]
wire [7:0] _r_divsqrt_killed_T; // @[util.scala:118:51]
assign _r_divsqrt_killed_T = _GEN_0; // @[util.scala:118:51]
wire [7:0] _r_out_val_T_1; // @[util.scala:118:51]
assign _r_out_val_T_1 = _GEN_0; // @[util.scala:118:51]
wire _r_divsqrt_killed_T_1 = |_r_divsqrt_killed_T; // @[util.scala:118:{51,59}]
wire _r_divsqrt_killed_T_2 = r_divsqrt_killed | _r_divsqrt_killed_T_1; // @[util.scala:118:59]
wire _r_divsqrt_killed_T_3 = _r_divsqrt_killed_T_2 | io_req_bits_kill_0; // @[fdiv.scala:84:7, :167:{40,88}]
wire [7:0] _r_divsqrt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_divsqrt_uop_br_mask_T_1 = r_divsqrt_uop_br_mask & _r_divsqrt_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire _r_divsqrt_killed_T_5 = |_r_divsqrt_killed_T_4; // @[util.scala:118:{51,59}]
wire _r_divsqrt_killed_T_6 = _r_divsqrt_killed_T_5 | io_req_bits_kill_0; // @[util.scala:118:59]
wire [7:0] _r_divsqrt_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_divsqrt_uop_br_mask_T_3 = r_buffer_req_uop_br_mask & _r_divsqrt_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
reg r_out_val; // @[fdiv.scala:184:26]
reg [6:0] r_out_uop_uopc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_uopc_0 = r_out_uop_uopc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_uopc_0 = r_out_uop_uopc; // @[fdiv.scala:84:7, :185:22]
reg [31:0] r_out_uop_inst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_inst_0 = r_out_uop_inst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_inst_0 = r_out_uop_inst; // @[fdiv.scala:84:7, :185:22]
reg [31:0] r_out_uop_debug_inst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_inst_0 = r_out_uop_debug_inst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_inst_0 = r_out_uop_debug_inst; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_rvc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_rvc_0 = r_out_uop_is_rvc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_rvc_0 = r_out_uop_is_rvc; // @[fdiv.scala:84:7, :185:22]
reg [39:0] r_out_uop_debug_pc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_pc_0 = r_out_uop_debug_pc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_pc_0 = r_out_uop_debug_pc; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_iq_type; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iq_type_0 = r_out_uop_iq_type; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iq_type_0 = r_out_uop_iq_type; // @[fdiv.scala:84:7, :185:22]
reg [9:0] r_out_uop_fu_code; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_fu_code_0 = r_out_uop_fu_code; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_fu_code_0 = r_out_uop_fu_code; // @[fdiv.scala:84:7, :185:22]
reg [3:0] r_out_uop_ctrl_br_type; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_br_type_0 = r_out_uop_ctrl_br_type; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = r_out_uop_ctrl_br_type; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_ctrl_op1_sel; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_out_uop_ctrl_op1_sel; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = r_out_uop_ctrl_op1_sel; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ctrl_op2_sel; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_out_uop_ctrl_op2_sel; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = r_out_uop_ctrl_op2_sel; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ctrl_imm_sel; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_out_uop_ctrl_imm_sel; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = r_out_uop_ctrl_imm_sel; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_ctrl_op_fcn; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_out_uop_ctrl_op_fcn; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = r_out_uop_ctrl_op_fcn; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_is_load; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_is_load_0 = r_out_uop_ctrl_is_load; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = r_out_uop_ctrl_is_load; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_is_sta; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_out_uop_ctrl_is_sta; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = r_out_uop_ctrl_is_sta; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_is_std; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_is_std_0 = r_out_uop_ctrl_is_std; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = r_out_uop_ctrl_is_std; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_iw_state; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iw_state_0 = r_out_uop_iw_state; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iw_state_0 = r_out_uop_iw_state; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_iw_p1_poisoned; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_out_uop_iw_p1_poisoned; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = r_out_uop_iw_p1_poisoned; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_iw_p2_poisoned; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_out_uop_iw_p2_poisoned; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = r_out_uop_iw_p2_poisoned; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_br; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_br_0 = r_out_uop_is_br; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_br_0 = r_out_uop_is_br; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_jalr; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_jalr_0 = r_out_uop_is_jalr; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_jalr_0 = r_out_uop_is_jalr; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_jal; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_jal_0 = r_out_uop_is_jal; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_jal_0 = r_out_uop_is_jal; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_sfb; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_sfb_0 = r_out_uop_is_sfb; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_sfb_0 = r_out_uop_is_sfb; // @[fdiv.scala:84:7, :185:22]
reg [7:0] r_out_uop_br_mask; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_br_mask_0 = r_out_uop_br_mask; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_br_tag; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_br_tag_0 = r_out_uop_br_tag; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_br_tag_0 = r_out_uop_br_tag; // @[fdiv.scala:84:7, :185:22]
reg [3:0] r_out_uop_ftq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ftq_idx_0 = r_out_uop_ftq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ftq_idx_0 = r_out_uop_ftq_idx; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_edge_inst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_edge_inst_0 = r_out_uop_edge_inst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_edge_inst_0 = r_out_uop_edge_inst; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_pc_lob; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_pc_lob_0 = r_out_uop_pc_lob; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_pc_lob_0 = r_out_uop_pc_lob; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_taken; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_taken_0 = r_out_uop_taken; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_taken_0 = r_out_uop_taken; // @[fdiv.scala:84:7, :185:22]
reg [19:0] r_out_uop_imm_packed; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_imm_packed_0 = r_out_uop_imm_packed; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_imm_packed_0 = r_out_uop_imm_packed; // @[fdiv.scala:84:7, :185:22]
reg [11:0] r_out_uop_csr_addr; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_csr_addr_0 = r_out_uop_csr_addr; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_csr_addr_0 = r_out_uop_csr_addr; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_rob_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_rob_idx_0 = r_out_uop_rob_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_rob_idx_0 = r_out_uop_rob_idx; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ldq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldq_idx_0 = r_out_uop_ldq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldq_idx_0 = r_out_uop_ldq_idx; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_stq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_stq_idx_0 = r_out_uop_stq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_stq_idx_0 = r_out_uop_stq_idx; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_rxq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_rxq_idx_0 = r_out_uop_rxq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_rxq_idx_0 = r_out_uop_rxq_idx; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_pdst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_pdst_0 = r_out_uop_pdst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_pdst_0 = r_out_uop_pdst; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_prs1; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs1_0 = r_out_uop_prs1; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs1_0 = r_out_uop_prs1; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_prs2; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs2_0 = r_out_uop_prs2; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs2_0 = r_out_uop_prs2; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_prs3; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs3_0 = r_out_uop_prs3; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs3_0 = r_out_uop_prs3; // @[fdiv.scala:84:7, :185:22]
reg [3:0] r_out_uop_ppred; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ppred_0 = r_out_uop_ppred; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ppred_0 = r_out_uop_ppred; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_prs1_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs1_busy_0 = r_out_uop_prs1_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs1_busy_0 = r_out_uop_prs1_busy; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_prs2_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs2_busy_0 = r_out_uop_prs2_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs2_busy_0 = r_out_uop_prs2_busy; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_prs3_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs3_busy_0 = r_out_uop_prs3_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs3_busy_0 = r_out_uop_prs3_busy; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ppred_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ppred_busy_0 = r_out_uop_ppred_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ppred_busy_0 = r_out_uop_ppred_busy; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_stale_pdst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_stale_pdst_0 = r_out_uop_stale_pdst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_stale_pdst_0 = r_out_uop_stale_pdst; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_exception; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_exception_0 = r_out_uop_exception; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_exception_0 = r_out_uop_exception; // @[fdiv.scala:84:7, :185:22]
reg [63:0] r_out_uop_exc_cause; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_exc_cause_0 = r_out_uop_exc_cause; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_exc_cause_0 = r_out_uop_exc_cause; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_bypassable; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_bypassable_0 = r_out_uop_bypassable; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_bypassable_0 = r_out_uop_bypassable; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_mem_cmd; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_mem_cmd_0 = r_out_uop_mem_cmd; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_mem_cmd_0 = r_out_uop_mem_cmd; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_mem_size; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_mem_size_0 = r_out_uop_mem_size; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_mem_size_0 = r_out_uop_mem_size; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_mem_signed; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_mem_signed_0 = r_out_uop_mem_signed; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_mem_signed_0 = r_out_uop_mem_signed; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_fence; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_fence_0 = r_out_uop_is_fence; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_fence_0 = r_out_uop_is_fence; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_fencei; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_fencei_0 = r_out_uop_is_fencei; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_fencei_0 = r_out_uop_is_fencei; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_amo; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_amo_0 = r_out_uop_is_amo; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_amo_0 = r_out_uop_is_amo; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_uses_ldq; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_uses_ldq_0 = r_out_uop_uses_ldq; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_uses_ldq_0 = r_out_uop_uses_ldq; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_uses_stq; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_uses_stq_0 = r_out_uop_uses_stq; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_uses_stq_0 = r_out_uop_uses_stq; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_sys_pc2epc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_out_uop_is_sys_pc2epc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = r_out_uop_is_sys_pc2epc; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_unique; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_unique_0 = r_out_uop_is_unique; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_unique_0 = r_out_uop_is_unique; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_flush_on_commit; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_flush_on_commit_0 = r_out_uop_flush_on_commit; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_flush_on_commit_0 = r_out_uop_flush_on_commit; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ldst_is_rs1; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_out_uop_ldst_is_rs1; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = r_out_uop_ldst_is_rs1; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_ldst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldst_0 = r_out_uop_ldst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldst_0 = r_out_uop_ldst; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_lrs1; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs1_0 = r_out_uop_lrs1; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs1_0 = r_out_uop_lrs1; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_lrs2; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs2_0 = r_out_uop_lrs2; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs2_0 = r_out_uop_lrs2; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_lrs3; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs3_0 = r_out_uop_lrs3; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs3_0 = r_out_uop_lrs3; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ldst_val; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldst_val_0 = r_out_uop_ldst_val; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldst_val_0 = r_out_uop_ldst_val; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_dst_rtype; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_dst_rtype_0 = r_out_uop_dst_rtype; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_dst_rtype_0 = r_out_uop_dst_rtype; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_lrs1_rtype; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs1_rtype_0 = r_out_uop_lrs1_rtype; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = r_out_uop_lrs1_rtype; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_lrs2_rtype; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs2_rtype_0 = r_out_uop_lrs2_rtype; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = r_out_uop_lrs2_rtype; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_frs3_en; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_frs3_en_0 = r_out_uop_frs3_en; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_frs3_en_0 = r_out_uop_frs3_en; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_fp_val; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_fp_val_0 = r_out_uop_fp_val; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_fp_val_0 = r_out_uop_fp_val; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_fp_single; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_fp_single_0 = r_out_uop_fp_single; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_fp_single_0 = r_out_uop_fp_single; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_xcpt_pf_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_out_uop_xcpt_pf_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = r_out_uop_xcpt_pf_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_xcpt_ae_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_out_uop_xcpt_ae_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = r_out_uop_xcpt_ae_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_xcpt_ma_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_out_uop_xcpt_ma_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = r_out_uop_xcpt_ma_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_bp_debug_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_bp_debug_if_0 = r_out_uop_bp_debug_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_bp_debug_if_0 = r_out_uop_bp_debug_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_bp_xcpt_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_out_uop_bp_xcpt_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = r_out_uop_bp_xcpt_if; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_debug_fsrc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_fsrc_0 = r_out_uop_debug_fsrc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_fsrc_0 = r_out_uop_debug_fsrc; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_debug_tsrc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_tsrc_0 = r_out_uop_debug_tsrc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_tsrc_0 = r_out_uop_debug_tsrc; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_flags_double; // @[fdiv.scala:186:31]
reg [64:0] r_out_wdata_double; // @[fdiv.scala:187:31]
wire [64:0] _io_resp_bits_data_T_4 = r_out_wdata_double; // @[package.scala:39:76]
assign _output_buffer_available_T = ~r_out_val; // @[fdiv.scala:184:26, :189:30]
assign output_buffer_available = _output_buffer_available_T; // @[fdiv.scala:151:37, :189:30]
wire [7:0] _r_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_out_uop_br_mask_T_1 = r_out_uop_br_mask & _r_out_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_out_uop_br_mask; // @[util.scala:118:51]
wire _T_21 = _divsqrt_io_outValid_div | _divsqrt_io_outValid_sqrt; // @[fdiv.scala:143:23, :196:33]
wire _r_out_val_T = ~r_divsqrt_killed; // @[fdiv.scala:146:29, :199:18]
wire _r_out_val_T_2 = |_r_out_val_T_1; // @[util.scala:118:{51,59}]
wire _r_out_val_T_3 = ~_r_out_val_T_2; // @[util.scala:118:59]
wire _r_out_val_T_4 = _r_out_val_T & _r_out_val_T_3; // @[fdiv.scala:199:{18,36,39}]
wire _r_out_val_T_5 = ~io_req_bits_kill_0; // @[fdiv.scala:84:7, :105:71, :199:88]
wire _r_out_val_T_6 = _r_out_val_T_4 & _r_out_val_T_5; // @[fdiv.scala:199:{36,85,88}]
wire [7:0] _r_out_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_out_uop_br_mask_T_3 = r_divsqrt_uop_br_mask & _r_out_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
wire [64:0] r_out_wdata_double_maskedNaN = _divsqrt_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25]
wire [2:0] _r_out_wdata_double_T = _divsqrt_io_out[63:61]; // @[FPU.scala:249:25]
wire _r_out_wdata_double_T_1 = &_r_out_wdata_double_T; // @[FPU.scala:249:{25,56}]
wire [64:0] _r_out_wdata_double_T_2 = _r_out_wdata_double_T_1 ? r_out_wdata_double_maskedNaN : _divsqrt_io_out; // @[FPU.scala:249:56, :413:25, :414:10] |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w5_i0_2( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
output [4:0] io_q // @[AsyncResetReg.scala:59:14]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire [4:0] io_d = 5'h0; // @[AsyncResetReg.scala:56:7]
wire [4:0] io_q_0; // @[AsyncResetReg.scala:56:7]
reg [4:0] reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 5'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= 5'h0; // @[AsyncResetReg.scala:61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_170( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_23( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h17; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h1A; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h1D; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h20; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h8; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h8; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_192( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_340 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
| module MulAddRecFNToRaw_preMul_e8_s24_15( // @[MulAddRecFN.scala:71:7]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [10:0] _sExpAlignedProd_T = 11'h12B; // @[MulAddRecFN.scala:100:19]
wire [11:0] _sExpAlignedProd_T_1 = 12'h46; // @[MulAddRecFN.scala:100:32]
wire [10:0] _sExpAlignedProd_T_2 = 11'h46; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = 11'h46; // @[MulAddRecFN.scala:100:32]
wire [32:0] reduced4CExtra_shift = 33'h100000000; // @[primitives.scala:76:56]
wire [3:0] _reduced4CExtra_T_4 = 4'h0; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = 4'h0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_3 = 6'h0; // @[primitives.scala:77:20, :78:22]
wire [5:0] _reduced4CExtra_T_18 = 6'h0; // @[primitives.scala:77:20, :78:22]
wire [6:0] CAlignDist = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68]
wire [11:0] _io_toPostMul_sExpSum_T = 12'h2E; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = 11'h2E; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = 11'h2E; // @[MulAddRecFN.scala:158:53]
wire [4:0] io_toPostMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47]
wire [4:0] _reduced4CExtra_T_2 = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47]
wire io_toPostMul_isZeroA = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _signProd_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _isMinCAlign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire isMinCAlign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _CIsDominant_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _reduced4CExtra_T_6 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_15 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = 1'h0; // @[primitives.scala:77:20]
wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11]
wire _io_toPostMul_isSigNaNAny_T = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_2 = 1'h0; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_6 = 1'h0; // @[MulAddRecFN.scala:146:32]
wire _io_toPostMul_isNaNAOrB_T = 1'h0; // @[MulAddRecFN.scala:148:42]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16]
wire [23:0] io_mulAddA = 24'h0; // @[MulAddRecFN.scala:71:7, :74:16, :141:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_5 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_8 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_9 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_12 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_14 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_17 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _doSubMags_T = ~rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _sNatCAlignDist_T = 12'h46 - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
assign CIsDominant = _CIsDominant_T; // @[MulAddRecFN.scala:110:{9,23}]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = _mainAlignedSigC_T_4; // @[MulAddRecFN.scala:120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:53:28, :55:23, :61:32]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : 11'h2E; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_186( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_3( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [53:0] _roundMask_T = 54'h0; // @[RoundAnyRawFNToRecFN.scala:153:36]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [55:0] roundMask = 56'h3; // @[RoundAnyRawFNToRecFN.scala:153:55]
wire [56:0] _shiftedRoundMask_T = 57'h3; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [55:0] shiftedRoundMask = 56'h1; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [55:0] _roundPosMask_T = 56'hFFFFFFFFFFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [55:0] roundPosMask = 56'h2; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [55:0] _roundedSig_T_10 = 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [54:0] _roundedSig_T_6 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [54:0] _roundedSig_T_14 = 55'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [11:0] _expOut_T_12 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [11:0] _expOut_T_11 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [11:0] _expOut_T_18 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [11:0] _expOut_T_20 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [51:0] _fractOut_T_2 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire [12:0] _sAdjustedExp_T = {{4{io_in_sExp_0[8]}}, io_in_sExp_0} + 13'h780; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [54:0] _adjustedSig_T = io_in_sig_0[64:10]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23]
wire [9:0] _adjustedSig_T_1 = io_in_sig_0[9:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26]
wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}]
wire [55:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60]
wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [55:0] _roundPosBit_T = adjustedSig & 56'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [55:0] _anyRoundExtra_T = adjustedSig & 56'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [55:0] _roundedSig_T = adjustedSig | 56'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32]
wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [54:0] _roundedSig_T_7 = {54'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}]
wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [55:0] _roundedSig_T_11 = adjustedSig & 56'hFFFFFFFFFFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}]
wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [54:0] _roundedSig_T_15 = {54'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}]
wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [13:0] sRoundedExp = {sAdjustedExp[12], sAdjustedExp} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [11:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [11:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [11:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? 52'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_220( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_400 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_326( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File recFNFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object recFNFromFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val rawIn = rawFloatFromFN(expWidth, sigWidth, in)
rawIn.sign ##
(Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) |
Mux(rawIn.isNaN, 1.U, 0.U)) ##
rawIn.sExp(expWidth - 3, 0) ##
rawIn.sig(sigWidth - 2, 0)
}
}
File VectorScalarMultiplier.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
class VectorScalarMultiplierReq[T <: Data, U <: Data, Tag <: Data](block_cols: Int, t: T, u: U, tag_t: Tag) extends Bundle {
val in: Vec[T] = Vec(block_cols, t.cloneType)
val scale: U = u.cloneType
val repeats: UInt = UInt(16.W) // TODO magic number
val pixel_repeats: UInt = UInt(8.W) // TODO magic number
val last: Bool = Bool()
val tag: Tag = tag_t.cloneType
}
class VectorScalarMultiplierResp[T <: Data, Tag <: Data](block_cols: Int, t: T, tag_t: Tag) extends Bundle {
val out: Vec[T] = Vec(block_cols, t.cloneType)
val row: UInt = UInt(16.W) // TODO magic number
val last: Bool = Bool()
val tag: Tag = tag_t.cloneType
}
class DataWithIndex[T <: Data, U <: Data](t: T, u: U) extends Bundle {
val data = t.cloneType
val scale = u.cloneType
val id = UInt(2.W) // TODO hardcoded
val index = UInt()
}
class ScalePipe[T <: Data, U <: Data](t: T, mvin_scale_args: ScaleArguments[T, U]) extends Module {
val u = mvin_scale_args.multiplicand_t
val io = IO(new Bundle {
val in = Input(Valid(new DataWithIndex(t, u)))
val out = Output(Valid(new DataWithIndex(t, u)))
})
val latency = mvin_scale_args.latency
val out = WireInit(io.in)
out.bits.data := mvin_scale_args.scale_func(io.in.bits.data, io.in.bits.scale.asTypeOf(u))
io.out := Pipe(out, latency)
}
class VectorScalarMultiplier[T <: Data, U <: Data, Tag <: Data](
mvin_scale_args: Option[ScaleArguments[T, U]], block_cols: Int, t: T, tag_t: Tag
) extends Module {
val (u, num_scale_units, always_identity) = mvin_scale_args match {
case Some(ScaleArguments(_, _, multiplicand_t, num_scale_units, _, _)) => (multiplicand_t, num_scale_units, false)
case None => (Bool(), -1, true) // TODO make this a 0-width UInt
}
val io = IO(new Bundle {
val req = Flipped(Decoupled(new VectorScalarMultiplierReq(block_cols, t, u, tag_t)))
val resp = Decoupled(new VectorScalarMultiplierResp(block_cols, t, tag_t))
})
val width = block_cols
val latency = mvin_scale_args match {
case Some(ScaleArguments(_, latency, _, _, _, _)) => latency
case None => 0
}
val in = Reg(Valid(new VectorScalarMultiplierReq(block_cols, t, u, tag_t)))
val in_fire = WireInit(false.B)
io.req.ready := !in.valid || (in.bits.repeats === 0.U && in_fire)
when (io.req.fire) {
in.valid := io.req.valid
in.bits := io.req.bits
} .elsewhen (in_fire) {
when (in.bits.repeats === 0.U) {
in.valid := false.B
}
in.bits.repeats := in.bits.repeats - 1.U
}
when (reset.asBool) {
in.valid := false.B
}
if (num_scale_units == -1) {
val pipe = Module(new Pipeline[VectorScalarMultiplierResp[T, Tag]](
new VectorScalarMultiplierResp(block_cols, t, tag_t),
latency
)())
io.resp <> pipe.io.out
in_fire := pipe.io.in.fire
pipe.io.in.valid := in.valid
pipe.io.in.bits.tag := in.bits.tag
pipe.io.in.bits.last := in.bits.repeats === 0.U && in.bits.last
pipe.io.in.bits.row := in.bits.repeats
pipe.io.in.bits.out := (mvin_scale_args match {
case Some(ScaleArguments(mvin_scale_func, _, multiplicand_t, _, _, _)) =>
in.bits.in.map(x => mvin_scale_func(x, in.bits.scale.asTypeOf(multiplicand_t)))
case None => in.bits.in
})
} else {
val nEntries = 3
val regs = Reg(Vec(nEntries, Valid(new VectorScalarMultiplierReq(block_cols, t, u, tag_t))))
val out_regs = Reg(Vec(nEntries, new VectorScalarMultiplierResp(block_cols, t, tag_t)))
val fired_masks = Reg(Vec(nEntries, Vec(width, Bool())))
val completed_masks = Reg(Vec(nEntries, Vec(width, Bool())))
val head_oh = RegInit(1.U(nEntries.W))
val tail_oh = RegInit(1.U(nEntries.W))
io.resp.valid := Mux1H(head_oh.asBools, (regs zip completed_masks).map({case (r,c) => r.valid && c.reduce(_&&_)}))
io.resp.bits := Mux1H(head_oh.asBools, out_regs)
when (io.resp.fire) {
for (i <- 0 until nEntries) {
when (head_oh(i)) {
regs(i).valid := false.B
}
}
head_oh := (head_oh << 1) | head_oh(nEntries-1)
}
in_fire := (in.valid &&
(!Mux1H(tail_oh.asBools, regs.map(_.valid)))
)
when (in_fire) {
for (i <- 0 until nEntries) {
when (tail_oh(i)) {
regs(i).valid := true.B
regs(i).bits := in.bits
out_regs(i).tag := in.bits.tag
out_regs(i).last := in.bits.repeats === 0.U && in.bits.last
out_regs(i).row := in.bits.repeats
out_regs(i).out := in.bits.in
val identity = (u match {
case u: UInt => Arithmetic.UIntArithmetic.cast(u).identity
case s: SInt => Arithmetic.SIntArithmetic.cast(s).identity
case f: Float => Arithmetic.FloatArithmetic.cast(f).identity
case b: Bool => 1.U(1.W)
})
fired_masks(i).foreach(_ := in.bits.scale.asUInt === identity.asUInt || always_identity.B)
completed_masks(i).foreach(_ := in.bits.scale.asUInt === identity.asUInt || always_identity.B)
}
}
tail_oh := (tail_oh << 1) | tail_oh(nEntries-1)
}
val inputs = Seq.fill(width*nEntries) { Wire(Decoupled(new DataWithIndex(t, u))) }
for (i <- 0 until nEntries) {
for (w <- 0 until width) {
val input = inputs(i*width+w)
input.valid := regs(i).valid && !fired_masks(i)(w)
input.bits.data := regs(i).bits.in(w)
input.bits.scale := regs(i).bits.scale.asTypeOf(u)
input.bits.id := i.U
input.bits.index := w.U
when (input.fire) {
fired_masks(i)(w) := true.B
}
}
}
for (i <- 0 until num_scale_units) {
val arbIn = inputs.zipWithIndex.filter({ case (_, w) => w % num_scale_units == i }).map(_._1)
val arb = Module(new RRArbiter(new DataWithIndex(t, u), arbIn.length))
arb.io.in <> arbIn
arb.io.out.ready := true.B
val arbOut = Reg(Valid(new DataWithIndex(t, u)))
arbOut.valid := arb.io.out.valid
arbOut.bits := arb.io.out.bits
when (reset.asBool) {
arbOut.valid := false.B
}
val pipe = Module(new ScalePipe(t, mvin_scale_args.get))
pipe.io.in := arbOut
val pipe_out = pipe.io.out
for (j <- 0 until nEntries) {
for (w <- 0 until width) {
if ((j*width+w) % num_scale_units == i) {
when (pipe_out.fire && pipe_out.bits.id === j.U && pipe_out.bits.index === w.U) {
out_regs(j).out(w) := pipe_out.bits.data
completed_masks(j)(w) := true.B
}
}
}
}
}
when (reset.asBool) {
regs.foreach(_.valid := false.B)
}
}
}
object VectorScalarMultiplier {
// Returns the input and output IO of the module (together with the pipeline)
def apply[T <: Data, U <: Data, Tag <: Data](
scale_args: Option[ScaleArguments[T, U]],
t: T, cols: Int, tag_t: Tag,
is_acc: Boolean,
is_mvin: Boolean=true
) = {
assert(!is_acc || is_mvin)
val vsm = Module(new VectorScalarMultiplier(scale_args, cols, t, tag_t))
val vsm_in_q = Module(new Queue(chiselTypeOf(vsm.io.req.bits), 2))
vsm.io.req <> vsm_in_q.io.deq
(vsm_in_q.io.enq, vsm.io.resp)
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
File fNFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object fNFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in)
val isSubnormal = rawIn.sExp < minNormExp.S
val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0)
val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0)
val expOut =
Mux(isSubnormal,
0.U,
rawIn.sExp(expWidth - 1, 0) -
((BigInt(1)<<(expWidth - 1)) + 1).U
) | Fill(expWidth, rawIn.isNaN || rawIn.isInf)
val fractOut =
Mux(isSubnormal,
denormFract,
Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0))
)
Cat(rawIn.sign, expOut, fractOut)
}
}
File rawFloatFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object rawFloatFromFN {
def apply(expWidth: Int, sigWidth: Int, in: Bits) = {
val sign = in(expWidth + sigWidth - 1)
val expIn = in(expWidth + sigWidth - 2, sigWidth - 1)
val fractIn = in(sigWidth - 2, 0)
val isZeroExpIn = (expIn === 0.U)
val isZeroFractIn = (fractIn === 0.U)
val normDist = countLeadingZeros(fractIn)
val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1
val adjustedExp =
Mux(isZeroExpIn,
normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U,
expIn
) + ((BigInt(1) << (expWidth - 1)).U
| Mux(isZeroExpIn, 2.U, 1.U))
val isZero = isZeroExpIn && isZeroFractIn
val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && !isZeroFractIn
out.isInf := isSpecial && isZeroFractIn
out.isZero := isZero
out.sign := sign
out.sExp := adjustedExp(expWidth, 0).zext
out.sig :=
0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn)
out
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module VectorScalarMultiplier( // @[VectorScalarMultiplier.scala:45:7]
input clock, // @[VectorScalarMultiplier.scala:45:7]
input reset, // @[VectorScalarMultiplier.scala:45:7]
output io_req_ready, // @[VectorScalarMultiplier.scala:54:14]
input io_req_valid, // @[VectorScalarMultiplier.scala:54:14]
input [31:0] io_req_bits_in_0_bits, // @[VectorScalarMultiplier.scala:54:14]
input [31:0] io_req_bits_in_1_bits, // @[VectorScalarMultiplier.scala:54:14]
input [31:0] io_req_bits_in_2_bits, // @[VectorScalarMultiplier.scala:54:14]
input [31:0] io_req_bits_in_3_bits, // @[VectorScalarMultiplier.scala:54:14]
input [31:0] io_req_bits_scale_bits, // @[VectorScalarMultiplier.scala:54:14]
input [15:0] io_req_bits_repeats, // @[VectorScalarMultiplier.scala:54:14]
input [7:0] io_req_bits_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_last, // @[VectorScalarMultiplier.scala:54:14]
input [127:0] io_req_bits_tag_data, // @[VectorScalarMultiplier.scala:54:14]
input [13:0] io_req_bits_tag_addr, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_0, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_1, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_2, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_3, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_4, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_5, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_6, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_7, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_8, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_9, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_10, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_11, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_12, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_13, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_14, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_mask_15, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_is_acc, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_accumulate, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_has_acc_bitwidth, // @[VectorScalarMultiplier.scala:54:14]
input [31:0] io_req_bits_tag_scale, // @[VectorScalarMultiplier.scala:54:14]
input [15:0] io_req_bits_tag_repeats, // @[VectorScalarMultiplier.scala:54:14]
input [15:0] io_req_bits_tag_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14]
input [15:0] io_req_bits_tag_len, // @[VectorScalarMultiplier.scala:54:14]
input io_req_bits_tag_last, // @[VectorScalarMultiplier.scala:54:14]
input [7:0] io_req_bits_tag_bytes_read, // @[VectorScalarMultiplier.scala:54:14]
input [7:0] io_req_bits_tag_cmd_id, // @[VectorScalarMultiplier.scala:54:14]
input io_resp_ready, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_valid, // @[VectorScalarMultiplier.scala:54:14]
output [31:0] io_resp_bits_out_0_bits, // @[VectorScalarMultiplier.scala:54:14]
output [31:0] io_resp_bits_out_1_bits, // @[VectorScalarMultiplier.scala:54:14]
output [31:0] io_resp_bits_out_2_bits, // @[VectorScalarMultiplier.scala:54:14]
output [31:0] io_resp_bits_out_3_bits, // @[VectorScalarMultiplier.scala:54:14]
output [15:0] io_resp_bits_row, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_last, // @[VectorScalarMultiplier.scala:54:14]
output [127:0] io_resp_bits_tag_data, // @[VectorScalarMultiplier.scala:54:14]
output [13:0] io_resp_bits_tag_addr, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_0, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_1, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_2, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_3, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_4, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_5, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_6, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_7, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_8, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_9, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_10, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_11, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_12, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_13, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_14, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_mask_15, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_is_acc, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_accumulate, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_has_acc_bitwidth, // @[VectorScalarMultiplier.scala:54:14]
output [31:0] io_resp_bits_tag_scale, // @[VectorScalarMultiplier.scala:54:14]
output [15:0] io_resp_bits_tag_repeats, // @[VectorScalarMultiplier.scala:54:14]
output [15:0] io_resp_bits_tag_pixel_repeats, // @[VectorScalarMultiplier.scala:54:14]
output [15:0] io_resp_bits_tag_len, // @[VectorScalarMultiplier.scala:54:14]
output io_resp_bits_tag_last, // @[VectorScalarMultiplier.scala:54:14]
output [7:0] io_resp_bits_tag_bytes_read, // @[VectorScalarMultiplier.scala:54:14]
output [7:0] io_resp_bits_tag_cmd_id // @[VectorScalarMultiplier.scala:54:14]
);
wire self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _muladder_3_io_out; // @[Arithmetic.scala:342:30]
wire [32:0] _t_resizer_3_io_out; // @[Arithmetic.scala:336:32]
wire [32:0] _muladder_2_io_out; // @[Arithmetic.scala:342:30]
wire [32:0] _t_resizer_2_io_out; // @[Arithmetic.scala:336:32]
wire [32:0] _muladder_1_io_out; // @[Arithmetic.scala:342:30]
wire [32:0] _t_resizer_1_io_out; // @[Arithmetic.scala:336:32]
wire [32:0] _muladder_io_out; // @[Arithmetic.scala:342:30]
wire [32:0] _t_resizer_io_out; // @[Arithmetic.scala:336:32]
wire _pipe_io_in_ready; // @[VectorScalarMultiplier.scala:83:22]
wire io_req_valid_0 = io_req_valid; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_req_bits_in_0_bits_0 = io_req_bits_in_0_bits; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_req_bits_in_1_bits_0 = io_req_bits_in_1_bits; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_req_bits_in_2_bits_0 = io_req_bits_in_2_bits; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_req_bits_in_3_bits_0 = io_req_bits_in_3_bits; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_req_bits_scale_bits_0 = io_req_bits_scale_bits; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[VectorScalarMultiplier.scala:45:7]
wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_last_0 = io_req_bits_last; // @[VectorScalarMultiplier.scala:45:7]
wire [127:0] io_req_bits_tag_data_0 = io_req_bits_tag_data; // @[VectorScalarMultiplier.scala:45:7]
wire [13:0] io_req_bits_tag_addr_0 = io_req_bits_tag_addr; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_0_0 = io_req_bits_tag_mask_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_1_0 = io_req_bits_tag_mask_1; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_2_0 = io_req_bits_tag_mask_2; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_3_0 = io_req_bits_tag_mask_3; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_4_0 = io_req_bits_tag_mask_4; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_5_0 = io_req_bits_tag_mask_5; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_6_0 = io_req_bits_tag_mask_6; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_7_0 = io_req_bits_tag_mask_7; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_8_0 = io_req_bits_tag_mask_8; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_9_0 = io_req_bits_tag_mask_9; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_10_0 = io_req_bits_tag_mask_10; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_11_0 = io_req_bits_tag_mask_11; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_12_0 = io_req_bits_tag_mask_12; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_13_0 = io_req_bits_tag_mask_13; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_14_0 = io_req_bits_tag_mask_14; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_mask_15_0 = io_req_bits_tag_mask_15; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_is_acc_0 = io_req_bits_tag_is_acc; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_accumulate_0 = io_req_bits_tag_accumulate; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_has_acc_bitwidth_0 = io_req_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_req_bits_tag_scale_0 = io_req_bits_tag_scale; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_req_bits_tag_repeats_0 = io_req_bits_tag_repeats; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_req_bits_tag_pixel_repeats_0 = io_req_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_req_bits_tag_len_0 = io_req_bits_tag_len; // @[VectorScalarMultiplier.scala:45:7]
wire io_req_bits_tag_last_0 = io_req_bits_tag_last; // @[VectorScalarMultiplier.scala:45:7]
wire [7:0] io_req_bits_tag_bytes_read_0 = io_req_bits_tag_bytes_read; // @[VectorScalarMultiplier.scala:45:7]
wire [7:0] io_req_bits_tag_cmd_id_0 = io_req_bits_tag_cmd_id; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_ready_0 = io_resp_ready; // @[VectorScalarMultiplier.scala:45:7]
wire _io_req_ready_T_3; // @[VectorScalarMultiplier.scala:67:29]
wire io_req_ready_0; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_resp_bits_out_0_bits_0; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_resp_bits_out_1_bits_0; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_resp_bits_out_2_bits_0; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_resp_bits_out_3_bits_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7]
wire [127:0] io_resp_bits_tag_data_0; // @[VectorScalarMultiplier.scala:45:7]
wire [13:0] io_resp_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_has_acc_bitwidth_0; // @[VectorScalarMultiplier.scala:45:7]
wire [31:0] io_resp_bits_tag_scale_0; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_resp_bits_tag_repeats_0; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_resp_bits_tag_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_resp_bits_tag_len_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_tag_last_0; // @[VectorScalarMultiplier.scala:45:7]
wire [7:0] io_resp_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7]
wire [7:0] io_resp_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7]
wire [15:0] io_resp_bits_row_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_bits_last_0; // @[VectorScalarMultiplier.scala:45:7]
wire io_resp_valid_0; // @[VectorScalarMultiplier.scala:45:7]
reg in_valid; // @[VectorScalarMultiplier.scala:65:15]
reg [31:0] in_bits_in_0_bits; // @[VectorScalarMultiplier.scala:65:15]
reg [31:0] in_bits_in_1_bits; // @[VectorScalarMultiplier.scala:65:15]
reg [31:0] in_bits_in_2_bits; // @[VectorScalarMultiplier.scala:65:15]
reg [31:0] in_bits_in_3_bits; // @[VectorScalarMultiplier.scala:65:15]
reg [31:0] in_bits_scale_bits; // @[VectorScalarMultiplier.scala:65:15]
reg [15:0] in_bits_repeats; // @[VectorScalarMultiplier.scala:65:15]
reg [7:0] in_bits_pixel_repeats; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_last; // @[VectorScalarMultiplier.scala:65:15]
reg [127:0] in_bits_tag_data; // @[VectorScalarMultiplier.scala:65:15]
reg [13:0] in_bits_tag_addr; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_0; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_1; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_2; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_3; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_4; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_5; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_6; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_7; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_8; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_9; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_10; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_11; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_12; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_13; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_14; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_mask_15; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_is_acc; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_accumulate; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_has_acc_bitwidth; // @[VectorScalarMultiplier.scala:65:15]
reg [31:0] in_bits_tag_scale; // @[VectorScalarMultiplier.scala:65:15]
reg [15:0] in_bits_tag_repeats; // @[VectorScalarMultiplier.scala:65:15]
reg [15:0] in_bits_tag_pixel_repeats; // @[VectorScalarMultiplier.scala:65:15]
reg [15:0] in_bits_tag_len; // @[VectorScalarMultiplier.scala:65:15]
reg in_bits_tag_last; // @[VectorScalarMultiplier.scala:65:15]
reg [7:0] in_bits_tag_bytes_read; // @[VectorScalarMultiplier.scala:65:15]
reg [7:0] in_bits_tag_cmd_id; // @[VectorScalarMultiplier.scala:65:15]
wire _in_fire_T; // @[Decoupled.scala:51:35]
wire in_fire; // @[VectorScalarMultiplier.scala:66:25]
wire _io_req_ready_T = ~in_valid; // @[VectorScalarMultiplier.scala:65:15, :67:19]
wire _T_1 = in_bits_repeats == 16'h0; // @[VectorScalarMultiplier.scala:65:15, :67:49]
wire _io_req_ready_T_1; // @[VectorScalarMultiplier.scala:67:49]
assign _io_req_ready_T_1 = _T_1; // @[VectorScalarMultiplier.scala:67:49]
wire _pipe_io_in_bits_last_T; // @[VectorScalarMultiplier.scala:92:45]
assign _pipe_io_in_bits_last_T = _T_1; // @[VectorScalarMultiplier.scala:67:49, :92:45]
wire _io_req_ready_T_2 = _io_req_ready_T_1 & in_fire; // @[VectorScalarMultiplier.scala:66:25, :67:{49,57}]
assign _io_req_ready_T_3 = _io_req_ready_T | _io_req_ready_T_2; // @[VectorScalarMultiplier.scala:67:{19,29,57}]
assign io_req_ready_0 = _io_req_ready_T_3; // @[VectorScalarMultiplier.scala:45:7, :67:29]
wire [16:0] _in_bits_repeats_T = {1'h0, in_bits_repeats} - 17'h1; // @[VectorScalarMultiplier.scala:65:15, :76:40]
wire [15:0] _in_bits_repeats_T_1 = _in_bits_repeats_T[15:0]; // @[VectorScalarMultiplier.scala:76:40]
assign _in_fire_T = _pipe_io_in_ready & in_valid; // @[Decoupled.scala:51:35]
assign in_fire = _in_fire_T; // @[Decoupled.scala:51:35]
wire _pipe_io_in_bits_last_T_1 = _pipe_io_in_bits_last_T & in_bits_last; // @[VectorScalarMultiplier.scala:65:15, :92:{45,53}]
wire t_rec_rawIn_sign = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire t_rec_rawIn_sign_1 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire t_rec_rawIn_sign_2 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire t_rec_rawIn_sign_3 = in_bits_scale_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire t_rec_rawIn_sign_0 = t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] t_rec_rawIn_expIn = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] t_rec_rawIn_expIn_1 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] t_rec_rawIn_expIn_2 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] t_rec_rawIn_expIn_3 = in_bits_scale_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] t_rec_rawIn_fractIn = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] t_rec_rawIn_fractIn_1 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] t_rec_rawIn_fractIn_2 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] t_rec_rawIn_fractIn_3 = in_bits_scale_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire t_rec_rawIn_isZeroExpIn = t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire t_rec_rawIn_isZeroFractIn = t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _t_rec_rawIn_normDist_T = t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_1 = t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_2 = t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_3 = t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_4 = t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_5 = t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_6 = t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_7 = t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_8 = t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_9 = t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_10 = t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_11 = t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_12 = t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_13 = t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_14 = t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_15 = t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_16 = t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_17 = t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_18 = t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_19 = t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_20 = t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_21 = t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_22 = t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _t_rec_rawIn_normDist_T_23 = _t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_24 = _t_rec_rawIn_normDist_T_2 ? 5'h14 : _t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_25 = _t_rec_rawIn_normDist_T_3 ? 5'h13 : _t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_26 = _t_rec_rawIn_normDist_T_4 ? 5'h12 : _t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_27 = _t_rec_rawIn_normDist_T_5 ? 5'h11 : _t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_28 = _t_rec_rawIn_normDist_T_6 ? 5'h10 : _t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_29 = _t_rec_rawIn_normDist_T_7 ? 5'hF : _t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_30 = _t_rec_rawIn_normDist_T_8 ? 5'hE : _t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_31 = _t_rec_rawIn_normDist_T_9 ? 5'hD : _t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_32 = _t_rec_rawIn_normDist_T_10 ? 5'hC : _t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_33 = _t_rec_rawIn_normDist_T_11 ? 5'hB : _t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_34 = _t_rec_rawIn_normDist_T_12 ? 5'hA : _t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_35 = _t_rec_rawIn_normDist_T_13 ? 5'h9 : _t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_36 = _t_rec_rawIn_normDist_T_14 ? 5'h8 : _t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_37 = _t_rec_rawIn_normDist_T_15 ? 5'h7 : _t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_38 = _t_rec_rawIn_normDist_T_16 ? 5'h6 : _t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_39 = _t_rec_rawIn_normDist_T_17 ? 5'h5 : _t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_40 = _t_rec_rawIn_normDist_T_18 ? 5'h4 : _t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_41 = _t_rec_rawIn_normDist_T_19 ? 5'h3 : _t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_42 = _t_rec_rawIn_normDist_T_20 ? 5'h2 : _t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_43 = _t_rec_rawIn_normDist_T_21 ? 5'h1 : _t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] t_rec_rawIn_normDist = _t_rec_rawIn_normDist_T_22 ? 5'h0 : _t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _t_rec_rawIn_subnormFract_T = {31'h0, t_rec_rawIn_fractIn} << t_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _t_rec_rawIn_subnormFract_T_1 = _t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] t_rec_rawIn_subnormFract = {_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _t_rec_rawIn_adjustedExp_T = {4'hF, ~t_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _t_rec_rawIn_adjustedExp_T_1 = t_rec_rawIn_isZeroExpIn ? _t_rec_rawIn_adjustedExp_T : {1'h0, t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _t_rec_rawIn_adjustedExp_T_2 = t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _t_rec_rawIn_adjustedExp_T_3 = {6'h20, _t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _t_rec_rawIn_adjustedExp_T_4 = {1'h0, _t_rec_rawIn_adjustedExp_T_1} + {2'h0, _t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] t_rec_rawIn_adjustedExp = _t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _t_rec_rawIn_out_sExp_T = t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire t_rec_rawIn_isZero = t_rec_rawIn_isZeroExpIn & t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire t_rec_rawIn_isZero_0 = t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _t_rec_rawIn_isSpecial_T = t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire t_rec_rawIn_isSpecial = &_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _t_rec_T_2 = t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _t_rec_rawIn_out_isNaN_T = ~t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _t_rec_rawIn_out_isNaN_T_1 = t_rec_rawIn_isSpecial & _t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign t_rec_rawIn_isNaN = _t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _t_rec_rawIn_out_isInf_T = t_rec_rawIn_isSpecial & t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign t_rec_rawIn_isInf = _t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _t_rec_rawIn_out_sExp_T_1 = {1'h0, _t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign t_rec_rawIn_sExp = _t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _t_rec_rawIn_out_sig_T = ~t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _t_rec_rawIn_out_sig_T_1 = {1'h0, _t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _t_rec_rawIn_out_sig_T_2 = t_rec_rawIn_isZeroExpIn ? t_rec_rawIn_subnormFract : t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _t_rec_rawIn_out_sig_T_3 = {_t_rec_rawIn_out_sig_T_1, _t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign t_rec_rawIn_sig = _t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _t_rec_T = t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _t_rec_T_1 = t_rec_rawIn_isZero_0 ? 3'h0 : _t_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _t_rec_T_3 = {_t_rec_T_1[2:1], _t_rec_T_1[0] | _t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _t_rec_T_4 = {t_rec_rawIn_sign_0, _t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _t_rec_T_5 = t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _t_rec_T_6 = {_t_rec_T_4, _t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _t_rec_T_7 = t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] t_rec = {_t_rec_T_6, _t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire self_rec_rawIn_sign = in_bits_in_0_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_sign_0 = self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] self_rec_rawIn_expIn = in_bits_in_0_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] self_rec_rawIn_fractIn = in_bits_in_0_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire self_rec_rawIn_isZeroExpIn = self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn = self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T = self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_1 = self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_2 = self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_3 = self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_4 = self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_5 = self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_6 = self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_7 = self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_8 = self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_9 = self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_10 = self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_11 = self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_12 = self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_13 = self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_14 = self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_15 = self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_16 = self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_17 = self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_18 = self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_19 = self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_20 = self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_21 = self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_22 = self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_23 = _self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_24 = _self_rec_rawIn_normDist_T_2 ? 5'h14 : _self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_25 = _self_rec_rawIn_normDist_T_3 ? 5'h13 : _self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_26 = _self_rec_rawIn_normDist_T_4 ? 5'h12 : _self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_27 = _self_rec_rawIn_normDist_T_5 ? 5'h11 : _self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_28 = _self_rec_rawIn_normDist_T_6 ? 5'h10 : _self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_29 = _self_rec_rawIn_normDist_T_7 ? 5'hF : _self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_30 = _self_rec_rawIn_normDist_T_8 ? 5'hE : _self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_31 = _self_rec_rawIn_normDist_T_9 ? 5'hD : _self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_32 = _self_rec_rawIn_normDist_T_10 ? 5'hC : _self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_33 = _self_rec_rawIn_normDist_T_11 ? 5'hB : _self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_34 = _self_rec_rawIn_normDist_T_12 ? 5'hA : _self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_35 = _self_rec_rawIn_normDist_T_13 ? 5'h9 : _self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_36 = _self_rec_rawIn_normDist_T_14 ? 5'h8 : _self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_37 = _self_rec_rawIn_normDist_T_15 ? 5'h7 : _self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_38 = _self_rec_rawIn_normDist_T_16 ? 5'h6 : _self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_39 = _self_rec_rawIn_normDist_T_17 ? 5'h5 : _self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_40 = _self_rec_rawIn_normDist_T_18 ? 5'h4 : _self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_41 = _self_rec_rawIn_normDist_T_19 ? 5'h3 : _self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_42 = _self_rec_rawIn_normDist_T_20 ? 5'h2 : _self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_43 = _self_rec_rawIn_normDist_T_21 ? 5'h1 : _self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist = _self_rec_rawIn_normDist_T_22 ? 5'h0 : _self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T = {31'h0, self_rec_rawIn_fractIn} << self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_1 = _self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract = {_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T = {4'hF, ~self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_1 = self_rec_rawIn_isZeroExpIn ? _self_rec_rawIn_adjustedExp_T : {1'h0, self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_2 = self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_3 = {6'h20, _self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_4 = {1'h0, _self_rec_rawIn_adjustedExp_T_1} + {2'h0, _self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp = _self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T = self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero = self_rec_rawIn_isZeroExpIn & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_isZero_0 = self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T = self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial = &_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_2 = self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T = ~self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_1 = self_rec_rawIn_isSpecial & _self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_isNaN = _self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T = self_rec_rawIn_isSpecial & self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_isInf = _self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_1 = {1'h0, _self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_sExp = _self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T = ~self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_1 = {1'h0, _self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_2 = self_rec_rawIn_isZeroExpIn ? self_rec_rawIn_subnormFract : self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_3 = {_self_rec_rawIn_out_sig_T_1, _self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_sig = _self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T = self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_1 = self_rec_rawIn_isZero_0 ? 3'h0 : _self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_3 = {_self_rec_T_1[2:1], _self_rec_T_1[0] | _self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_4 = {self_rec_rawIn_sign_0, _self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_5 = self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_6 = {_self_rec_T_4, _self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_7 = self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec = {_self_rec_T_6, _self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _out_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] out_bits; // @[Arithmetic.scala:350:23]
wire [8:0] out_bits_rawIn_exp = _muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _out_bits_rawIn_isZero_T = out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire out_bits_rawIn_isZero = _out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire out_bits_rawIn_isZero_0 = out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _out_bits_rawIn_isSpecial_T = out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire out_bits_rawIn_isSpecial = &_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _out_bits_rawIn_out_isNaN_T = out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _out_bits_rawIn_out_isInf_T = out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _out_bits_rawIn_out_isNaN_T_1 = out_bits_rawIn_isSpecial & _out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign out_bits_rawIn_isNaN = _out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _out_bits_rawIn_out_isInf_T_1 = ~_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _out_bits_rawIn_out_isInf_T_2 = out_bits_rawIn_isSpecial & _out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign out_bits_rawIn_isInf = _out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _out_bits_rawIn_out_sign_T = _muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign out_bits_rawIn_sign = _out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _out_bits_rawIn_out_sExp_T = {1'h0, out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign out_bits_rawIn_sExp = _out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _out_bits_rawIn_out_sig_T = ~out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _out_bits_rawIn_out_sig_T_1 = {1'h0, _out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _out_bits_rawIn_out_sig_T_2 = _muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _out_bits_rawIn_out_sig_T_3 = {_out_bits_rawIn_out_sig_T_1, _out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign out_bits_rawIn_sig = _out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire out_bits_isSubnormal = $signed(out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _out_bits_denormShiftDist_T = out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] out_bits_denormShiftDist = _out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _out_bits_denormFract_T = out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _out_bits_denormFract_T_1 = _out_bits_denormFract_T >> out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] out_bits_denormFract = _out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _out_bits_expOut_T = out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _out_bits_expOut_T_1 = {1'h0, _out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _out_bits_expOut_T_2 = _out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _out_bits_expOut_T_3 = out_bits_isSubnormal ? 8'h0 : _out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _out_bits_expOut_T_4 = out_bits_rawIn_isNaN | out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _out_bits_expOut_T_5 = {8{_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] out_bits_expOut = _out_bits_expOut_T_3 | _out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _out_bits_fractOut_T = out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _out_bits_fractOut_T_1 = out_bits_rawIn_isInf ? 23'h0 : _out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] out_bits_fractOut = out_bits_isSubnormal ? out_bits_denormFract : _out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] out_bits_hi = {out_bits_rawIn_sign, out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _out_bits_T = {out_bits_hi, out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign out_bits = _out_bits_T; // @[fNFromRecFN.scala:66:12]
wire t_rec_rawIn_1_sign = t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire t_rec_rawIn_isZeroExpIn_1 = t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire t_rec_rawIn_isZeroFractIn_1 = t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _t_rec_rawIn_normDist_T_44 = t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_45 = t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_46 = t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_47 = t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_48 = t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_49 = t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_50 = t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_51 = t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_52 = t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_53 = t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_54 = t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_55 = t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_56 = t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_57 = t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_58 = t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_59 = t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_60 = t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_61 = t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_62 = t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_63 = t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_64 = t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_65 = t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_66 = t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _t_rec_rawIn_normDist_T_67 = _t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_68 = _t_rec_rawIn_normDist_T_46 ? 5'h14 : _t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_69 = _t_rec_rawIn_normDist_T_47 ? 5'h13 : _t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_70 = _t_rec_rawIn_normDist_T_48 ? 5'h12 : _t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_71 = _t_rec_rawIn_normDist_T_49 ? 5'h11 : _t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_72 = _t_rec_rawIn_normDist_T_50 ? 5'h10 : _t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_73 = _t_rec_rawIn_normDist_T_51 ? 5'hF : _t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_74 = _t_rec_rawIn_normDist_T_52 ? 5'hE : _t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_75 = _t_rec_rawIn_normDist_T_53 ? 5'hD : _t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_76 = _t_rec_rawIn_normDist_T_54 ? 5'hC : _t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_77 = _t_rec_rawIn_normDist_T_55 ? 5'hB : _t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_78 = _t_rec_rawIn_normDist_T_56 ? 5'hA : _t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_79 = _t_rec_rawIn_normDist_T_57 ? 5'h9 : _t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_80 = _t_rec_rawIn_normDist_T_58 ? 5'h8 : _t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_81 = _t_rec_rawIn_normDist_T_59 ? 5'h7 : _t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_82 = _t_rec_rawIn_normDist_T_60 ? 5'h6 : _t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_83 = _t_rec_rawIn_normDist_T_61 ? 5'h5 : _t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_84 = _t_rec_rawIn_normDist_T_62 ? 5'h4 : _t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_85 = _t_rec_rawIn_normDist_T_63 ? 5'h3 : _t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_86 = _t_rec_rawIn_normDist_T_64 ? 5'h2 : _t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_87 = _t_rec_rawIn_normDist_T_65 ? 5'h1 : _t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] t_rec_rawIn_normDist_1 = _t_rec_rawIn_normDist_T_66 ? 5'h0 : _t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _t_rec_rawIn_subnormFract_T_2 = {31'h0, t_rec_rawIn_fractIn_1} << t_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _t_rec_rawIn_subnormFract_T_3 = _t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] t_rec_rawIn_subnormFract_1 = {_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _t_rec_rawIn_adjustedExp_T_6 = t_rec_rawIn_isZeroExpIn_1 ? _t_rec_rawIn_adjustedExp_T_5 : {1'h0, t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _t_rec_rawIn_adjustedExp_T_7 = t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _t_rec_rawIn_adjustedExp_T_8 = {6'h20, _t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _t_rec_rawIn_adjustedExp_T_9 = {1'h0, _t_rec_rawIn_adjustedExp_T_6} + {2'h0, _t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] t_rec_rawIn_adjustedExp_1 = _t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _t_rec_rawIn_out_sExp_T_2 = t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire t_rec_rawIn_isZero_1 = t_rec_rawIn_isZeroExpIn_1 & t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire t_rec_rawIn_1_isZero = t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _t_rec_rawIn_isSpecial_T_1 = t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire t_rec_rawIn_isSpecial_1 = &_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _t_rec_T_10 = t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _t_rec_rawIn_out_isNaN_T_2 = ~t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _t_rec_rawIn_out_isNaN_T_3 = t_rec_rawIn_isSpecial_1 & _t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign t_rec_rawIn_1_isNaN = _t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _t_rec_rawIn_out_isInf_T_1 = t_rec_rawIn_isSpecial_1 & t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign t_rec_rawIn_1_isInf = _t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _t_rec_rawIn_out_sExp_T_3 = {1'h0, _t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign t_rec_rawIn_1_sExp = _t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _t_rec_rawIn_out_sig_T_4 = ~t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _t_rec_rawIn_out_sig_T_5 = {1'h0, _t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _t_rec_rawIn_out_sig_T_6 = t_rec_rawIn_isZeroExpIn_1 ? t_rec_rawIn_subnormFract_1 : t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _t_rec_rawIn_out_sig_T_7 = {_t_rec_rawIn_out_sig_T_5, _t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign t_rec_rawIn_1_sig = _t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _t_rec_T_8 = t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _t_rec_T_9 = t_rec_rawIn_1_isZero ? 3'h0 : _t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _t_rec_T_11 = {_t_rec_T_9[2:1], _t_rec_T_9[0] | _t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _t_rec_T_12 = {t_rec_rawIn_1_sign, _t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _t_rec_T_13 = t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _t_rec_T_14 = {_t_rec_T_12, _t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _t_rec_T_15 = t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] t_rec_1 = {_t_rec_T_14, _t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire self_rec_rawIn_sign_1 = in_bits_in_1_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_1_sign = self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] self_rec_rawIn_expIn_1 = in_bits_in_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] self_rec_rawIn_fractIn_1 = in_bits_in_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire self_rec_rawIn_isZeroExpIn_1 = self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn_1 = self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T_44 = self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_45 = self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_46 = self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_47 = self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_48 = self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_49 = self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_50 = self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_51 = self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_52 = self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_53 = self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_54 = self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_55 = self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_56 = self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_57 = self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_58 = self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_59 = self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_60 = self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_61 = self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_62 = self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_63 = self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_64 = self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_65 = self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_66 = self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_67 = _self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_68 = _self_rec_rawIn_normDist_T_46 ? 5'h14 : _self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_69 = _self_rec_rawIn_normDist_T_47 ? 5'h13 : _self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_70 = _self_rec_rawIn_normDist_T_48 ? 5'h12 : _self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_71 = _self_rec_rawIn_normDist_T_49 ? 5'h11 : _self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_72 = _self_rec_rawIn_normDist_T_50 ? 5'h10 : _self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_73 = _self_rec_rawIn_normDist_T_51 ? 5'hF : _self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_74 = _self_rec_rawIn_normDist_T_52 ? 5'hE : _self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_75 = _self_rec_rawIn_normDist_T_53 ? 5'hD : _self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_76 = _self_rec_rawIn_normDist_T_54 ? 5'hC : _self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_77 = _self_rec_rawIn_normDist_T_55 ? 5'hB : _self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_78 = _self_rec_rawIn_normDist_T_56 ? 5'hA : _self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_79 = _self_rec_rawIn_normDist_T_57 ? 5'h9 : _self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_80 = _self_rec_rawIn_normDist_T_58 ? 5'h8 : _self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_81 = _self_rec_rawIn_normDist_T_59 ? 5'h7 : _self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_82 = _self_rec_rawIn_normDist_T_60 ? 5'h6 : _self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_83 = _self_rec_rawIn_normDist_T_61 ? 5'h5 : _self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_84 = _self_rec_rawIn_normDist_T_62 ? 5'h4 : _self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_85 = _self_rec_rawIn_normDist_T_63 ? 5'h3 : _self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_86 = _self_rec_rawIn_normDist_T_64 ? 5'h2 : _self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_87 = _self_rec_rawIn_normDist_T_65 ? 5'h1 : _self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist_1 = _self_rec_rawIn_normDist_T_66 ? 5'h0 : _self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T_2 = {31'h0, self_rec_rawIn_fractIn_1} << self_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_3 = _self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract_1 = {_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_6 = self_rec_rawIn_isZeroExpIn_1 ? _self_rec_rawIn_adjustedExp_T_5 : {1'h0, self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_7 = self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_8 = {6'h20, _self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_9 = {1'h0, _self_rec_rawIn_adjustedExp_T_6} + {2'h0, _self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp_1 = _self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T_2 = self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero_1 = self_rec_rawIn_isZeroExpIn_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_1_isZero = self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T_1 = self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial_1 = &_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_10 = self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T_2 = ~self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_3 = self_rec_rawIn_isSpecial_1 & _self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_1_isNaN = _self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T_1 = self_rec_rawIn_isSpecial_1 & self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_1_isInf = _self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_3 = {1'h0, _self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_1_sExp = _self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T_4 = ~self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_5 = {1'h0, _self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_6 = self_rec_rawIn_isZeroExpIn_1 ? self_rec_rawIn_subnormFract_1 : self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_7 = {_self_rec_rawIn_out_sig_T_5, _self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_1_sig = _self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T_8 = self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_9 = self_rec_rawIn_1_isZero ? 3'h0 : _self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_11 = {_self_rec_T_9[2:1], _self_rec_T_9[0] | _self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_12 = {self_rec_rawIn_1_sign, _self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_13 = self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_14 = {_self_rec_T_12, _self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_15 = self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec_1 = {_self_rec_T_14, _self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _out_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire [31:0] out_1_bits; // @[Arithmetic.scala:350:23]
wire [8:0] out_bits_rawIn_exp_1 = _muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _out_bits_rawIn_isZero_T_1 = out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire out_bits_rawIn_isZero_1 = _out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire out_bits_rawIn_1_isZero = out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _out_bits_rawIn_isSpecial_T_1 = out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire out_bits_rawIn_isSpecial_1 = &_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _out_bits_rawIn_out_isNaN_T_2 = out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _out_bits_rawIn_out_isInf_T_3 = out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _out_bits_rawIn_out_isNaN_T_3 = out_bits_rawIn_isSpecial_1 & _out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign out_bits_rawIn_1_isNaN = _out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _out_bits_rawIn_out_isInf_T_4 = ~_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _out_bits_rawIn_out_isInf_T_5 = out_bits_rawIn_isSpecial_1 & _out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign out_bits_rawIn_1_isInf = _out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _out_bits_rawIn_out_sign_T_1 = _muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign out_bits_rawIn_1_sign = _out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _out_bits_rawIn_out_sExp_T_1 = {1'h0, out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign out_bits_rawIn_1_sExp = _out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _out_bits_rawIn_out_sig_T_4 = ~out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _out_bits_rawIn_out_sig_T_5 = {1'h0, _out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _out_bits_rawIn_out_sig_T_6 = _muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _out_bits_rawIn_out_sig_T_7 = {_out_bits_rawIn_out_sig_T_5, _out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign out_bits_rawIn_1_sig = _out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire out_bits_isSubnormal_1 = $signed(out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _out_bits_denormShiftDist_T_2 = out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] out_bits_denormShiftDist_1 = _out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _out_bits_denormFract_T_2 = out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _out_bits_denormFract_T_3 = _out_bits_denormFract_T_2 >> out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] out_bits_denormFract_1 = _out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _out_bits_expOut_T_6 = out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _out_bits_expOut_T_7 = {1'h0, _out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _out_bits_expOut_T_8 = _out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _out_bits_expOut_T_9 = out_bits_isSubnormal_1 ? 8'h0 : _out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _out_bits_expOut_T_10 = out_bits_rawIn_1_isNaN | out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _out_bits_expOut_T_11 = {8{_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] out_bits_expOut_1 = _out_bits_expOut_T_9 | _out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _out_bits_fractOut_T_2 = out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _out_bits_fractOut_T_3 = out_bits_rawIn_1_isInf ? 23'h0 : _out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] out_bits_fractOut_1 = out_bits_isSubnormal_1 ? out_bits_denormFract_1 : _out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] out_bits_hi_1 = {out_bits_rawIn_1_sign, out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
assign _out_bits_T_1 = {out_bits_hi_1, out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
assign out_1_bits = _out_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire t_rec_rawIn_2_sign = t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire t_rec_rawIn_isZeroExpIn_2 = t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire t_rec_rawIn_isZeroFractIn_2 = t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _t_rec_rawIn_normDist_T_88 = t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_89 = t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_90 = t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_91 = t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_92 = t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_93 = t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_94 = t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_95 = t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_96 = t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_97 = t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_98 = t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_99 = t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_100 = t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_101 = t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_102 = t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_103 = t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_104 = t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_105 = t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_106 = t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_107 = t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_108 = t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_109 = t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_110 = t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _t_rec_rawIn_normDist_T_111 = _t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_112 = _t_rec_rawIn_normDist_T_90 ? 5'h14 : _t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_113 = _t_rec_rawIn_normDist_T_91 ? 5'h13 : _t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_114 = _t_rec_rawIn_normDist_T_92 ? 5'h12 : _t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_115 = _t_rec_rawIn_normDist_T_93 ? 5'h11 : _t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_116 = _t_rec_rawIn_normDist_T_94 ? 5'h10 : _t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_117 = _t_rec_rawIn_normDist_T_95 ? 5'hF : _t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_118 = _t_rec_rawIn_normDist_T_96 ? 5'hE : _t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_119 = _t_rec_rawIn_normDist_T_97 ? 5'hD : _t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_120 = _t_rec_rawIn_normDist_T_98 ? 5'hC : _t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_121 = _t_rec_rawIn_normDist_T_99 ? 5'hB : _t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_122 = _t_rec_rawIn_normDist_T_100 ? 5'hA : _t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_123 = _t_rec_rawIn_normDist_T_101 ? 5'h9 : _t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_124 = _t_rec_rawIn_normDist_T_102 ? 5'h8 : _t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_125 = _t_rec_rawIn_normDist_T_103 ? 5'h7 : _t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_126 = _t_rec_rawIn_normDist_T_104 ? 5'h6 : _t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_127 = _t_rec_rawIn_normDist_T_105 ? 5'h5 : _t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_128 = _t_rec_rawIn_normDist_T_106 ? 5'h4 : _t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_129 = _t_rec_rawIn_normDist_T_107 ? 5'h3 : _t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_130 = _t_rec_rawIn_normDist_T_108 ? 5'h2 : _t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_131 = _t_rec_rawIn_normDist_T_109 ? 5'h1 : _t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] t_rec_rawIn_normDist_2 = _t_rec_rawIn_normDist_T_110 ? 5'h0 : _t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _t_rec_rawIn_subnormFract_T_4 = {31'h0, t_rec_rawIn_fractIn_2} << t_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _t_rec_rawIn_subnormFract_T_5 = _t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] t_rec_rawIn_subnormFract_2 = {_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _t_rec_rawIn_adjustedExp_T_11 = t_rec_rawIn_isZeroExpIn_2 ? _t_rec_rawIn_adjustedExp_T_10 : {1'h0, t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _t_rec_rawIn_adjustedExp_T_12 = t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _t_rec_rawIn_adjustedExp_T_13 = {6'h20, _t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _t_rec_rawIn_adjustedExp_T_14 = {1'h0, _t_rec_rawIn_adjustedExp_T_11} + {2'h0, _t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] t_rec_rawIn_adjustedExp_2 = _t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _t_rec_rawIn_out_sExp_T_4 = t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire t_rec_rawIn_isZero_2 = t_rec_rawIn_isZeroExpIn_2 & t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire t_rec_rawIn_2_isZero = t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _t_rec_rawIn_isSpecial_T_2 = t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire t_rec_rawIn_isSpecial_2 = &_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _t_rec_T_18 = t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _t_rec_rawIn_out_isNaN_T_4 = ~t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _t_rec_rawIn_out_isNaN_T_5 = t_rec_rawIn_isSpecial_2 & _t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign t_rec_rawIn_2_isNaN = _t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _t_rec_rawIn_out_isInf_T_2 = t_rec_rawIn_isSpecial_2 & t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign t_rec_rawIn_2_isInf = _t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _t_rec_rawIn_out_sExp_T_5 = {1'h0, _t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign t_rec_rawIn_2_sExp = _t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _t_rec_rawIn_out_sig_T_8 = ~t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _t_rec_rawIn_out_sig_T_9 = {1'h0, _t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _t_rec_rawIn_out_sig_T_10 = t_rec_rawIn_isZeroExpIn_2 ? t_rec_rawIn_subnormFract_2 : t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _t_rec_rawIn_out_sig_T_11 = {_t_rec_rawIn_out_sig_T_9, _t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign t_rec_rawIn_2_sig = _t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _t_rec_T_16 = t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _t_rec_T_17 = t_rec_rawIn_2_isZero ? 3'h0 : _t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _t_rec_T_19 = {_t_rec_T_17[2:1], _t_rec_T_17[0] | _t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _t_rec_T_20 = {t_rec_rawIn_2_sign, _t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _t_rec_T_21 = t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _t_rec_T_22 = {_t_rec_T_20, _t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _t_rec_T_23 = t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] t_rec_2 = {_t_rec_T_22, _t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire self_rec_rawIn_sign_2 = in_bits_in_2_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_2_sign = self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] self_rec_rawIn_expIn_2 = in_bits_in_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] self_rec_rawIn_fractIn_2 = in_bits_in_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire self_rec_rawIn_isZeroExpIn_2 = self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn_2 = self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T_88 = self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_89 = self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_90 = self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_91 = self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_92 = self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_93 = self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_94 = self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_95 = self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_96 = self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_97 = self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_98 = self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_99 = self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_100 = self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_101 = self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_102 = self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_103 = self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_104 = self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_105 = self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_106 = self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_107 = self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_108 = self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_109 = self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_110 = self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_111 = _self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_112 = _self_rec_rawIn_normDist_T_90 ? 5'h14 : _self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_113 = _self_rec_rawIn_normDist_T_91 ? 5'h13 : _self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_114 = _self_rec_rawIn_normDist_T_92 ? 5'h12 : _self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_115 = _self_rec_rawIn_normDist_T_93 ? 5'h11 : _self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_116 = _self_rec_rawIn_normDist_T_94 ? 5'h10 : _self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_117 = _self_rec_rawIn_normDist_T_95 ? 5'hF : _self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_118 = _self_rec_rawIn_normDist_T_96 ? 5'hE : _self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_119 = _self_rec_rawIn_normDist_T_97 ? 5'hD : _self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_120 = _self_rec_rawIn_normDist_T_98 ? 5'hC : _self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_121 = _self_rec_rawIn_normDist_T_99 ? 5'hB : _self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_122 = _self_rec_rawIn_normDist_T_100 ? 5'hA : _self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_123 = _self_rec_rawIn_normDist_T_101 ? 5'h9 : _self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_124 = _self_rec_rawIn_normDist_T_102 ? 5'h8 : _self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_125 = _self_rec_rawIn_normDist_T_103 ? 5'h7 : _self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_126 = _self_rec_rawIn_normDist_T_104 ? 5'h6 : _self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_127 = _self_rec_rawIn_normDist_T_105 ? 5'h5 : _self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_128 = _self_rec_rawIn_normDist_T_106 ? 5'h4 : _self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_129 = _self_rec_rawIn_normDist_T_107 ? 5'h3 : _self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_130 = _self_rec_rawIn_normDist_T_108 ? 5'h2 : _self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_131 = _self_rec_rawIn_normDist_T_109 ? 5'h1 : _self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist_2 = _self_rec_rawIn_normDist_T_110 ? 5'h0 : _self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T_4 = {31'h0, self_rec_rawIn_fractIn_2} << self_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_5 = _self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract_2 = {_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_11 = self_rec_rawIn_isZeroExpIn_2 ? _self_rec_rawIn_adjustedExp_T_10 : {1'h0, self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_12 = self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_13 = {6'h20, _self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_14 = {1'h0, _self_rec_rawIn_adjustedExp_T_11} + {2'h0, _self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp_2 = _self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T_4 = self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero_2 = self_rec_rawIn_isZeroExpIn_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_2_isZero = self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T_2 = self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial_2 = &_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_18 = self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T_4 = ~self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_5 = self_rec_rawIn_isSpecial_2 & _self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_2_isNaN = _self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T_2 = self_rec_rawIn_isSpecial_2 & self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_2_isInf = _self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_5 = {1'h0, _self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_2_sExp = _self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T_8 = ~self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_9 = {1'h0, _self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_10 = self_rec_rawIn_isZeroExpIn_2 ? self_rec_rawIn_subnormFract_2 : self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_11 = {_self_rec_rawIn_out_sig_T_9, _self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_2_sig = _self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T_16 = self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_17 = self_rec_rawIn_2_isZero ? 3'h0 : _self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_19 = {_self_rec_T_17[2:1], _self_rec_T_17[0] | _self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_20 = {self_rec_rawIn_2_sign, _self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_21 = self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_22 = {_self_rec_T_20, _self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_23 = self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec_2 = {_self_rec_T_22, _self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _out_bits_T_2; // @[fNFromRecFN.scala:66:12]
wire [31:0] out_2_bits; // @[Arithmetic.scala:350:23]
wire [8:0] out_bits_rawIn_exp_2 = _muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _out_bits_rawIn_isZero_T_2 = out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire out_bits_rawIn_isZero_2 = _out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire out_bits_rawIn_2_isZero = out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _out_bits_rawIn_isSpecial_T_2 = out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire out_bits_rawIn_isSpecial_2 = &_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _out_bits_rawIn_out_isNaN_T_4 = out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _out_bits_rawIn_out_isInf_T_6 = out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _out_bits_rawIn_out_isNaN_T_5 = out_bits_rawIn_isSpecial_2 & _out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign out_bits_rawIn_2_isNaN = _out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _out_bits_rawIn_out_isInf_T_7 = ~_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _out_bits_rawIn_out_isInf_T_8 = out_bits_rawIn_isSpecial_2 & _out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign out_bits_rawIn_2_isInf = _out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _out_bits_rawIn_out_sign_T_2 = _muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign out_bits_rawIn_2_sign = _out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _out_bits_rawIn_out_sExp_T_2 = {1'h0, out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign out_bits_rawIn_2_sExp = _out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _out_bits_rawIn_out_sig_T_8 = ~out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _out_bits_rawIn_out_sig_T_9 = {1'h0, _out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _out_bits_rawIn_out_sig_T_10 = _muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _out_bits_rawIn_out_sig_T_11 = {_out_bits_rawIn_out_sig_T_9, _out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign out_bits_rawIn_2_sig = _out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire out_bits_isSubnormal_2 = $signed(out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _out_bits_denormShiftDist_T_4 = out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] out_bits_denormShiftDist_2 = _out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _out_bits_denormFract_T_4 = out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _out_bits_denormFract_T_5 = _out_bits_denormFract_T_4 >> out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] out_bits_denormFract_2 = _out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _out_bits_expOut_T_12 = out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _out_bits_expOut_T_13 = {1'h0, _out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _out_bits_expOut_T_14 = _out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _out_bits_expOut_T_15 = out_bits_isSubnormal_2 ? 8'h0 : _out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _out_bits_expOut_T_16 = out_bits_rawIn_2_isNaN | out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _out_bits_expOut_T_17 = {8{_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] out_bits_expOut_2 = _out_bits_expOut_T_15 | _out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _out_bits_fractOut_T_4 = out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _out_bits_fractOut_T_5 = out_bits_rawIn_2_isInf ? 23'h0 : _out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] out_bits_fractOut_2 = out_bits_isSubnormal_2 ? out_bits_denormFract_2 : _out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] out_bits_hi_2 = {out_bits_rawIn_2_sign, out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
assign _out_bits_T_2 = {out_bits_hi_2, out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
assign out_2_bits = _out_bits_T_2; // @[fNFromRecFN.scala:66:12]
wire t_rec_rawIn_3_sign = t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19]
wire t_rec_rawIn_isZeroExpIn_3 = t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire t_rec_rawIn_isZeroFractIn_3 = t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _t_rec_rawIn_normDist_T_132 = t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_133 = t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_134 = t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_135 = t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_136 = t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_137 = t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_138 = t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_139 = t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_140 = t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_141 = t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_142 = t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_143 = t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_144 = t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_145 = t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_146 = t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_147 = t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_148 = t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_149 = t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_150 = t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_151 = t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_152 = t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_153 = t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21]
wire _t_rec_rawIn_normDist_T_154 = t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _t_rec_rawIn_normDist_T_155 = _t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_156 = _t_rec_rawIn_normDist_T_134 ? 5'h14 : _t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_157 = _t_rec_rawIn_normDist_T_135 ? 5'h13 : _t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_158 = _t_rec_rawIn_normDist_T_136 ? 5'h12 : _t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_159 = _t_rec_rawIn_normDist_T_137 ? 5'h11 : _t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_160 = _t_rec_rawIn_normDist_T_138 ? 5'h10 : _t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_161 = _t_rec_rawIn_normDist_T_139 ? 5'hF : _t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_162 = _t_rec_rawIn_normDist_T_140 ? 5'hE : _t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_163 = _t_rec_rawIn_normDist_T_141 ? 5'hD : _t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_164 = _t_rec_rawIn_normDist_T_142 ? 5'hC : _t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_165 = _t_rec_rawIn_normDist_T_143 ? 5'hB : _t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_166 = _t_rec_rawIn_normDist_T_144 ? 5'hA : _t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_167 = _t_rec_rawIn_normDist_T_145 ? 5'h9 : _t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_168 = _t_rec_rawIn_normDist_T_146 ? 5'h8 : _t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_169 = _t_rec_rawIn_normDist_T_147 ? 5'h7 : _t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_170 = _t_rec_rawIn_normDist_T_148 ? 5'h6 : _t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_171 = _t_rec_rawIn_normDist_T_149 ? 5'h5 : _t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_172 = _t_rec_rawIn_normDist_T_150 ? 5'h4 : _t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_173 = _t_rec_rawIn_normDist_T_151 ? 5'h3 : _t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_174 = _t_rec_rawIn_normDist_T_152 ? 5'h2 : _t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70]
wire [4:0] _t_rec_rawIn_normDist_T_175 = _t_rec_rawIn_normDist_T_153 ? 5'h1 : _t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70]
wire [4:0] t_rec_rawIn_normDist_3 = _t_rec_rawIn_normDist_T_154 ? 5'h0 : _t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70]
wire [53:0] _t_rec_rawIn_subnormFract_T_6 = {31'h0, t_rec_rawIn_fractIn_3} << t_rec_rawIn_normDist_3; // @[Mux.scala:50:70]
wire [21:0] _t_rec_rawIn_subnormFract_T_7 = _t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] t_rec_rawIn_subnormFract_3 = {_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70]
wire [8:0] _t_rec_rawIn_adjustedExp_T_16 = t_rec_rawIn_isZeroExpIn_3 ? _t_rec_rawIn_adjustedExp_T_15 : {1'h0, t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _t_rec_rawIn_adjustedExp_T_17 = t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _t_rec_rawIn_adjustedExp_T_18 = {6'h20, _t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _t_rec_rawIn_adjustedExp_T_19 = {1'h0, _t_rec_rawIn_adjustedExp_T_16} + {2'h0, _t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] t_rec_rawIn_adjustedExp_3 = _t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _t_rec_rawIn_out_sExp_T_6 = t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28]
wire t_rec_rawIn_isZero_3 = t_rec_rawIn_isZeroExpIn_3 & t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire t_rec_rawIn_3_isZero = t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _t_rec_rawIn_isSpecial_T_3 = t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire t_rec_rawIn_isSpecial_3 = &_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}]
wire _t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28]
wire _t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28]
wire _t_rec_T_26 = t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27]
wire t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19]
wire _t_rec_rawIn_out_isNaN_T_6 = ~t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _t_rec_rawIn_out_isNaN_T_7 = t_rec_rawIn_isSpecial_3 & _t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign t_rec_rawIn_3_isNaN = _t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _t_rec_rawIn_out_isInf_T_3 = t_rec_rawIn_isSpecial_3 & t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign t_rec_rawIn_3_isInf = _t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _t_rec_rawIn_out_sExp_T_7 = {1'h0, _t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}]
assign t_rec_rawIn_3_sExp = _t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _t_rec_rawIn_out_sig_T_12 = ~t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _t_rec_rawIn_out_sig_T_13 = {1'h0, _t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _t_rec_rawIn_out_sig_T_14 = t_rec_rawIn_isZeroExpIn_3 ? t_rec_rawIn_subnormFract_3 : t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _t_rec_rawIn_out_sig_T_15 = {_t_rec_rawIn_out_sig_T_13, _t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign t_rec_rawIn_3_sig = _t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _t_rec_T_24 = t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _t_rec_T_25 = t_rec_rawIn_3_isZero ? 3'h0 : _t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _t_rec_T_27 = {_t_rec_T_25[2:1], _t_rec_T_25[0] | _t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _t_rec_T_28 = {t_rec_rawIn_3_sign, _t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _t_rec_T_29 = t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _t_rec_T_30 = {_t_rec_T_28, _t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _t_rec_T_31 = t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] t_rec_3 = {_t_rec_T_30, _t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire self_rec_rawIn_sign_3 = in_bits_in_3_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire self_rec_rawIn_3_sign = self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] self_rec_rawIn_expIn_3 = in_bits_in_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] self_rec_rawIn_fractIn_3 = in_bits_in_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire self_rec_rawIn_isZeroExpIn_3 = self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire self_rec_rawIn_isZeroFractIn_3 = self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _self_rec_rawIn_normDist_T_132 = self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_133 = self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_134 = self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_135 = self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_136 = self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_137 = self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_138 = self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_139 = self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_140 = self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_141 = self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_142 = self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_143 = self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_144 = self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_145 = self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_146 = self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_147 = self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_148 = self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_149 = self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_150 = self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_151 = self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_152 = self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_153 = self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21]
wire _self_rec_rawIn_normDist_T_154 = self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _self_rec_rawIn_normDist_T_155 = _self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_156 = _self_rec_rawIn_normDist_T_134 ? 5'h14 : _self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_157 = _self_rec_rawIn_normDist_T_135 ? 5'h13 : _self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_158 = _self_rec_rawIn_normDist_T_136 ? 5'h12 : _self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_159 = _self_rec_rawIn_normDist_T_137 ? 5'h11 : _self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_160 = _self_rec_rawIn_normDist_T_138 ? 5'h10 : _self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_161 = _self_rec_rawIn_normDist_T_139 ? 5'hF : _self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_162 = _self_rec_rawIn_normDist_T_140 ? 5'hE : _self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_163 = _self_rec_rawIn_normDist_T_141 ? 5'hD : _self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_164 = _self_rec_rawIn_normDist_T_142 ? 5'hC : _self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_165 = _self_rec_rawIn_normDist_T_143 ? 5'hB : _self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_166 = _self_rec_rawIn_normDist_T_144 ? 5'hA : _self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_167 = _self_rec_rawIn_normDist_T_145 ? 5'h9 : _self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_168 = _self_rec_rawIn_normDist_T_146 ? 5'h8 : _self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_169 = _self_rec_rawIn_normDist_T_147 ? 5'h7 : _self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_170 = _self_rec_rawIn_normDist_T_148 ? 5'h6 : _self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_171 = _self_rec_rawIn_normDist_T_149 ? 5'h5 : _self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_172 = _self_rec_rawIn_normDist_T_150 ? 5'h4 : _self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_173 = _self_rec_rawIn_normDist_T_151 ? 5'h3 : _self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_174 = _self_rec_rawIn_normDist_T_152 ? 5'h2 : _self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70]
wire [4:0] _self_rec_rawIn_normDist_T_175 = _self_rec_rawIn_normDist_T_153 ? 5'h1 : _self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70]
wire [4:0] self_rec_rawIn_normDist_3 = _self_rec_rawIn_normDist_T_154 ? 5'h0 : _self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70]
wire [53:0] _self_rec_rawIn_subnormFract_T_6 = {31'h0, self_rec_rawIn_fractIn_3} << self_rec_rawIn_normDist_3; // @[Mux.scala:50:70]
wire [21:0] _self_rec_rawIn_subnormFract_T_7 = _self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] self_rec_rawIn_subnormFract_3 = {_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70]
wire [8:0] _self_rec_rawIn_adjustedExp_T_16 = self_rec_rawIn_isZeroExpIn_3 ? _self_rec_rawIn_adjustedExp_T_15 : {1'h0, self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _self_rec_rawIn_adjustedExp_T_17 = self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _self_rec_rawIn_adjustedExp_T_18 = {6'h20, _self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _self_rec_rawIn_adjustedExp_T_19 = {1'h0, _self_rec_rawIn_adjustedExp_T_16} + {2'h0, _self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] self_rec_rawIn_adjustedExp_3 = _self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _self_rec_rawIn_out_sExp_T_6 = self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28]
wire self_rec_rawIn_isZero_3 = self_rec_rawIn_isZeroExpIn_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire self_rec_rawIn_3_isZero = self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _self_rec_rawIn_isSpecial_T_3 = self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire self_rec_rawIn_isSpecial_3 = &_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}]
wire _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28]
wire _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28]
wire _self_rec_T_26 = self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27]
wire self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19]
wire _self_rec_rawIn_out_isNaN_T_6 = ~self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _self_rec_rawIn_out_isNaN_T_7 = self_rec_rawIn_isSpecial_3 & _self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign self_rec_rawIn_3_isNaN = _self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _self_rec_rawIn_out_isInf_T_3 = self_rec_rawIn_isSpecial_3 & self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign self_rec_rawIn_3_isInf = _self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _self_rec_rawIn_out_sExp_T_7 = {1'h0, _self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}]
assign self_rec_rawIn_3_sExp = _self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _self_rec_rawIn_out_sig_T_12 = ~self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _self_rec_rawIn_out_sig_T_13 = {1'h0, _self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _self_rec_rawIn_out_sig_T_14 = self_rec_rawIn_isZeroExpIn_3 ? self_rec_rawIn_subnormFract_3 : self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _self_rec_rawIn_out_sig_T_15 = {_self_rec_rawIn_out_sig_T_13, _self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign self_rec_rawIn_3_sig = _self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _self_rec_T_24 = self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _self_rec_T_25 = self_rec_rawIn_3_isZero ? 3'h0 : _self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _self_rec_T_27 = {_self_rec_T_25[2:1], _self_rec_T_25[0] | _self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _self_rec_T_28 = {self_rec_rawIn_3_sign, _self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _self_rec_T_29 = self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _self_rec_T_30 = {_self_rec_T_28, _self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _self_rec_T_31 = self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] self_rec_3 = {_self_rec_T_30, _self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _out_bits_T_3; // @[fNFromRecFN.scala:66:12]
wire [31:0] out_3_bits; // @[Arithmetic.scala:350:23]
wire [8:0] out_bits_rawIn_exp_3 = _muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _out_bits_rawIn_isZero_T_3 = out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire out_bits_rawIn_isZero_3 = _out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire out_bits_rawIn_3_isZero = out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _out_bits_rawIn_isSpecial_T_3 = out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire out_bits_rawIn_isSpecial_3 = &_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33]
wire _out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33]
wire _out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44]
wire out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _out_bits_rawIn_out_isNaN_T_6 = out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _out_bits_rawIn_out_isInf_T_9 = out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _out_bits_rawIn_out_isNaN_T_7 = out_bits_rawIn_isSpecial_3 & _out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign out_bits_rawIn_3_isNaN = _out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _out_bits_rawIn_out_isInf_T_10 = ~_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _out_bits_rawIn_out_isInf_T_11 = out_bits_rawIn_isSpecial_3 & _out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign out_bits_rawIn_3_isInf = _out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _out_bits_rawIn_out_sign_T_3 = _muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign out_bits_rawIn_3_sign = _out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _out_bits_rawIn_out_sExp_T_3 = {1'h0, out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign out_bits_rawIn_3_sExp = _out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _out_bits_rawIn_out_sig_T_12 = ~out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _out_bits_rawIn_out_sig_T_13 = {1'h0, _out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _out_bits_rawIn_out_sig_T_14 = _muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _out_bits_rawIn_out_sig_T_15 = {_out_bits_rawIn_out_sig_T_13, _out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign out_bits_rawIn_3_sig = _out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire out_bits_isSubnormal_3 = $signed(out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _out_bits_denormShiftDist_T_6 = out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] out_bits_denormShiftDist_3 = _out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _out_bits_denormFract_T_6 = out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _out_bits_denormFract_T_7 = _out_bits_denormFract_T_6 >> out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] out_bits_denormFract_3 = _out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _out_bits_expOut_T_18 = out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _out_bits_expOut_T_19 = {1'h0, _out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _out_bits_expOut_T_20 = _out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _out_bits_expOut_T_21 = out_bits_isSubnormal_3 ? 8'h0 : _out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _out_bits_expOut_T_22 = out_bits_rawIn_3_isNaN | out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _out_bits_expOut_T_23 = {8{_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] out_bits_expOut_3 = _out_bits_expOut_T_21 | _out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _out_bits_fractOut_T_6 = out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _out_bits_fractOut_T_7 = out_bits_rawIn_3_isInf ? 23'h0 : _out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] out_bits_fractOut_3 = out_bits_isSubnormal_3 ? out_bits_denormFract_3 : _out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] out_bits_hi_3 = {out_bits_rawIn_3_sign, out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23]
assign _out_bits_T_3 = {out_bits_hi_3, out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12]
assign out_3_bits = _out_bits_T_3; // @[fNFromRecFN.scala:66:12]
wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[VectorScalarMultiplier.scala:45:7]
if (reset) // @[VectorScalarMultiplier.scala:45:7]
in_valid <= 1'h0; // @[VectorScalarMultiplier.scala:65:15]
else // @[VectorScalarMultiplier.scala:45:7]
in_valid <= _T ? io_req_valid_0 : ~(in_fire & _T_1) & in_valid; // @[Decoupled.scala:51:35]
if (_T) begin // @[Decoupled.scala:51:35]
in_bits_in_0_bits <= io_req_bits_in_0_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_in_1_bits <= io_req_bits_in_1_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_in_2_bits <= io_req_bits_in_2_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_in_3_bits <= io_req_bits_in_3_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_scale_bits <= io_req_bits_scale_bits_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_repeats <= io_req_bits_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_last <= io_req_bits_last_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_data <= io_req_bits_tag_data_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_addr <= io_req_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_0 <= io_req_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_1 <= io_req_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_2 <= io_req_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_3 <= io_req_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_4 <= io_req_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_5 <= io_req_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_6 <= io_req_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_7 <= io_req_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_8 <= io_req_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_9 <= io_req_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_10 <= io_req_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_11 <= io_req_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_12 <= io_req_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_13 <= io_req_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_14 <= io_req_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_mask_15 <= io_req_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_is_acc <= io_req_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_accumulate <= io_req_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_has_acc_bitwidth <= io_req_bits_tag_has_acc_bitwidth_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_scale <= io_req_bits_tag_scale_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_repeats <= io_req_bits_tag_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_pixel_repeats <= io_req_bits_tag_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_len <= io_req_bits_tag_len_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_last <= io_req_bits_tag_last_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_bytes_read <= io_req_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
in_bits_tag_cmd_id <= io_req_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7, :65:15]
end
else if (in_fire) // @[VectorScalarMultiplier.scala:66:25]
in_bits_repeats <= _in_bits_repeats_T_1; // @[VectorScalarMultiplier.scala:65:15, :76:40]
always @(posedge)
Pipeline pipe ( // @[VectorScalarMultiplier.scala:83:22]
.clock (clock),
.reset (reset),
.io_in_ready (_pipe_io_in_ready),
.io_in_valid (in_valid), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_out_0_bits (out_bits), // @[Arithmetic.scala:350:23]
.io_in_bits_out_1_bits (out_1_bits), // @[Arithmetic.scala:350:23]
.io_in_bits_out_2_bits (out_2_bits), // @[Arithmetic.scala:350:23]
.io_in_bits_out_3_bits (out_3_bits), // @[Arithmetic.scala:350:23]
.io_in_bits_row (in_bits_repeats), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_last (_pipe_io_in_bits_last_T_1), // @[VectorScalarMultiplier.scala:92:53]
.io_in_bits_tag_data (in_bits_tag_data), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_addr (in_bits_tag_addr), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_0 (in_bits_tag_mask_0), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_1 (in_bits_tag_mask_1), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_2 (in_bits_tag_mask_2), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_3 (in_bits_tag_mask_3), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_4 (in_bits_tag_mask_4), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_5 (in_bits_tag_mask_5), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_6 (in_bits_tag_mask_6), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_7 (in_bits_tag_mask_7), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_8 (in_bits_tag_mask_8), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_9 (in_bits_tag_mask_9), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_10 (in_bits_tag_mask_10), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_11 (in_bits_tag_mask_11), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_12 (in_bits_tag_mask_12), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_13 (in_bits_tag_mask_13), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_14 (in_bits_tag_mask_14), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_mask_15 (in_bits_tag_mask_15), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_is_acc (in_bits_tag_is_acc), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_accumulate (in_bits_tag_accumulate), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_has_acc_bitwidth (in_bits_tag_has_acc_bitwidth), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_scale (in_bits_tag_scale), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_repeats (in_bits_tag_repeats), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_pixel_repeats (in_bits_tag_pixel_repeats), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_len (in_bits_tag_len), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_last (in_bits_tag_last), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_bytes_read (in_bits_tag_bytes_read), // @[VectorScalarMultiplier.scala:65:15]
.io_in_bits_tag_cmd_id (in_bits_tag_cmd_id), // @[VectorScalarMultiplier.scala:65:15]
.io_out_ready (io_resp_ready_0), // @[VectorScalarMultiplier.scala:45:7]
.io_out_valid (io_resp_valid_0),
.io_out_bits_out_0_bits (io_resp_bits_out_0_bits_0),
.io_out_bits_out_1_bits (io_resp_bits_out_1_bits_0),
.io_out_bits_out_2_bits (io_resp_bits_out_2_bits_0),
.io_out_bits_out_3_bits (io_resp_bits_out_3_bits_0),
.io_out_bits_row (io_resp_bits_row_0),
.io_out_bits_last (io_resp_bits_last_0),
.io_out_bits_tag_data (io_resp_bits_tag_data_0),
.io_out_bits_tag_addr (io_resp_bits_tag_addr_0),
.io_out_bits_tag_mask_0 (io_resp_bits_tag_mask_0_0),
.io_out_bits_tag_mask_1 (io_resp_bits_tag_mask_1_0),
.io_out_bits_tag_mask_2 (io_resp_bits_tag_mask_2_0),
.io_out_bits_tag_mask_3 (io_resp_bits_tag_mask_3_0),
.io_out_bits_tag_mask_4 (io_resp_bits_tag_mask_4_0),
.io_out_bits_tag_mask_5 (io_resp_bits_tag_mask_5_0),
.io_out_bits_tag_mask_6 (io_resp_bits_tag_mask_6_0),
.io_out_bits_tag_mask_7 (io_resp_bits_tag_mask_7_0),
.io_out_bits_tag_mask_8 (io_resp_bits_tag_mask_8_0),
.io_out_bits_tag_mask_9 (io_resp_bits_tag_mask_9_0),
.io_out_bits_tag_mask_10 (io_resp_bits_tag_mask_10_0),
.io_out_bits_tag_mask_11 (io_resp_bits_tag_mask_11_0),
.io_out_bits_tag_mask_12 (io_resp_bits_tag_mask_12_0),
.io_out_bits_tag_mask_13 (io_resp_bits_tag_mask_13_0),
.io_out_bits_tag_mask_14 (io_resp_bits_tag_mask_14_0),
.io_out_bits_tag_mask_15 (io_resp_bits_tag_mask_15_0),
.io_out_bits_tag_is_acc (io_resp_bits_tag_is_acc_0),
.io_out_bits_tag_accumulate (io_resp_bits_tag_accumulate_0),
.io_out_bits_tag_has_acc_bitwidth (io_resp_bits_tag_has_acc_bitwidth_0),
.io_out_bits_tag_scale (io_resp_bits_tag_scale_0),
.io_out_bits_tag_repeats (io_resp_bits_tag_repeats_0),
.io_out_bits_tag_pixel_repeats (io_resp_bits_tag_pixel_repeats_0),
.io_out_bits_tag_len (io_resp_bits_tag_len_0),
.io_out_bits_tag_last (io_resp_bits_tag_last_0),
.io_out_bits_tag_bytes_read (io_resp_bits_tag_bytes_read_0),
.io_out_bits_tag_cmd_id (io_resp_bits_tag_cmd_id_0)
); // @[VectorScalarMultiplier.scala:83:22]
RecFNToRecFN_4 t_resizer ( // @[Arithmetic.scala:336:32]
.io_in (t_rec), // @[recFNFromFN.scala:50:41]
.io_out (_t_resizer_io_out)
); // @[Arithmetic.scala:336:32]
MulRecFN muladder ( // @[Arithmetic.scala:342:30]
.io_a (self_rec), // @[recFNFromFN.scala:50:41]
.io_b (_t_resizer_io_out), // @[Arithmetic.scala:336:32]
.io_out (_muladder_io_out)
); // @[Arithmetic.scala:342:30]
RecFNToRecFN_5 t_resizer_1 ( // @[Arithmetic.scala:336:32]
.io_in (t_rec_1), // @[recFNFromFN.scala:50:41]
.io_out (_t_resizer_1_io_out)
); // @[Arithmetic.scala:336:32]
MulRecFN_1 muladder_1 ( // @[Arithmetic.scala:342:30]
.io_a (self_rec_1), // @[recFNFromFN.scala:50:41]
.io_b (_t_resizer_1_io_out), // @[Arithmetic.scala:336:32]
.io_out (_muladder_1_io_out)
); // @[Arithmetic.scala:342:30]
RecFNToRecFN_6 t_resizer_2 ( // @[Arithmetic.scala:336:32]
.io_in (t_rec_2), // @[recFNFromFN.scala:50:41]
.io_out (_t_resizer_2_io_out)
); // @[Arithmetic.scala:336:32]
MulRecFN_2 muladder_2 ( // @[Arithmetic.scala:342:30]
.io_a (self_rec_2), // @[recFNFromFN.scala:50:41]
.io_b (_t_resizer_2_io_out), // @[Arithmetic.scala:336:32]
.io_out (_muladder_2_io_out)
); // @[Arithmetic.scala:342:30]
RecFNToRecFN_7 t_resizer_3 ( // @[Arithmetic.scala:336:32]
.io_in (t_rec_3), // @[recFNFromFN.scala:50:41]
.io_out (_t_resizer_3_io_out)
); // @[Arithmetic.scala:336:32]
MulRecFN_3 muladder_3 ( // @[Arithmetic.scala:342:30]
.io_a (self_rec_3), // @[recFNFromFN.scala:50:41]
.io_b (_t_resizer_3_io_out), // @[Arithmetic.scala:336:32]
.io_out (_muladder_3_io_out)
); // @[Arithmetic.scala:342:30]
assign io_req_ready = io_req_ready_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_valid = io_resp_valid_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_out_0_bits = io_resp_bits_out_0_bits_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_out_1_bits = io_resp_bits_out_1_bits_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_out_2_bits = io_resp_bits_out_2_bits_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_out_3_bits = io_resp_bits_out_3_bits_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_row = io_resp_bits_row_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_last = io_resp_bits_last_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_data = io_resp_bits_tag_data_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_addr = io_resp_bits_tag_addr_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_0 = io_resp_bits_tag_mask_0_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_1 = io_resp_bits_tag_mask_1_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_2 = io_resp_bits_tag_mask_2_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_3 = io_resp_bits_tag_mask_3_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_4 = io_resp_bits_tag_mask_4_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_5 = io_resp_bits_tag_mask_5_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_6 = io_resp_bits_tag_mask_6_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_7 = io_resp_bits_tag_mask_7_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_8 = io_resp_bits_tag_mask_8_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_9 = io_resp_bits_tag_mask_9_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_10 = io_resp_bits_tag_mask_10_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_11 = io_resp_bits_tag_mask_11_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_12 = io_resp_bits_tag_mask_12_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_13 = io_resp_bits_tag_mask_13_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_14 = io_resp_bits_tag_mask_14_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_mask_15 = io_resp_bits_tag_mask_15_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_is_acc = io_resp_bits_tag_is_acc_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_accumulate = io_resp_bits_tag_accumulate_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_has_acc_bitwidth = io_resp_bits_tag_has_acc_bitwidth_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_scale = io_resp_bits_tag_scale_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_repeats = io_resp_bits_tag_repeats_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_pixel_repeats = io_resp_bits_tag_pixel_repeats_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_len = io_resp_bits_tag_len_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_last = io_resp_bits_tag_last_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_bytes_read = io_resp_bits_tag_bytes_read_0; // @[VectorScalarMultiplier.scala:45:7]
assign io_resp_bits_tag_cmd_id = io_resp_bits_tag_cmd_id_0; // @[VectorScalarMultiplier.scala:45:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_260( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_27( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16]
output [16:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire rawIn_isNaN = (&(io_in[31:30])) & io_in[29]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
RoundAnyRawFNToRecFN_ie8_is24_oe5_os11 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (rawIn_isNaN & ~(io_in[22])), // @[rawFloatFromRecFN.scala:56:33]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:56:33]
.io_in_isInf ((&(io_in[31:30])) & ~(io_in[29])), // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
.io_in_isZero (~(|(io_in[31:29]))), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
.io_in_sign (io_in[32]), // @[rawFloatFromRecFN.scala:59:25]
.io_in_sExp ({1'h0, io_in[31:23]}), // @[rawFloatFromRecFN.scala:51:21, :60:27]
.io_in_sig ({1'h0, |(io_in[31:29]), io_in[22:0]}), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}]
.io_roundingMode (io_roundingMode),
.io_out (io_out)
); // @[RecFNToRecFN.scala:72:19]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Breakpoint.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._
class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val ttype = UInt(4.W)
val dmode = Bool()
val maskmax = UInt(6.W)
val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)
val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)
val chain = Bool()
val zero = UInt(2.W)
val tmatch = UInt(2.W)
val m = Bool()
val h = Bool()
val s = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
def tType = 2
def maskMax = 4
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}
class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34
def mselectPos: Int = if (xLen == 32) 25 else 50
def mvaluePos : Int = mselectPos + 1
def sselectPos: Int = 0
def svaluePos : Int = 2
val mvalue = UInt(mvalueBits.W)
val mselect = Bool()
val pad2 = UInt((mselectPos - svalueBits - 2).W)
val svalue = UInt(svalueBits.W)
val pad1 = UInt(1.W)
val sselect = Bool()
}
class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
val address = UInt(vaddrBits.W)
val textra = new TExtra
def contextMatch(mcontext: UInt, scontext: UInt) =
(if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)
def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
def pow2AddressMatch(x: UInt) =
(~x | mask()) === (~address | mask())
def rangeAddressMatch(x: UInt) =
(x >= address) ^ control.tmatch(0)
def addressMatch(x: UInt) =
Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
}
class BPWatch (val n: Int) extends Bundle() {
val valid = Vec(n, Bool())
val rvalid = Vec(n, Bool())
val wvalid = Vec(n, Bool())
val ivalid = Vec(n, Bool())
val action = UInt(3.W)
}
class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val status = Input(new MStatus())
val bp = Input(Vec(n, new BP))
val pc = Input(UInt(vaddrBits.W))
val ea = Input(UInt(vaddrBits.W))
val mcontext = Input(UInt(coreParams.mcontextWidth.W))
val scontext = Input(UInt(coreParams.scontextWidth.W))
val xcpt_if = Output(Bool())
val xcpt_ld = Output(Bool())
val xcpt_st = Output(Bool())
val debug_if = Output(Bool())
val debug_ld = Output(Bool())
val debug_st = Output(Bool())
val bpwatch = Output(Vec(n, new BPWatch(1)))
})
io.xcpt_if := false.B
io.xcpt_ld := false.B
io.xcpt_st := false.B
io.debug_if := false.B
io.debug_ld := false.B
io.debug_st := false.B
(io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) =>
val en = bp.control.enabled(io.status)
val cx = bp.contextMatch(io.mcontext, io.scontext)
val r = en && bp.control.r && bp.addressMatch(io.ea) && cx
val w = en && bp.control.w && bp.addressMatch(io.ea) && cx
val x = en && bp.control.x && bp.addressMatch(io.pc) && cx
val end = !bp.control.chain
val action = bp.control.action
bpw.action := action
bpw.valid(0) := false.B
bpw.rvalid(0) := false.B
bpw.wvalid(0) := false.B
bpw.ivalid(0) := false.B
when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }
when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }
(end || r, end || w, end || x)
}
}
| module BreakpointUnit_18( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_60( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_73 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_16( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = io_in_bits_egress_id == 5'h9; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_13, 3'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hB : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hC : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_13}; // @[IngressUnit.scala:30:72, :45:50]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h8; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h8; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module rockettile_icache_data_arrays_1_5( // @[DescribedSRAM.scala:17:26]
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [255:0] RW0_wdata,
output [255:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_41( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [2:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [7:0] b_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg [2:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [7:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [2:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [4:0] inflight; // @[Monitor.scala:614:27]
reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [4:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [7:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [15:0] inflight_2; // @[Monitor.scala:828:27]
reg [7:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [15:0] _GEN_9 = {12'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [15:0] d_set = _GEN_8 ? 16'h1 << _GEN_9 : 16'h0; // @[OneHot.scala:58:35]
wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35]
wire [15:0] _GEN_11 = {12'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_29( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [13:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [13:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [8207:0] inflight; // @[Monitor.scala:614:27]
reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [16383:0] _GEN = {16370'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [16383:0] _GEN_2 = {16370'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [8207:0] inflight_1; // @[Monitor.scala:726:35]
reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File Plic.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}
import scala.math.min
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq
class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val complete = Input(Bool())
}
class LevelGateway extends Module {
val io = IO(new Bundle {
val interrupt = Input(Bool())
val plic = new GatewayPLICIO
})
val inFlight = RegInit(false.B)
when (io.interrupt && io.plic.ready) { inFlight := true.B }
when (io.plic.complete) { inFlight := false.B }
io.plic.valid := io.interrupt && !inFlight
}
object PLICConsts
{
def maxDevices = 1023
def maxMaxHarts = 15872
def priorityBase = 0x0
def pendingBase = 0x1000
def enableBase = 0x2000
def hartBase = 0x200000
def claimOffset = 4
def priorityBytes = 4
def enableOffset(i: Int) = i * ((maxDevices+7)/8)
def hartOffset(i: Int) = i * 0x1000
def enableBase(i: Int):Int = enableOffset(i) + enableBase
def hartBase(i: Int):Int = hartOffset(i) + hartBase
def size(maxHarts: Int): Int = {
require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}")
1 << log2Ceil(hartBase(maxHarts))
}
require(hartBase >= enableBase(maxMaxHarts))
}
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)
}
case object PLICKey extends Field[Option[PLICParams]](None)
case class PLICAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object PLICAttachKey extends Field(PLICAttachParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val extra = Map(
"interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)),
"riscv,max-priority" -> Seq(ResourceInt(nPriorities)),
"#interrupt-cells" -> Seq(ResourceInt(1)))
Description(name, mapping ++ extra)
}
}
val node : TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes,
undefZero = true,
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode: IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum
def minPriorities = min(params.maxPriorities, nDevices)
def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1
def nHarts = intnode.edges.out.map(_.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edges.in.map(_.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
ResourceBinding {
flatSources.foreach { s => s.resources.foreach { r =>
// +1 because interrupt 0 is reserved
(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
} }
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io_harts.flatten
def getNInterrupts = interrupts.size
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>
// +1 because 0 is reserved, +1-1 because the range is half-open
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
}
println("")
require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}")
require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}")
require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}")
require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}")
// For now, use LevelGateways for all TL2 interrupts
val gateways = interrupts.map { case i =>
val gateway = Module(new LevelGateway)
gateway.io.interrupt := i
gateway.io.plic
}
val prioBits = log2Ceil(nPriorities+1)
val priority =
if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nDevices max 1)(1.U))
val threshold =
if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nHarts)(0.U))
val pending = RegInit(VecInit.fill(nDevices max 1){false.B})
/* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */
val firstEnable = nDevices min 7
val fullEnables = (nDevices - firstEnable) / 8
val tailEnable = nDevices - firstEnable - 8*fullEnables
def enableRegs = (Reg(UInt(firstEnable.W)) +:
Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++
(if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)
val enables = Seq.fill(nHarts) { enableRegs }
val enableVec = VecInit(enables.map(x => Cat(x.reverse)))
val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))
val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
val pendingUInt = Cat(pending.reverse)
if(nDevices > 0) {
for (hart <- 0 until nHarts) {
val fanin = Module(new PLICFanIn(nDevices, prioBits))
fanin.io.prio := priority
fanin.io.ip := enableVec(hart) & pendingUInt
maxDevs(hart) := fanin.io.dev
harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
}
}
// Priority registers are 32-bit aligned so treat each as its own group.
// Otherwise, the off-by-one nature of the priority registers gets confusing.
require(PLICConsts.priorityBytes == 4,
s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}")
def priorityRegDesc(i: Int) =
RegFieldDesc(
name = s"priority_$i",
desc = s"Acting priority of interrupt source $i",
group = Some(s"priority_${i}"),
groupDesc = Some(s"Acting priority of interrupt source ${i}"),
reset = if (nPriorities > 0) None else Some(1))
def pendingRegDesc(i: Int) =
RegFieldDesc(
name = s"pending_$i",
desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
group = Some("pending"),
groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."),
volatile = true)
def enableRegDesc(i: Int, j: Int, wide: Int) = {
val low = if (j == 0) 1 else j*8
val high = low + wide - 1
RegFieldDesc(
name = s"enables_${j}",
desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.",
group = Some(s"enables_${i}"),
groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."))
}
def priorityRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, priorityRegDesc(i))
} else {
RegField.r(prioBits, x, priorityRegDesc(i))
}
val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>
PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->
Seq(priorityRegField(p, i+1)) }
val pendingRegFields = Seq(PLICConsts.pendingBase ->
(RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>
RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }
// When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot
val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)
val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)
((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>
g.ready := !p
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
val completerDev = Wire(UInt(log2Up(nDevices + 1).W))
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)
(gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>
g.complete := c
}
def thresholdRegDesc(i: Int) =
RegFieldDesc(
name = s"threshold_$i",
desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
reset = if (nPriorities > 0) None else Some(1))
def thresholdRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, thresholdRegDesc(i))
} else {
RegField.r(prioBits, x, thresholdRegDesc(i))
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
PLICConsts.hartBase(i) -> Seq(
thresholdRegField(threshold(i), i),
RegField(32-prioBits),
RegField(32,
RegReadFn { valid =>
claimer(i) := valid
(true.B, maxDevs(i))
},
RegWriteFn { (valid, data) =>
assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
"completerDev should be consistent for all harts")
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enableVec0(i)(completerDev)
true.B
},
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
wrType = Some(RegFieldWrType.MODIFY),
rdAction = Some(RegFieldRdAction.MODIFY),
volatile = true))
)
)
}
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0.U
val completed = completer(0)
property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}
class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
val io = IO(new Bundle {
val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
val ip = Flipped(UInt(nDevices.W))
val dev = UInt(log2Ceil(nDevices+1).W)
val max = UInt(prioBits.W)
})
def findMax(x: Seq[UInt]): (UInt, UInt) = {
if (x.length > 1) {
val half = 1 << (log2Ceil(x.length) - 1)
val left = findMax(x take half)
val right = findMax(x drop half)
MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
} else (x.head, 0.U)
}
val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
val (maxPri, maxDev) = findMax(effectivePriority)
io.max := maxPri // strips the always-constant high '1' bit
io.dev := maxDev
}
/** Trait that will connect a PLIC to a subsystem */
trait CanHavePeripheryPLIC { this: BaseSubsystem =>
val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
(plic, plicDomainWrapper)
}.unzip
}
| module PLICFanIn_1( // @[Plic.scala:338:7]
input clock, // @[Plic.scala:338:7]
input reset, // @[Plic.scala:338:7]
input io_prio_0, // @[Plic.scala:339:14]
input io_ip, // @[Plic.scala:339:14]
output io_dev, // @[Plic.scala:339:14]
output io_max // @[Plic.scala:339:14]
);
wire io_prio_0_0 = io_prio_0; // @[Plic.scala:338:7]
wire io_ip_0 = io_ip; // @[Plic.scala:338:7]
wire [1:0] effectivePriority_0 = 2'h2; // @[Plic.scala:355:32]
wire _effectivePriority_T = io_ip_0; // @[Plic.scala:338:7, :355:55]
wire maxDev; // @[Misc.scala:35:36]
wire io_dev_0; // @[Plic.scala:338:7]
wire io_max_0; // @[Plic.scala:338:7]
wire [1:0] effectivePriority_1 = {_effectivePriority_T, io_prio_0_0}; // @[Plic.scala:338:7, :355:{55,100}]
wire [1:0] maxPri = effectivePriority_1 != 2'h3 ? 2'h2 : effectivePriority_1; // @[Misc.scala:35:9]
assign maxDev = &effectivePriority_1; // @[Misc.scala:35:36]
assign io_dev_0 = maxDev; // @[Misc.scala:35:36]
assign io_max_0 = maxPri[0]; // @[Misc.scala:35:9]
assign io_dev = io_dev_0; // @[Plic.scala:338:7]
assign io_max = io_max_0; // @[Plic.scala:338:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w1_i0_23( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
input io_en // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire io_en_0 = io_en; // @[AsyncResetReg.scala:56:7]
wire _reg_T = 1'h1; // @[AsyncResetReg.scala:56:7, :61:29]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
wire reg_0 = 1'h0; // @[AsyncResetReg.scala:61:50]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AesCipherCore.scala:
// See LICENSE for license details
package aes
import sys.process._
import chisel3._
import chisel3.util._
import chisel3.util.random.{LFSR}
import freechips.rocketchip.util.{DecoupledHelper}
import roccaccutils._
// Non-exhaustive list of resources used to integrate:
// https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38a.pdf
// https://opentitan.org/book/doc/introduction.html
// https://github.com/lowRISC/opentitan/blob/fe702b60582f7c4e5549352a09e7992544d41bec/
// hw/ip/aes/rtl/aes_core.sv
// hw/ip/aes/rtl/aes_control_fsm.sv
// hw/ip/aes/rtl/aes_reg_top.sv
// sw/device/lib/crypto/drivers/aes.c
// sw/device/lib/crypto/drivers/aes_test.c
trait AESConsts {
val BLOCK_SZ_BYTES = 16
val BLOCK_SZ_BITS = BLOCK_SZ_BYTES * 8
}
object AES256Consts extends AESConsts {
val KEY_SZ_BYTES = 32
val KEY_SZ_BITS = KEY_SZ_BYTES * 8
}
import AES256Consts._
// AES256 Encrypt/Decrypt Block (ECB-mode, no security masking)
class AesCipherCoreWrapper_AES256_ECB_NoMask
//extends BlackBox with HasBlackBoxResource {
// TODO: BlackBoxPath causes issues when there are duplicates in firtool
extends BlackBox with HasBlackBoxPath {
val io = IO(new Bundle {
val clk_i = Input(Clock())
val rst_ni = Input(Reset())
val in_valid_i = Input(Bool())
val in_ready_o = Output(Bool())
val out_valid_o = Output(Bool())
val out_ready_i = Input(Bool())
val op_i = Input(UInt(2.W))
val key_len_i = Input(UInt(3.W))
val crypt_i = Input(Bool())
val dec_key_gen_i = Input(Bool())
val prng_reseed_i = Input(Bool())
val prd_clearing_i_0 = Input(UInt(64.W))
val data_in_mask_o = Output(UInt(BLOCK_SZ_BITS.W))
val entropy_req_o = Output(Bool())
val entropy_ack_i = Input(Bool())
val entropy_i = Input(UInt(32.W))
val state_init_i_0 = Input(UInt(BLOCK_SZ_BITS.W))
val key_init_i_0 = Input(UInt(KEY_SZ_BITS.W))
val state_o_0 = Output(UInt(BLOCK_SZ_BITS.W))
val alert_o = Output(Bool())
})
def in_fire() = io.in_valid_i && io.in_ready_o
def out_fire() = io.out_valid_o && io.out_ready_i
val chipyardDir = System.getProperty("user.dir")
val aesDir = s"$chipyardDir/generators/caliptra-aes-acc/src/main/resources/"
val vsrcDirPostfix = "vsrc/aes/aes_cipher_core"
val proc = s"make -C ${aesDir + vsrcDirPostfix} core"
require(proc.! == 0, "Failed to run pre-processing step")
addPath(s"${aesDir + vsrcDirPostfix}/core.sv")
//addResource(s"$vsrcDirPostfix/core.sv")
}
class InCryptBundle extends Bundle {
val encrypt = Input(Bool()) // if not then decrypt
val data = Input(UInt(BLOCK_SZ_BITS.W))
val key = Input(UInt(KEY_SZ_BITS.W))
}
class OutCryptBundle extends Bundle {
val data = Output(UInt(BLOCK_SZ_BITS.W))
}
// ECB-mode AES-256 block driver
// - Expects the key to stay the same throughout the entire time of {en,de}crypting
class AesCipherCoreDriver extends Module {
val io = IO(new Bundle {
val in = Flipped(DecoupledIO(new InCryptBundle))
val out = DecoupledIO(new OutCryptBundle)
})
object AesCipherCoreConsts {
val AES_256 = "b100".U
val CIPH_FWD = "b01".U
val CIPH_INV = "b10".U
}
import AesCipherCoreConsts._
val acc = Module(new AesCipherCoreWrapper_AES256_ECB_NoMask)
acc.io.clk_i := clock
acc.io.rst_ni := !reset.asBool
acc.io.key_len_i := AES_256
acc.io.entropy_ack_i := true.B // entropy is always available
val entropy_i = RegInit(0.U(32.W))
when (acc.io.entropy_req_o) {
entropy_i := LFSR(32, acc.io.entropy_req_o)
}
acc.io.entropy_i := entropy_i
val prd_clearing_i_0 = RegInit(0.U(64.W))
when (acc.io.out_valid_o) {
prd_clearing_i_0 := LFSR(32, acc.io.out_valid_o)
}
acc.io.prd_clearing_i_0 := prd_clearing_i_0
val s_initial_idle :: s_idle :: s_encrypt :: s_dec_key_gen :: s_decrypt :: Nil = Enum(5)
val state = RegInit(s_initial_idle)
val prev_state = RegInit(s_initial_idle)
switch (state) {
// wait for core to be ready
is (s_initial_idle) {
when (acc.io.in_ready_o) {
state := s_idle
prev_state := s_initial_idle
}
}
// start here when switching from encrypt to decrypt
is (s_idle) {
when (io.in.valid) {
// since we go back to idle after sending and encrypt/decrypt req, make sure to return to that state
// if you started in that state (i.e. only go to dec_key_gen when there is a switch from encrypt -> decrypt)
state := Mux(io.in.bits.encrypt, s_encrypt, Mux(prev_state === s_decrypt, s_decrypt, s_dec_key_gen))
prev_state := s_idle
}
}
is (s_encrypt) {
when (io.in.fire) {
state := s_idle
prev_state := s_encrypt
}
}
// create initial decryption key
is (s_dec_key_gen) {
when (acc.out_fire()) {
state := s_decrypt
prev_state := s_dec_key_gen
}
}
is (s_decrypt) {
when (io.in.fire) {
state := s_idle
prev_state := s_decrypt
}
}
}
val op = RegInit(CIPH_FWD)
acc.io.key_init_i_0 := io.in.bits.key
val encrypt_send_helper = DecoupledHelper(
state === s_encrypt,
io.in.valid,
io.in.ready
)
val decrypt_send_helper = DecoupledHelper(
state === s_decrypt,
io.in.valid,
io.in.ready
)
val dec_key_send_helper = DecoupledHelper(
state === s_dec_key_gen,
io.in.valid,
io.in.ready
)
when (io.in.fire) {
printf(":AES:CMDIN: Encrypt(0x%x) Data(0x%x) Key(0x%x)\n",
io.in.bits.encrypt,
io.in.bits.data,
io.in.bits.key)
}
when (io.out.fire) {
printf(":AES:RESPOUT: Data(0x%x)\n", io.out.bits.data)
}
val is_initial_state = (state === s_initial_idle)
val is_non_state = (state === s_dec_key_gen)
val is_all_non_state = is_initial_state || is_non_state
acc.io.in_valid_i := encrypt_send_helper.fire(io.in.ready) ||
dec_key_send_helper.fire(io.in.ready) ||
decrypt_send_helper.fire(io.in.ready)
io.in.ready := acc.io.in_ready_o && !is_all_non_state && (state =/= s_idle)
io.out.valid := acc.io.out_valid_o && !is_all_non_state
acc.io.out_ready_i := io.out.ready || is_all_non_state
io.out.bits.data := acc.io.state_o_0
acc.io.dec_key_gen_i := (state === s_dec_key_gen)
acc.io.crypt_i := true.B
acc.io.prng_reseed_i := true.B
acc.io.state_init_i_0 := io.in.bits.data
acc.io.op_i := Mux(
(state === s_decrypt) || ((state === s_idle) && (prev_state === s_decrypt)),
CIPH_INV,
CIPH_FWD)
}
| module AesCipherCoreDriver( // @[AesCipherCore.scala:96:7]
input clock, // @[AesCipherCore.scala:96:7]
input reset, // @[AesCipherCore.scala:96:7]
output io_in_ready, // @[AesCipherCore.scala:97:14]
input io_in_valid, // @[AesCipherCore.scala:97:14]
input io_in_bits_encrypt, // @[AesCipherCore.scala:97:14]
input [127:0] io_in_bits_data, // @[AesCipherCore.scala:97:14]
input [255:0] io_in_bits_key, // @[AesCipherCore.scala:97:14]
input io_out_ready, // @[AesCipherCore.scala:97:14]
output io_out_valid, // @[AesCipherCore.scala:97:14]
output [127:0] io_out_bits_data // @[AesCipherCore.scala:97:14]
);
wire _prd_clearing_i_0_prng_io_out_0; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_1; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_2; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_3; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_4; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_5; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_6; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_7; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_8; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_9; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_10; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_11; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_12; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_13; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_14; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_15; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_16; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_17; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_18; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_19; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_20; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_21; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_22; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_23; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_24; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_25; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_26; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_27; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_28; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_29; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_30; // @[PRNG.scala:91:22]
wire _prd_clearing_i_0_prng_io_out_31; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_0; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_1; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_2; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_3; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_4; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_5; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_6; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_7; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_8; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_9; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_10; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_11; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_12; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_13; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_14; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_15; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_16; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_17; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_18; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_19; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_20; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_21; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_22; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_23; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_24; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_25; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_26; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_27; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_28; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_29; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_30; // @[PRNG.scala:91:22]
wire _entropy_i_prng_io_out_31; // @[PRNG.scala:91:22]
wire _acc_in_ready_o; // @[AesCipherCore.scala:110:19]
wire _acc_out_valid_o; // @[AesCipherCore.scala:110:19]
wire _acc_entropy_req_o; // @[AesCipherCore.scala:110:19]
wire io_in_valid_0 = io_in_valid; // @[AesCipherCore.scala:96:7]
wire io_in_bits_encrypt_0 = io_in_bits_encrypt; // @[AesCipherCore.scala:96:7]
wire [127:0] io_in_bits_data_0 = io_in_bits_data; // @[AesCipherCore.scala:96:7]
wire [255:0] io_in_bits_key_0 = io_in_bits_key; // @[AesCipherCore.scala:96:7]
wire io_out_ready_0 = io_out_ready; // @[AesCipherCore.scala:96:7]
wire _acc_io_rst_ni_T = reset; // @[AesCipherCore.scala:112:27]
wire _io_in_ready_T_3; // @[AesCipherCore.scala:212:57]
wire _io_out_valid_T_1; // @[AesCipherCore.scala:214:38]
wire io_in_ready_0; // @[AesCipherCore.scala:96:7]
wire [127:0] io_out_bits_data_0; // @[AesCipherCore.scala:96:7]
wire io_out_valid_0; // @[AesCipherCore.scala:96:7]
wire _acc_io_rst_ni_T_1 = ~_acc_io_rst_ni_T; // @[AesCipherCore.scala:112:{20,27}]
reg [31:0] entropy_i; // @[AesCipherCore.scala:116:26]
wire [1:0] entropy_i_lo_lo_lo_lo = {_entropy_i_prng_io_out_1, _entropy_i_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_lo_lo_lo_hi = {_entropy_i_prng_io_out_3, _entropy_i_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_lo_lo_lo = {entropy_i_lo_lo_lo_hi, entropy_i_lo_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_lo_lo_hi_lo = {_entropy_i_prng_io_out_5, _entropy_i_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_lo_lo_hi_hi = {_entropy_i_prng_io_out_7, _entropy_i_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_lo_lo_hi = {entropy_i_lo_lo_hi_hi, entropy_i_lo_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] entropy_i_lo_lo = {entropy_i_lo_lo_hi, entropy_i_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_lo_hi_lo_lo = {_entropy_i_prng_io_out_9, _entropy_i_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_lo_hi_lo_hi = {_entropy_i_prng_io_out_11, _entropy_i_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_lo_hi_lo = {entropy_i_lo_hi_lo_hi, entropy_i_lo_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_lo_hi_hi_lo = {_entropy_i_prng_io_out_13, _entropy_i_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_lo_hi_hi_hi = {_entropy_i_prng_io_out_15, _entropy_i_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_lo_hi_hi = {entropy_i_lo_hi_hi_hi, entropy_i_lo_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] entropy_i_lo_hi = {entropy_i_lo_hi_hi, entropy_i_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] entropy_i_lo = {entropy_i_lo_hi, entropy_i_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_hi_lo_lo_lo = {_entropy_i_prng_io_out_17, _entropy_i_prng_io_out_16}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_hi_lo_lo_hi = {_entropy_i_prng_io_out_19, _entropy_i_prng_io_out_18}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_hi_lo_lo = {entropy_i_hi_lo_lo_hi, entropy_i_hi_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_hi_lo_hi_lo = {_entropy_i_prng_io_out_21, _entropy_i_prng_io_out_20}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_hi_lo_hi_hi = {_entropy_i_prng_io_out_23, _entropy_i_prng_io_out_22}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_hi_lo_hi = {entropy_i_hi_lo_hi_hi, entropy_i_hi_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] entropy_i_hi_lo = {entropy_i_hi_lo_hi, entropy_i_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_hi_hi_lo_lo = {_entropy_i_prng_io_out_25, _entropy_i_prng_io_out_24}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_hi_hi_lo_hi = {_entropy_i_prng_io_out_27, _entropy_i_prng_io_out_26}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_hi_hi_lo = {entropy_i_hi_hi_lo_hi, entropy_i_hi_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] entropy_i_hi_hi_hi_lo = {_entropy_i_prng_io_out_29, _entropy_i_prng_io_out_28}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] entropy_i_hi_hi_hi_hi = {_entropy_i_prng_io_out_31, _entropy_i_prng_io_out_30}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] entropy_i_hi_hi_hi = {entropy_i_hi_hi_hi_hi, entropy_i_hi_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] entropy_i_hi_hi = {entropy_i_hi_hi_hi, entropy_i_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] entropy_i_hi = {entropy_i_hi_hi, entropy_i_hi_lo}; // @[PRNG.scala:95:17]
wire [31:0] _entropy_i_T = {entropy_i_hi, entropy_i_lo}; // @[PRNG.scala:95:17]
reg [63:0] prd_clearing_i_0; // @[AesCipherCore.scala:121:33]
wire [1:0] prd_clearing_i_0_lo_lo_lo_lo = {_prd_clearing_i_0_prng_io_out_1, _prd_clearing_i_0_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_lo_lo_lo_hi = {_prd_clearing_i_0_prng_io_out_3, _prd_clearing_i_0_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_lo_lo_lo = {prd_clearing_i_0_lo_lo_lo_hi, prd_clearing_i_0_lo_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_lo_lo_hi_lo = {_prd_clearing_i_0_prng_io_out_5, _prd_clearing_i_0_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_lo_lo_hi_hi = {_prd_clearing_i_0_prng_io_out_7, _prd_clearing_i_0_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_lo_lo_hi = {prd_clearing_i_0_lo_lo_hi_hi, prd_clearing_i_0_lo_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] prd_clearing_i_0_lo_lo = {prd_clearing_i_0_lo_lo_hi, prd_clearing_i_0_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_lo_hi_lo_lo = {_prd_clearing_i_0_prng_io_out_9, _prd_clearing_i_0_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_lo_hi_lo_hi = {_prd_clearing_i_0_prng_io_out_11, _prd_clearing_i_0_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_lo_hi_lo = {prd_clearing_i_0_lo_hi_lo_hi, prd_clearing_i_0_lo_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_lo_hi_hi_lo = {_prd_clearing_i_0_prng_io_out_13, _prd_clearing_i_0_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_lo_hi_hi_hi = {_prd_clearing_i_0_prng_io_out_15, _prd_clearing_i_0_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_lo_hi_hi = {prd_clearing_i_0_lo_hi_hi_hi, prd_clearing_i_0_lo_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] prd_clearing_i_0_lo_hi = {prd_clearing_i_0_lo_hi_hi, prd_clearing_i_0_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] prd_clearing_i_0_lo = {prd_clearing_i_0_lo_hi, prd_clearing_i_0_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_hi_lo_lo_lo = {_prd_clearing_i_0_prng_io_out_17, _prd_clearing_i_0_prng_io_out_16}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_hi_lo_lo_hi = {_prd_clearing_i_0_prng_io_out_19, _prd_clearing_i_0_prng_io_out_18}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_hi_lo_lo = {prd_clearing_i_0_hi_lo_lo_hi, prd_clearing_i_0_hi_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_hi_lo_hi_lo = {_prd_clearing_i_0_prng_io_out_21, _prd_clearing_i_0_prng_io_out_20}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_hi_lo_hi_hi = {_prd_clearing_i_0_prng_io_out_23, _prd_clearing_i_0_prng_io_out_22}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_hi_lo_hi = {prd_clearing_i_0_hi_lo_hi_hi, prd_clearing_i_0_hi_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] prd_clearing_i_0_hi_lo = {prd_clearing_i_0_hi_lo_hi, prd_clearing_i_0_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_hi_hi_lo_lo = {_prd_clearing_i_0_prng_io_out_25, _prd_clearing_i_0_prng_io_out_24}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_hi_hi_lo_hi = {_prd_clearing_i_0_prng_io_out_27, _prd_clearing_i_0_prng_io_out_26}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_hi_hi_lo = {prd_clearing_i_0_hi_hi_lo_hi, prd_clearing_i_0_hi_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] prd_clearing_i_0_hi_hi_hi_lo = {_prd_clearing_i_0_prng_io_out_29, _prd_clearing_i_0_prng_io_out_28}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] prd_clearing_i_0_hi_hi_hi_hi = {_prd_clearing_i_0_prng_io_out_31, _prd_clearing_i_0_prng_io_out_30}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] prd_clearing_i_0_hi_hi_hi = {prd_clearing_i_0_hi_hi_hi_hi, prd_clearing_i_0_hi_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] prd_clearing_i_0_hi_hi = {prd_clearing_i_0_hi_hi_hi, prd_clearing_i_0_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] prd_clearing_i_0_hi = {prd_clearing_i_0_hi_hi, prd_clearing_i_0_hi_lo}; // @[PRNG.scala:95:17]
wire [31:0] _prd_clearing_i_0_T = {prd_clearing_i_0_hi, prd_clearing_i_0_lo}; // @[PRNG.scala:95:17]
reg [2:0] state; // @[AesCipherCore.scala:128:22]
reg [2:0] prev_state; // @[AesCipherCore.scala:129:27]
wire is_initial_state = state == 3'h0; // @[AesCipherCore.scala:128:22, :131:18, :205:33]
wire _GEN = prev_state == 3'h4; // @[AesCipherCore.scala:129:27, :145:68]
wire _state_T; // @[AesCipherCore.scala:145:68]
assign _state_T = _GEN; // @[AesCipherCore.scala:145:68]
wire _acc_io_op_i_T_2; // @[AesCipherCore.scala:225:65]
assign _acc_io_op_i_T_2 = _GEN; // @[AesCipherCore.scala:145:68, :225:65]
wire [2:0] _state_T_1 = _state_T ? 3'h4 : 3'h3; // @[AesCipherCore.scala:145:{56,68}]
wire [2:0] _state_T_2 = io_in_bits_encrypt_0 ? 3'h2 : _state_T_1; // @[AesCipherCore.scala:96:7, :145:{21,56}]
wire _acc_io_op_i_T = state == 3'h4; // @[AesCipherCore.scala:128:22, :183:11, :225:12]
wire _T_10 = state == 3'h3; // @[AesCipherCore.scala:128:22, :189:11]
wire is_non_state; // @[AesCipherCore.scala:206:29]
assign is_non_state = _T_10; // @[AesCipherCore.scala:189:11, :206:29]
wire _acc_io_dec_key_gen_i_T; // @[AesCipherCore.scala:218:34]
assign _acc_io_dec_key_gen_i_T = _T_10; // @[AesCipherCore.scala:189:11, :218:34] |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_20( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_20 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_221( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_142( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? 5'h0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_3( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_259 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_188( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_194( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module TLNoC_router_14ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_13 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready),
.auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid),
.auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head),
.auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload),
.auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLWidthWidget32_2( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71]
wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24]
wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25]
wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53]
assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] count; // @[WidthWidget.scala:40:27]
wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 2'h0; // @[WidthWidget.scala:105:26]
count <= 2'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
end
always @(posedge)
TLMonitor_60 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d256s5k3z4u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File HasTiles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
import freechips.rocketchip.tilelink.TLWidthWidget
import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing}
import freechips.rocketchip.rocket.TracedInstruction
import freechips.rocketchip.util.TraceCoreInterface
import scala.collection.immutable.SortedMap
/** Entry point for Config-uring the presence of Tiles */
case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil)
/** List of HierarchicalLocations which might contain a Tile */
case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil)
/** For determining static tile id */
case object NumTiles extends Field[Int](0)
/** Whether to add timing-closure registers along the path of the hart id
* as it propagates through the subsystem and into the tile.
*
* These are typically only desirable when a dynamically programmable prefix is being combined
* with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]].
*/
case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false)
/** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block,
* and if so, what their width should be.
*/
case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None)
/** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block.
*
* Unlike the hart ids, the reset vector width is determined by the sinks within the tiles,
* based on the size of the address map visible to the tiles.
*/
case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
/** These are sources of "constants" that are driven into the tile.
*
* While they are not expected to change dyanmically while the tile is executing code,
* they may be either tied to a contant value or programmed during boot or reset.
* They need to be instantiated before tiles are attached within the subsystem containing them.
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes.
*
* Each "prefix" input is actually the same full width as the outer hart id; the expected usage
* is that each prefix source would set only some non-overlapping portion of the bits to non-zero values.
* This node orReduces them, and further combines the reduction with the static ids assigned to each tile,
* producing a unique, dynamic hart id for each tile.
*
* If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered.
*
* The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into
* the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous.
*/
val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _,
outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i =>
val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup
if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y
},
default = Some(() => 0.U(p(MaxHartIdBits).W)),
inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below
shouldBeInlined = false // can't inline something whose output we are are dontTouching
)).node
// TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs
/** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */
val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */
val tileResetVectorNexusNode = BundleBroadcast[UInt](
inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below
)
/** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids.
*
* Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile.
*/
val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match {
case Some(w) => (0 until nTotalTiles).map { i =>
val hartIdSource = BundleBridgeSource(() => UInt(w.W))
tileHartIdNodes(i) := hartIdSource
hartIdSource
}
case None => {
(0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode }
Nil
}
}
/** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors.
*
* Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile.
*/
val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match {
case true => (0 until nTotalTiles).map { i =>
val resetVectorSource = BundleBridgeSource[UInt]()
tileResetVectorNodes(i) := resetVectorSource
resetVectorSource
}
case false => {
(0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode }
Nil
}
}
}
/** These are sinks of notifications that are driven out from the tile.
*
* They need to be instantiated before tiles are attached to the subsystem containing them.
*/
trait HasTileNotificationSinks { this: LazyModule =>
val tileHaltXbarNode = IntXbar()
val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple())
tileHaltSinkNode := tileHaltXbarNode
val tileWFIXbarNode = IntXbar()
val tileWFISinkNode = IntSinkNode(IntSinkPortSimple())
tileWFISinkNode := tileWFIXbarNode
val tileCeaseXbarNode = IntXbar()
val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple())
tileCeaseSinkNode := tileCeaseXbarNode
}
/** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources.
*
* Sub-classes of this trait can optionally override the individual connect functions in order to specialize
* their attachment behaviors, but most use cases should be be handled simply by changing the implementation
* of the injectNode functions in crossingParams.
*/
trait CanAttachTile {
type TileType <: BaseTile
type TileContextType <: DefaultHierarchicalElementContextType
def tileParams: InstantiableTileParams[TileType]
def crossingParams: HierarchicalElementCrossingParamsLike
/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
})
tile_prci_domain
}
/** A default set of connections that need to occur for most tile types */
def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
connectMasterPorts(domain, context)
connectSlavePorts(domain, context)
connectInterrupts(domain, context)
connectPRC(domain, context)
connectOutputNotifications(domain, context)
connectInputConstants(domain, context)
connectTrace(domain, context)
}
/** Connect the port where the tile is the master to a TileLink interconnect. */
def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
val dataBus = context.locateTLBusWrapper(crossingParams.master.where)
dataBus.coupleFrom(tileParams.baseName) { bus =>
bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType)
}
}
/** Connect the port where the tile is the slave to a TileLink interconnect. */
def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
DisableMonitors { implicit p =>
val controlBus = context.locateTLBusWrapper(crossingParams.slave.where)
controlBus.coupleTo(tileParams.baseName) { bus =>
domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus
}
}
}
/** Connect the various interrupts sent to and and raised by the tile. */
def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
// NOTE: The order of calls to := matters! They must match how interrupts
// are decoded from tile.intInwardNode inside the tile. For this reason,
// we stub out missing interrupts with constant sources here.
// 1. Debug interrupt is definitely asynchronous in all cases.
domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } :=
context.debugNodes(domain.element.tileId)
// 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively,
// so might need to be synchronized depending on the Tile's crossing type.
// From CLINT: "msip" and "mtip"
context.msipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.msipNodes(domain.element.tileId)
}
// From PLIC: "meip"
context.meipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.meipNodes(domain.element.tileId)
}
// From PLIC: "seip" (only if supervisor mode is enabled)
if (domain.element.tileParams.core.hasSupervisorMode) {
context.seipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.seipNodes(domain.element.tileId)
}
}
// 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock.
// (they are connected to domain.element.intInwardNode in a seperate trait)
// 4. Interrupts coming out of the tile are sent to the PLIC,
// so might need to be synchronized depending on the Tile's crossing type.
context.tileToPlicNodes.get(domain.element.tileId).foreach { node =>
FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out =>
context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) }
}}
}
// 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock.
domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId))
}
/** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */
def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
domain {
context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode)
context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode)
context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode)
}
// TODO should context be forced to have a trace sink connected here?
// for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally
}
/** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */
def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere)
domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId)
domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId)
tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ }
}
/** Connect power/reset/clock resources. */
def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where)
(crossingParams.crossingType match {
case _: SynchronousCrossing | _: CreditedCrossing =>
if (crossingParams.forceSeparateClockReset) {
domain.clockNode := tlBusToGetClockDriverFrom.clockNode
} else {
domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
}
case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
case _: AsynchronousCrossing => {
val tileClockGroup = ClockGroup()
tileClockGroup := context.allClockGroupsNode
domain.clockNode := tileClockGroup
}
})
domain {
domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
}
}
/** Function to handle all trace crossings when tile is instantiated inside domains */
def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle](
resetCrossingType = crossingParams.resetCrossingType)
context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode
val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface](
resetCrossingType = crossingParams.resetCrossingType)
context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode
}
}
case class CloneTileAttachParams(
sourceTileId: Int,
cloneParams: CanAttachTile
) extends CanAttachTile {
type TileType = cloneParams.TileType
type TileContextType = cloneParams.TileContextType
def tileParams = cloneParams.tileParams
def crossingParams = cloneParams.crossingParams
override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
require(instantiatedTiles.contains(sourceTileId))
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = CloneLazyModule(
new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
},
instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]]
)
tile_prci_domain
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TilePRCIDomain( // @[ClockDomain.scala:14:9]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_wdata, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset, // @[LazyModuleImp.scala:107:25]
output clock, // @[ClockDomain.scala:21:19]
output reset // @[ClockDomain.scala:22:19]
);
wire _intsink_3_auto_out_0; // @[Crossing.scala:109:29]
wire _intsink_2_auto_out_0; // @[Crossing.scala:109:29]
wire _intsink_1_auto_out_0; // @[Crossing.scala:109:29]
wire _intsink_1_auto_out_1; // @[Crossing.scala:109:29]
wire _intsink_auto_out_0; // @[Crossing.scala:86:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_b_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_b_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_b_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_b_bits_size; // @[Buffer.scala:75:28]
wire [5:0] _buffer_auto_in_b_bits_source; // @[Buffer.scala:75:28]
wire [31:0] _buffer_auto_in_b_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_in_b_bits_mask; // @[Buffer.scala:75:28]
wire _buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_in_c_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [5:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_in_e_ready; // @[Buffer.scala:75:28]
wire _element_reset_domain_rockettile_auto_buffer_out_a_valid; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_opcode; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_param; // @[HasTiles.scala:164:59]
wire [3:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_size; // @[HasTiles.scala:164:59]
wire [5:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_source; // @[HasTiles.scala:164:59]
wire [31:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_address; // @[HasTiles.scala:164:59]
wire [7:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_mask; // @[HasTiles.scala:164:59]
wire [63:0] _element_reset_domain_rockettile_auto_buffer_out_a_bits_data; // @[HasTiles.scala:164:59]
wire _element_reset_domain_rockettile_auto_buffer_out_a_bits_corrupt; // @[HasTiles.scala:164:59]
wire _element_reset_domain_rockettile_auto_buffer_out_b_ready; // @[HasTiles.scala:164:59]
wire _element_reset_domain_rockettile_auto_buffer_out_c_valid; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_opcode; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_param; // @[HasTiles.scala:164:59]
wire [3:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_size; // @[HasTiles.scala:164:59]
wire [5:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_source; // @[HasTiles.scala:164:59]
wire [31:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_address; // @[HasTiles.scala:164:59]
wire [63:0] _element_reset_domain_rockettile_auto_buffer_out_c_bits_data; // @[HasTiles.scala:164:59]
wire _element_reset_domain_rockettile_auto_buffer_out_d_ready; // @[HasTiles.scala:164:59]
wire _element_reset_domain_rockettile_auto_buffer_out_e_valid; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_rockettile_auto_buffer_out_e_bits_sink; // @[HasTiles.scala:164:59]
wire _element_reset_domain_rockettile_auto_wfi_out_0; // @[HasTiles.scala:164:59]
RocketTile element_reset_domain_rockettile ( // @[HasTiles.scala:164:59]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_buffer_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_buffer_out_a_valid (_element_reset_domain_rockettile_auto_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (_element_reset_domain_rockettile_auto_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (_element_reset_domain_rockettile_auto_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (_element_reset_domain_rockettile_auto_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (_element_reset_domain_rockettile_auto_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (_element_reset_domain_rockettile_auto_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (_element_reset_domain_rockettile_auto_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt (_element_reset_domain_rockettile_auto_buffer_out_a_bits_corrupt),
.auto_buffer_out_b_ready (_element_reset_domain_rockettile_auto_buffer_out_b_ready),
.auto_buffer_out_b_valid (_buffer_auto_in_b_valid), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_opcode (_buffer_auto_in_b_bits_opcode), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_param (_buffer_auto_in_b_bits_param), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_size (_buffer_auto_in_b_bits_size), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_source (_buffer_auto_in_b_bits_source), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_address (_buffer_auto_in_b_bits_address), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_mask (_buffer_auto_in_b_bits_mask), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), // @[Buffer.scala:75:28]
.auto_buffer_out_c_ready (_buffer_auto_in_c_ready), // @[Buffer.scala:75:28]
.auto_buffer_out_c_valid (_element_reset_domain_rockettile_auto_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (_element_reset_domain_rockettile_auto_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (_element_reset_domain_rockettile_auto_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (_element_reset_domain_rockettile_auto_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (_element_reset_domain_rockettile_auto_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (_element_reset_domain_rockettile_auto_buffer_out_c_bits_data),
.auto_buffer_out_d_ready (_element_reset_domain_rockettile_auto_buffer_out_d_ready),
.auto_buffer_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28]
.auto_buffer_out_e_ready (_buffer_auto_in_e_ready), // @[Buffer.scala:75:28]
.auto_buffer_out_e_valid (_element_reset_domain_rockettile_auto_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (_element_reset_domain_rockettile_auto_buffer_out_e_bits_sink),
.auto_wfi_out_0 (_element_reset_domain_rockettile_auto_wfi_out_0),
.auto_int_local_in_3_0 (_intsink_3_auto_out_0), // @[Crossing.scala:109:29]
.auto_int_local_in_2_0 (_intsink_2_auto_out_0), // @[Crossing.scala:109:29]
.auto_int_local_in_1_0 (_intsink_1_auto_out_0), // @[Crossing.scala:109:29]
.auto_int_local_in_1_1 (_intsink_1_auto_out_1), // @[Crossing.scala:109:29]
.auto_int_local_in_0_0 (_intsink_auto_out_0), // @[Crossing.scala:86:29]
.auto_trace_source_out_insns_0_valid (auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid),
.auto_trace_source_out_insns_0_iaddr (auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr),
.auto_trace_source_out_insns_0_insn (auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn),
.auto_trace_source_out_insns_0_priv (auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv),
.auto_trace_source_out_insns_0_exception (auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception),
.auto_trace_source_out_insns_0_interrupt (auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt),
.auto_trace_source_out_insns_0_cause (auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause),
.auto_trace_source_out_insns_0_tval (auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval),
.auto_trace_source_out_insns_0_wdata (auto_element_reset_domain_rockettile_trace_source_out_insns_0_wdata),
.auto_trace_source_out_time (auto_element_reset_domain_rockettile_trace_source_out_time),
.auto_hartid_in (auto_element_reset_domain_rockettile_hartid_in)
); // @[HasTiles.scala:164:59]
TLBuffer_a32d64s6k3z4c_1 buffer ( // @[Buffer.scala:75:28]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_element_reset_domain_rockettile_auto_buffer_out_a_valid), // @[HasTiles.scala:164:59]
.auto_in_a_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_a_bits_opcode), // @[HasTiles.scala:164:59]
.auto_in_a_bits_param (_element_reset_domain_rockettile_auto_buffer_out_a_bits_param), // @[HasTiles.scala:164:59]
.auto_in_a_bits_size (_element_reset_domain_rockettile_auto_buffer_out_a_bits_size), // @[HasTiles.scala:164:59]
.auto_in_a_bits_source (_element_reset_domain_rockettile_auto_buffer_out_a_bits_source), // @[HasTiles.scala:164:59]
.auto_in_a_bits_address (_element_reset_domain_rockettile_auto_buffer_out_a_bits_address), // @[HasTiles.scala:164:59]
.auto_in_a_bits_mask (_element_reset_domain_rockettile_auto_buffer_out_a_bits_mask), // @[HasTiles.scala:164:59]
.auto_in_a_bits_data (_element_reset_domain_rockettile_auto_buffer_out_a_bits_data), // @[HasTiles.scala:164:59]
.auto_in_a_bits_corrupt (_element_reset_domain_rockettile_auto_buffer_out_a_bits_corrupt), // @[HasTiles.scala:164:59]
.auto_in_b_ready (_element_reset_domain_rockettile_auto_buffer_out_b_ready), // @[HasTiles.scala:164:59]
.auto_in_b_valid (_buffer_auto_in_b_valid),
.auto_in_b_bits_opcode (_buffer_auto_in_b_bits_opcode),
.auto_in_b_bits_param (_buffer_auto_in_b_bits_param),
.auto_in_b_bits_size (_buffer_auto_in_b_bits_size),
.auto_in_b_bits_source (_buffer_auto_in_b_bits_source),
.auto_in_b_bits_address (_buffer_auto_in_b_bits_address),
.auto_in_b_bits_mask (_buffer_auto_in_b_bits_mask),
.auto_in_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt),
.auto_in_c_ready (_buffer_auto_in_c_ready),
.auto_in_c_valid (_element_reset_domain_rockettile_auto_buffer_out_c_valid), // @[HasTiles.scala:164:59]
.auto_in_c_bits_opcode (_element_reset_domain_rockettile_auto_buffer_out_c_bits_opcode), // @[HasTiles.scala:164:59]
.auto_in_c_bits_param (_element_reset_domain_rockettile_auto_buffer_out_c_bits_param), // @[HasTiles.scala:164:59]
.auto_in_c_bits_size (_element_reset_domain_rockettile_auto_buffer_out_c_bits_size), // @[HasTiles.scala:164:59]
.auto_in_c_bits_source (_element_reset_domain_rockettile_auto_buffer_out_c_bits_source), // @[HasTiles.scala:164:59]
.auto_in_c_bits_address (_element_reset_domain_rockettile_auto_buffer_out_c_bits_address), // @[HasTiles.scala:164:59]
.auto_in_c_bits_data (_element_reset_domain_rockettile_auto_buffer_out_c_bits_data), // @[HasTiles.scala:164:59]
.auto_in_d_ready (_element_reset_domain_rockettile_auto_buffer_out_d_ready), // @[HasTiles.scala:164:59]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_in_e_ready (_buffer_auto_in_e_ready),
.auto_in_e_valid (_element_reset_domain_rockettile_auto_buffer_out_e_valid), // @[HasTiles.scala:164:59]
.auto_in_e_bits_sink (_element_reset_domain_rockettile_auto_buffer_out_e_bits_sink), // @[HasTiles.scala:164:59]
.auto_out_a_ready (auto_tl_master_clock_xing_out_a_ready),
.auto_out_a_valid (auto_tl_master_clock_xing_out_a_valid),
.auto_out_a_bits_opcode (auto_tl_master_clock_xing_out_a_bits_opcode),
.auto_out_a_bits_param (auto_tl_master_clock_xing_out_a_bits_param),
.auto_out_a_bits_size (auto_tl_master_clock_xing_out_a_bits_size),
.auto_out_a_bits_source (auto_tl_master_clock_xing_out_a_bits_source),
.auto_out_a_bits_address (auto_tl_master_clock_xing_out_a_bits_address),
.auto_out_a_bits_mask (auto_tl_master_clock_xing_out_a_bits_mask),
.auto_out_a_bits_data (auto_tl_master_clock_xing_out_a_bits_data),
.auto_out_a_bits_corrupt (auto_tl_master_clock_xing_out_a_bits_corrupt),
.auto_out_b_ready (auto_tl_master_clock_xing_out_b_ready),
.auto_out_b_valid (auto_tl_master_clock_xing_out_b_valid),
.auto_out_b_bits_param (auto_tl_master_clock_xing_out_b_bits_param),
.auto_out_b_bits_address (auto_tl_master_clock_xing_out_b_bits_address),
.auto_out_c_ready (auto_tl_master_clock_xing_out_c_ready),
.auto_out_c_valid (auto_tl_master_clock_xing_out_c_valid),
.auto_out_c_bits_opcode (auto_tl_master_clock_xing_out_c_bits_opcode),
.auto_out_c_bits_param (auto_tl_master_clock_xing_out_c_bits_param),
.auto_out_c_bits_size (auto_tl_master_clock_xing_out_c_bits_size),
.auto_out_c_bits_source (auto_tl_master_clock_xing_out_c_bits_source),
.auto_out_c_bits_address (auto_tl_master_clock_xing_out_c_bits_address),
.auto_out_c_bits_data (auto_tl_master_clock_xing_out_c_bits_data),
.auto_out_c_bits_corrupt (auto_tl_master_clock_xing_out_c_bits_corrupt),
.auto_out_d_ready (auto_tl_master_clock_xing_out_d_ready),
.auto_out_d_valid (auto_tl_master_clock_xing_out_d_valid),
.auto_out_d_bits_opcode (auto_tl_master_clock_xing_out_d_bits_opcode),
.auto_out_d_bits_param (auto_tl_master_clock_xing_out_d_bits_param),
.auto_out_d_bits_size (auto_tl_master_clock_xing_out_d_bits_size),
.auto_out_d_bits_source (auto_tl_master_clock_xing_out_d_bits_source),
.auto_out_d_bits_sink (auto_tl_master_clock_xing_out_d_bits_sink),
.auto_out_d_bits_denied (auto_tl_master_clock_xing_out_d_bits_denied),
.auto_out_d_bits_data (auto_tl_master_clock_xing_out_d_bits_data),
.auto_out_d_bits_corrupt (auto_tl_master_clock_xing_out_d_bits_corrupt),
.auto_out_e_valid (auto_tl_master_clock_xing_out_e_valid),
.auto_out_e_bits_sink (auto_tl_master_clock_xing_out_e_bits_sink)
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29]
.clock (auto_tap_clock_in_clock),
.auto_in_sync_0 (auto_intsink_in_sync_0),
.auto_out_0 (_intsink_auto_out_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (auto_int_in_clock_xing_in_0_sync_0),
.auto_in_sync_1 (auto_int_in_clock_xing_in_0_sync_1),
.auto_out_0 (_intsink_1_auto_out_0),
.auto_out_1 (_intsink_1_auto_out_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (auto_int_in_clock_xing_in_1_sync_0),
.auto_out_0 (_intsink_2_auto_out_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (auto_int_in_clock_xing_in_2_sync_0),
.auto_out_0 (_intsink_3_auto_out_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_0 (1'h0), // @[Buffer.scala:75:28]
.auto_out_sync_0 (/* unused */)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_0 (_element_reset_domain_rockettile_auto_wfi_out_0), // @[HasTiles.scala:164:59]
.auto_out_sync_0 (/* unused */)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_2 ( // @[Crossing.scala:29:31]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_0 (1'h0), // @[Buffer.scala:75:28]
.auto_out_sync_0 (/* unused */)
); // @[Crossing.scala:29:31]
assign clock = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
assign reset = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_26( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_4 | _route_buffer_io_enq_bits_flow_egress_node_id_T_5 | _route_buffer_io_enq_bits_flow_egress_node_id_T_6 | _route_buffer_io_enq_bits_flow_egress_node_id_T_7}; // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hD; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hD; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_29( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [5:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_19 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_324( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_143( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
| module BranchKillableQueue_7( // @[util.scala:448:7]
input clock, // @[util.scala:448:7]
input reset, // @[util.scala:448:7]
output io_enq_ready, // @[util.scala:453:14]
input io_enq_valid, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:453:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_is_br, // @[util.scala:453:14]
input io_enq_bits_uop_is_jalr, // @[util.scala:453:14]
input io_enq_bits_uop_is_jal, // @[util.scala:453:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:453:14]
input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14]
input io_enq_bits_uop_taken, // @[util.scala:453:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14]
input io_enq_bits_uop_exception, // @[util.scala:453:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14]
input io_enq_bits_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:453:14]
input io_enq_bits_uop_is_fence, // @[util.scala:453:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:453:14]
input io_enq_bits_uop_is_amo, // @[util.scala:453:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:453:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_enq_bits_uop_is_unique, // @[util.scala:453:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:453:14]
input io_enq_bits_uop_fp_val, // @[util.scala:453:14]
input io_enq_bits_uop_fp_single, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14]
input [64:0] io_enq_bits_data, // @[util.scala:453:14]
input io_deq_ready, // @[util.scala:453:14]
output io_deq_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:453:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:453:14]
output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [64:0] io_deq_bits_data, // @[util.scala:453:14]
output io_deq_bits_predicated, // @[util.scala:453:14]
output io_deq_bits_fflags_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_fflags_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_fflags_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_rvc, // @[util.scala:453:14]
output [39:0] io_deq_bits_fflags_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_fflags_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_fflags_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_fflags_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_fflags_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_fflags_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_fflags_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_sfb, // @[util.scala:453:14]
output [15:0] io_deq_bits_fflags_bits_uop_br_mask, // @[util.scala:453:14]
output [3:0] io_deq_bits_fflags_bits_uop_br_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_fflags_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_fflags_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_fflags_bits_uop_csr_addr, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_rob_idx, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_uop_ldq_idx, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_rxq_idx, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_pdst, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_prs1, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_prs2, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_prs3, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ppred_busy, // @[util.scala:453:14]
output [6:0] io_deq_bits_fflags_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_fflags_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_fflags_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_fflags_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_fflags_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_fflags_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_fflags_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_fflags_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [4:0] io_deq_bits_fflags_bits_flags, // @[util.scala:453:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_br, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14]
input io_brupdate_b2_uop_taken, // @[util.scala:453:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14]
input io_brupdate_b2_uop_exception, // @[util.scala:453:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14]
input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14]
input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14]
input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14]
input io_brupdate_b2_valid, // @[util.scala:453:14]
input io_brupdate_b2_mispredict, // @[util.scala:453:14]
input io_brupdate_b2_taken, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14]
input io_flush, // @[util.scala:453:14]
output io_empty // @[util.scala:453:14]
);
wire [482:0] _ram_ext_R0_data; // @[util.scala:464:20]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7]
wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7]
wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7]
wire [64:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7]
wire io_flush_0 = io_flush; // @[util.scala:448:7]
wire [63:0] io_enq_bits_fflags_bits_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14]
wire [11:0] io_enq_bits_fflags_bits_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14]
wire [19:0] io_enq_bits_fflags_bits_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_enq_bits_fflags_bits_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_enq_bits_fflags_bits_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_enq_bits_fflags_bits_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_enq_bits_fflags_bits_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_enq_bits_fflags_bits_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14]
wire [15:0] io_enq_bits_fflags_bits_uop_br_mask = 16'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_uop_stq_idx = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_uop_ppred = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_enq_bits_fflags_bits_flags = 5'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_enq_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_iw_state = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_mem_size = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[util.scala:448:7]
wire [1:0] io_enq_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[util.scala:448:7]
wire [3:0] io_enq_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7, :453:14]
wire [3:0] io_enq_bits_fflags_bits_uop_br_tag = 4'h0; // @[util.scala:448:7, :453:14]
wire [9:0] io_enq_bits_fflags_bits_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_enq_bits_fflags_bits_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_enq_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14]
wire [39:0] io_enq_bits_fflags_bits_uop_debug_pc = 40'h0; // @[util.scala:448:7, :453:14]
wire [31:0] io_enq_bits_fflags_bits_uop_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [31:0] io_enq_bits_fflags_bits_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_rob_idx = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_enq_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire io_enq_bits_predicated = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_valid = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_rvc = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_br = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_jalr = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_jal = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_sfb = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_edge_inst = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_taken = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_exception = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_bypassable = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_mem_signed = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_fence = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_fencei = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_amo = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_uses_stq = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_is_unique = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_ldst_val = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_frs3_en = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_fp_val = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_fp_single = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[util.scala:448:7]
wire io_enq_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32]
wire _io_enq_ready_T; // @[util.scala:504:19]
wire _io_empty_T_1; // @[util.scala:473:25]
wire _valids_0_T_4 = io_flush_0; // @[util.scala:448:7, :481:83]
wire _valids_1_T_4 = io_flush_0; // @[util.scala:448:7, :481:83]
wire _valids_2_T_4 = io_flush_0; // @[util.scala:448:7, :481:83]
wire _io_deq_valid_T_6 = io_flush_0; // @[util.scala:448:7, :509:122]
wire [1:0] _io_count_T_5; // @[util.scala:529:20]
wire io_enq_ready_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_fflags_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_fflags_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_fflags_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [39:0] io_deq_bits_fflags_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_fflags_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_fflags_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [15:0] io_deq_bits_fflags_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_fflags_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_fflags_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_fflags_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_fflags_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_pdst_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_prs1_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_prs2_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_prs3_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_fflags_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_fflags_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_fflags_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_fflags_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_fflags_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_fflags_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_fflags_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_fflags_bits_flags_0; // @[util.scala:448:7]
wire io_deq_bits_fflags_valid_0; // @[util.scala:448:7]
wire [64:0] io_deq_bits_data_0; // @[util.scala:448:7]
wire io_deq_bits_predicated_0; // @[util.scala:448:7]
wire io_deq_valid_0; // @[util.scala:448:7]
wire io_empty_0; // @[util.scala:448:7]
wire [1:0] io_count; // @[util.scala:448:7]
wire [64:0] out_data = _ram_ext_R0_data[64:0]; // @[util.scala:464:20, :506:17]
wire out_predicated = _ram_ext_R0_data[65]; // @[util.scala:464:20, :506:17]
wire out_fflags_valid = _ram_ext_R0_data[66]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_uopc = _ram_ext_R0_data[73:67]; // @[util.scala:464:20, :506:17]
wire [31:0] out_fflags_bits_uop_inst = _ram_ext_R0_data[105:74]; // @[util.scala:464:20, :506:17]
wire [31:0] out_fflags_bits_uop_debug_inst = _ram_ext_R0_data[137:106]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_rvc = _ram_ext_R0_data[138]; // @[util.scala:464:20, :506:17]
wire [39:0] out_fflags_bits_uop_debug_pc = _ram_ext_R0_data[178:139]; // @[util.scala:464:20, :506:17]
wire [2:0] out_fflags_bits_uop_iq_type = _ram_ext_R0_data[181:179]; // @[util.scala:464:20, :506:17]
wire [9:0] out_fflags_bits_uop_fu_code = _ram_ext_R0_data[191:182]; // @[util.scala:464:20, :506:17]
wire [3:0] out_fflags_bits_uop_ctrl_br_type = _ram_ext_R0_data[195:192]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_ctrl_op1_sel = _ram_ext_R0_data[197:196]; // @[util.scala:464:20, :506:17]
wire [2:0] out_fflags_bits_uop_ctrl_op2_sel = _ram_ext_R0_data[200:198]; // @[util.scala:464:20, :506:17]
wire [2:0] out_fflags_bits_uop_ctrl_imm_sel = _ram_ext_R0_data[203:201]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_uop_ctrl_op_fcn = _ram_ext_R0_data[208:204]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ctrl_fcn_dw = _ram_ext_R0_data[209]; // @[util.scala:464:20, :506:17]
wire [2:0] out_fflags_bits_uop_ctrl_csr_cmd = _ram_ext_R0_data[212:210]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ctrl_is_load = _ram_ext_R0_data[213]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ctrl_is_sta = _ram_ext_R0_data[214]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ctrl_is_std = _ram_ext_R0_data[215]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_iw_state = _ram_ext_R0_data[217:216]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_iw_p1_poisoned = _ram_ext_R0_data[218]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_iw_p2_poisoned = _ram_ext_R0_data[219]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_br = _ram_ext_R0_data[220]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_jalr = _ram_ext_R0_data[221]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_jal = _ram_ext_R0_data[222]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_sfb = _ram_ext_R0_data[223]; // @[util.scala:464:20, :506:17]
wire [15:0] out_fflags_bits_uop_br_mask = _ram_ext_R0_data[239:224]; // @[util.scala:464:20, :506:17]
wire [3:0] out_fflags_bits_uop_br_tag = _ram_ext_R0_data[243:240]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_uop_ftq_idx = _ram_ext_R0_data[248:244]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_edge_inst = _ram_ext_R0_data[249]; // @[util.scala:464:20, :506:17]
wire [5:0] out_fflags_bits_uop_pc_lob = _ram_ext_R0_data[255:250]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_taken = _ram_ext_R0_data[256]; // @[util.scala:464:20, :506:17]
wire [19:0] out_fflags_bits_uop_imm_packed = _ram_ext_R0_data[276:257]; // @[util.scala:464:20, :506:17]
wire [11:0] out_fflags_bits_uop_csr_addr = _ram_ext_R0_data[288:277]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_rob_idx = _ram_ext_R0_data[295:289]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_uop_ldq_idx = _ram_ext_R0_data[300:296]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_uop_stq_idx = _ram_ext_R0_data[305:301]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_rxq_idx = _ram_ext_R0_data[307:306]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_pdst = _ram_ext_R0_data[314:308]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_prs1 = _ram_ext_R0_data[321:315]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_prs2 = _ram_ext_R0_data[328:322]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_prs3 = _ram_ext_R0_data[335:329]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_uop_ppred = _ram_ext_R0_data[340:336]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_prs1_busy = _ram_ext_R0_data[341]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_prs2_busy = _ram_ext_R0_data[342]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_prs3_busy = _ram_ext_R0_data[343]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ppred_busy = _ram_ext_R0_data[344]; // @[util.scala:464:20, :506:17]
wire [6:0] out_fflags_bits_uop_stale_pdst = _ram_ext_R0_data[351:345]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_exception = _ram_ext_R0_data[352]; // @[util.scala:464:20, :506:17]
wire [63:0] out_fflags_bits_uop_exc_cause = _ram_ext_R0_data[416:353]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_bypassable = _ram_ext_R0_data[417]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_uop_mem_cmd = _ram_ext_R0_data[422:418]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_mem_size = _ram_ext_R0_data[424:423]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_mem_signed = _ram_ext_R0_data[425]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_fence = _ram_ext_R0_data[426]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_fencei = _ram_ext_R0_data[427]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_amo = _ram_ext_R0_data[428]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_uses_ldq = _ram_ext_R0_data[429]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_uses_stq = _ram_ext_R0_data[430]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_sys_pc2epc = _ram_ext_R0_data[431]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_is_unique = _ram_ext_R0_data[432]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_flush_on_commit = _ram_ext_R0_data[433]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ldst_is_rs1 = _ram_ext_R0_data[434]; // @[util.scala:464:20, :506:17]
wire [5:0] out_fflags_bits_uop_ldst = _ram_ext_R0_data[440:435]; // @[util.scala:464:20, :506:17]
wire [5:0] out_fflags_bits_uop_lrs1 = _ram_ext_R0_data[446:441]; // @[util.scala:464:20, :506:17]
wire [5:0] out_fflags_bits_uop_lrs2 = _ram_ext_R0_data[452:447]; // @[util.scala:464:20, :506:17]
wire [5:0] out_fflags_bits_uop_lrs3 = _ram_ext_R0_data[458:453]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_ldst_val = _ram_ext_R0_data[459]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_dst_rtype = _ram_ext_R0_data[461:460]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_lrs1_rtype = _ram_ext_R0_data[463:462]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_lrs2_rtype = _ram_ext_R0_data[465:464]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_frs3_en = _ram_ext_R0_data[466]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_fp_val = _ram_ext_R0_data[467]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_fp_single = _ram_ext_R0_data[468]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_xcpt_pf_if = _ram_ext_R0_data[469]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_xcpt_ae_if = _ram_ext_R0_data[470]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_xcpt_ma_if = _ram_ext_R0_data[471]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_bp_debug_if = _ram_ext_R0_data[472]; // @[util.scala:464:20, :506:17]
wire out_fflags_bits_uop_bp_xcpt_if = _ram_ext_R0_data[473]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_debug_fsrc = _ram_ext_R0_data[475:474]; // @[util.scala:464:20, :506:17]
wire [1:0] out_fflags_bits_uop_debug_tsrc = _ram_ext_R0_data[477:476]; // @[util.scala:464:20, :506:17]
wire [4:0] out_fflags_bits_flags = _ram_ext_R0_data[482:478]; // @[util.scala:464:20, :506:17]
reg valids_0; // @[util.scala:465:24]
reg valids_1; // @[util.scala:465:24]
reg valids_2; // @[util.scala:465:24]
reg [6:0] uops_0_uopc; // @[util.scala:466:20]
reg [31:0] uops_0_inst; // @[util.scala:466:20]
reg [31:0] uops_0_debug_inst; // @[util.scala:466:20]
reg uops_0_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_0_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_0_iq_type; // @[util.scala:466:20]
reg [9:0] uops_0_fu_code; // @[util.scala:466:20]
reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_0_ctrl_is_load; // @[util.scala:466:20]
reg uops_0_ctrl_is_sta; // @[util.scala:466:20]
reg uops_0_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_0_iw_state; // @[util.scala:466:20]
reg uops_0_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_0_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_0_is_br; // @[util.scala:466:20]
reg uops_0_is_jalr; // @[util.scala:466:20]
reg uops_0_is_jal; // @[util.scala:466:20]
reg uops_0_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_0_br_mask; // @[util.scala:466:20]
reg [3:0] uops_0_br_tag; // @[util.scala:466:20]
reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20]
reg uops_0_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_0_pc_lob; // @[util.scala:466:20]
reg uops_0_taken; // @[util.scala:466:20]
reg [19:0] uops_0_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_0_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_0_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_0_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_0_pdst; // @[util.scala:466:20]
reg [6:0] uops_0_prs1; // @[util.scala:466:20]
reg [6:0] uops_0_prs2; // @[util.scala:466:20]
reg [6:0] uops_0_prs3; // @[util.scala:466:20]
reg [4:0] uops_0_ppred; // @[util.scala:466:20]
reg uops_0_prs1_busy; // @[util.scala:466:20]
reg uops_0_prs2_busy; // @[util.scala:466:20]
reg uops_0_prs3_busy; // @[util.scala:466:20]
reg uops_0_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20]
reg uops_0_exception; // @[util.scala:466:20]
reg [63:0] uops_0_exc_cause; // @[util.scala:466:20]
reg uops_0_bypassable; // @[util.scala:466:20]
reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_0_mem_size; // @[util.scala:466:20]
reg uops_0_mem_signed; // @[util.scala:466:20]
reg uops_0_is_fence; // @[util.scala:466:20]
reg uops_0_is_fencei; // @[util.scala:466:20]
reg uops_0_is_amo; // @[util.scala:466:20]
reg uops_0_uses_ldq; // @[util.scala:466:20]
reg uops_0_uses_stq; // @[util.scala:466:20]
reg uops_0_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_0_is_unique; // @[util.scala:466:20]
reg uops_0_flush_on_commit; // @[util.scala:466:20]
reg uops_0_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_0_ldst; // @[util.scala:466:20]
reg [5:0] uops_0_lrs1; // @[util.scala:466:20]
reg [5:0] uops_0_lrs2; // @[util.scala:466:20]
reg [5:0] uops_0_lrs3; // @[util.scala:466:20]
reg uops_0_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20]
reg uops_0_frs3_en; // @[util.scala:466:20]
reg uops_0_fp_val; // @[util.scala:466:20]
reg uops_0_fp_single; // @[util.scala:466:20]
reg uops_0_xcpt_pf_if; // @[util.scala:466:20]
reg uops_0_xcpt_ae_if; // @[util.scala:466:20]
reg uops_0_xcpt_ma_if; // @[util.scala:466:20]
reg uops_0_bp_debug_if; // @[util.scala:466:20]
reg uops_0_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_1_uopc; // @[util.scala:466:20]
reg [31:0] uops_1_inst; // @[util.scala:466:20]
reg [31:0] uops_1_debug_inst; // @[util.scala:466:20]
reg uops_1_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_1_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_1_iq_type; // @[util.scala:466:20]
reg [9:0] uops_1_fu_code; // @[util.scala:466:20]
reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_1_ctrl_is_load; // @[util.scala:466:20]
reg uops_1_ctrl_is_sta; // @[util.scala:466:20]
reg uops_1_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_1_iw_state; // @[util.scala:466:20]
reg uops_1_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_1_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_1_is_br; // @[util.scala:466:20]
reg uops_1_is_jalr; // @[util.scala:466:20]
reg uops_1_is_jal; // @[util.scala:466:20]
reg uops_1_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_1_br_mask; // @[util.scala:466:20]
reg [3:0] uops_1_br_tag; // @[util.scala:466:20]
reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20]
reg uops_1_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_1_pc_lob; // @[util.scala:466:20]
reg uops_1_taken; // @[util.scala:466:20]
reg [19:0] uops_1_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_1_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_1_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_1_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_1_pdst; // @[util.scala:466:20]
reg [6:0] uops_1_prs1; // @[util.scala:466:20]
reg [6:0] uops_1_prs2; // @[util.scala:466:20]
reg [6:0] uops_1_prs3; // @[util.scala:466:20]
reg [4:0] uops_1_ppred; // @[util.scala:466:20]
reg uops_1_prs1_busy; // @[util.scala:466:20]
reg uops_1_prs2_busy; // @[util.scala:466:20]
reg uops_1_prs3_busy; // @[util.scala:466:20]
reg uops_1_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20]
reg uops_1_exception; // @[util.scala:466:20]
reg [63:0] uops_1_exc_cause; // @[util.scala:466:20]
reg uops_1_bypassable; // @[util.scala:466:20]
reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_1_mem_size; // @[util.scala:466:20]
reg uops_1_mem_signed; // @[util.scala:466:20]
reg uops_1_is_fence; // @[util.scala:466:20]
reg uops_1_is_fencei; // @[util.scala:466:20]
reg uops_1_is_amo; // @[util.scala:466:20]
reg uops_1_uses_ldq; // @[util.scala:466:20]
reg uops_1_uses_stq; // @[util.scala:466:20]
reg uops_1_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_1_is_unique; // @[util.scala:466:20]
reg uops_1_flush_on_commit; // @[util.scala:466:20]
reg uops_1_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_1_ldst; // @[util.scala:466:20]
reg [5:0] uops_1_lrs1; // @[util.scala:466:20]
reg [5:0] uops_1_lrs2; // @[util.scala:466:20]
reg [5:0] uops_1_lrs3; // @[util.scala:466:20]
reg uops_1_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20]
reg uops_1_frs3_en; // @[util.scala:466:20]
reg uops_1_fp_val; // @[util.scala:466:20]
reg uops_1_fp_single; // @[util.scala:466:20]
reg uops_1_xcpt_pf_if; // @[util.scala:466:20]
reg uops_1_xcpt_ae_if; // @[util.scala:466:20]
reg uops_1_xcpt_ma_if; // @[util.scala:466:20]
reg uops_1_bp_debug_if; // @[util.scala:466:20]
reg uops_1_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_2_uopc; // @[util.scala:466:20]
reg [31:0] uops_2_inst; // @[util.scala:466:20]
reg [31:0] uops_2_debug_inst; // @[util.scala:466:20]
reg uops_2_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_2_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_2_iq_type; // @[util.scala:466:20]
reg [9:0] uops_2_fu_code; // @[util.scala:466:20]
reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_2_ctrl_is_load; // @[util.scala:466:20]
reg uops_2_ctrl_is_sta; // @[util.scala:466:20]
reg uops_2_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_2_iw_state; // @[util.scala:466:20]
reg uops_2_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_2_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_2_is_br; // @[util.scala:466:20]
reg uops_2_is_jalr; // @[util.scala:466:20]
reg uops_2_is_jal; // @[util.scala:466:20]
reg uops_2_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_2_br_mask; // @[util.scala:466:20]
reg [3:0] uops_2_br_tag; // @[util.scala:466:20]
reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20]
reg uops_2_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_2_pc_lob; // @[util.scala:466:20]
reg uops_2_taken; // @[util.scala:466:20]
reg [19:0] uops_2_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_2_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_2_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_2_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_2_pdst; // @[util.scala:466:20]
reg [6:0] uops_2_prs1; // @[util.scala:466:20]
reg [6:0] uops_2_prs2; // @[util.scala:466:20]
reg [6:0] uops_2_prs3; // @[util.scala:466:20]
reg [4:0] uops_2_ppred; // @[util.scala:466:20]
reg uops_2_prs1_busy; // @[util.scala:466:20]
reg uops_2_prs2_busy; // @[util.scala:466:20]
reg uops_2_prs3_busy; // @[util.scala:466:20]
reg uops_2_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20]
reg uops_2_exception; // @[util.scala:466:20]
reg [63:0] uops_2_exc_cause; // @[util.scala:466:20]
reg uops_2_bypassable; // @[util.scala:466:20]
reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_2_mem_size; // @[util.scala:466:20]
reg uops_2_mem_signed; // @[util.scala:466:20]
reg uops_2_is_fence; // @[util.scala:466:20]
reg uops_2_is_fencei; // @[util.scala:466:20]
reg uops_2_is_amo; // @[util.scala:466:20]
reg uops_2_uses_ldq; // @[util.scala:466:20]
reg uops_2_uses_stq; // @[util.scala:466:20]
reg uops_2_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_2_is_unique; // @[util.scala:466:20]
reg uops_2_flush_on_commit; // @[util.scala:466:20]
reg uops_2_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_2_ldst; // @[util.scala:466:20]
reg [5:0] uops_2_lrs1; // @[util.scala:466:20]
reg [5:0] uops_2_lrs2; // @[util.scala:466:20]
reg [5:0] uops_2_lrs3; // @[util.scala:466:20]
reg uops_2_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20]
reg uops_2_frs3_en; // @[util.scala:466:20]
reg uops_2_fp_val; // @[util.scala:466:20]
reg uops_2_fp_single; // @[util.scala:466:20]
reg uops_2_xcpt_pf_if; // @[util.scala:466:20]
reg uops_2_xcpt_ae_if; // @[util.scala:466:20]
reg uops_2_xcpt_ma_if; // @[util.scala:466:20]
reg uops_2_bp_debug_if; // @[util.scala:466:20]
reg uops_2_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20]
reg [1:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [1:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:470:27]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25]
wire full = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq; // @[util.scala:475:24]
wire [3:0] _GEN = {{valids_0}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42]
wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_0; // @[util.scala:476:42]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}]
wire do_deq; // @[util.scala:476:24]
wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}]
wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32]
wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}]
wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}]
wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32]
wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}]
wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}]
wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32]
wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}]
wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire wrap = enq_ptr_value == 2'h2; // @[Counter.scala:61:40, :73:24]
wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7]
wire [2:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [2:0] _value_T = _GEN_1 + 3'h1; // @[Counter.scala:77:24]
wire [1:0] _value_T_1 = _value_T[1:0]; // @[Counter.scala:77:24]
wire wrap_1 = deq_ptr_value == 2'h2; // @[Counter.scala:61:40, :73:24]
wire [2:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [2:0] _value_T_2 = _GEN_2 + 3'h1; // @[Counter.scala:77:24]
wire [1:0] _value_T_3 = _value_T_2[1:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19]
wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17]
wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17]
wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17]
wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17]
wire out_uop_ctrl_is_load; // @[util.scala:506:17]
wire out_uop_ctrl_is_sta; // @[util.scala:506:17]
wire out_uop_ctrl_is_std; // @[util.scala:506:17]
wire [6:0] out_uop_uopc; // @[util.scala:506:17]
wire [31:0] out_uop_inst; // @[util.scala:506:17]
wire [31:0] out_uop_debug_inst; // @[util.scala:506:17]
wire out_uop_is_rvc; // @[util.scala:506:17]
wire [39:0] out_uop_debug_pc; // @[util.scala:506:17]
wire [2:0] out_uop_iq_type; // @[util.scala:506:17]
wire [9:0] out_uop_fu_code; // @[util.scala:506:17]
wire [1:0] out_uop_iw_state; // @[util.scala:506:17]
wire out_uop_iw_p1_poisoned; // @[util.scala:506:17]
wire out_uop_iw_p2_poisoned; // @[util.scala:506:17]
wire out_uop_is_br; // @[util.scala:506:17]
wire out_uop_is_jalr; // @[util.scala:506:17]
wire out_uop_is_jal; // @[util.scala:506:17]
wire out_uop_is_sfb; // @[util.scala:506:17]
wire [15:0] out_uop_br_mask; // @[util.scala:506:17]
wire [3:0] out_uop_br_tag; // @[util.scala:506:17]
wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17]
wire out_uop_edge_inst; // @[util.scala:506:17]
wire [5:0] out_uop_pc_lob; // @[util.scala:506:17]
wire out_uop_taken; // @[util.scala:506:17]
wire [19:0] out_uop_imm_packed; // @[util.scala:506:17]
wire [11:0] out_uop_csr_addr; // @[util.scala:506:17]
wire [6:0] out_uop_rob_idx; // @[util.scala:506:17]
wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17]
wire [4:0] out_uop_stq_idx; // @[util.scala:506:17]
wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17]
wire [6:0] out_uop_pdst; // @[util.scala:506:17]
wire [6:0] out_uop_prs1; // @[util.scala:506:17]
wire [6:0] out_uop_prs2; // @[util.scala:506:17]
wire [6:0] out_uop_prs3; // @[util.scala:506:17]
wire [4:0] out_uop_ppred; // @[util.scala:506:17]
wire out_uop_prs1_busy; // @[util.scala:506:17]
wire out_uop_prs2_busy; // @[util.scala:506:17]
wire out_uop_prs3_busy; // @[util.scala:506:17]
wire out_uop_ppred_busy; // @[util.scala:506:17]
wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17]
wire out_uop_exception; // @[util.scala:506:17]
wire [63:0] out_uop_exc_cause; // @[util.scala:506:17]
wire out_uop_bypassable; // @[util.scala:506:17]
wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17]
wire [1:0] out_uop_mem_size; // @[util.scala:506:17]
wire out_uop_mem_signed; // @[util.scala:506:17]
wire out_uop_is_fence; // @[util.scala:506:17]
wire out_uop_is_fencei; // @[util.scala:506:17]
wire out_uop_is_amo; // @[util.scala:506:17]
wire out_uop_uses_ldq; // @[util.scala:506:17]
wire out_uop_uses_stq; // @[util.scala:506:17]
wire out_uop_is_sys_pc2epc; // @[util.scala:506:17]
wire out_uop_is_unique; // @[util.scala:506:17]
wire out_uop_flush_on_commit; // @[util.scala:506:17]
wire out_uop_ldst_is_rs1; // @[util.scala:506:17]
wire [5:0] out_uop_ldst; // @[util.scala:506:17]
wire [5:0] out_uop_lrs1; // @[util.scala:506:17]
wire [5:0] out_uop_lrs2; // @[util.scala:506:17]
wire [5:0] out_uop_lrs3; // @[util.scala:506:17]
wire out_uop_ldst_val; // @[util.scala:506:17]
wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17]
wire out_uop_frs3_en; // @[util.scala:506:17]
wire out_uop_fp_val; // @[util.scala:506:17]
wire out_uop_fp_single; // @[util.scala:506:17]
wire out_uop_xcpt_pf_if; // @[util.scala:506:17]
wire out_uop_xcpt_ae_if; // @[util.scala:506:17]
wire out_uop_xcpt_ma_if; // @[util.scala:506:17]
wire out_uop_bp_debug_if; // @[util.scala:506:17]
wire out_uop_bp_xcpt_if; // @[util.scala:506:17]
wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17]
wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17]
wire [3:0][6:0] _GEN_3 = {{uops_0_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19]
assign out_uop_uopc = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][31:0] _GEN_4 = {{uops_0_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][31:0] _GEN_5 = {{uops_0_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_6 = {{uops_0_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_rvc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][39:0] _GEN_7 = {{uops_0_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_pc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_8 = {{uops_0_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_iq_type = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][9:0] _GEN_9 = {{uops_0_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19]
assign out_uop_fu_code = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_10 = {{uops_0_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_br_type = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_11 = {{uops_0_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op1_sel = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_12 = {{uops_0_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op2_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_13 = {{uops_0_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_imm_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_14 = {{uops_0_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op_fcn = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_15 = {{uops_0_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_fcn_dw = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_16 = {{uops_0_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_csr_cmd = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_17 = {{uops_0_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_load = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_18 = {{uops_0_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_sta = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_19 = {{uops_0_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_std = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_20 = {{uops_0_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_state = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_21 = {{uops_0_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p1_poisoned = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_22 = {{uops_0_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p2_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_23 = {{uops_0_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_br = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_24 = {{uops_0_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jalr = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_25 = {{uops_0_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jal = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_26 = {{uops_0_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sfb = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][15:0] _GEN_27 = {{uops_0_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_mask = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_28 = {{uops_0_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_tag = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_29 = {{uops_0_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ftq_idx = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_30 = {{uops_0_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_edge_inst = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_31 = {{uops_0_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19]
assign out_uop_pc_lob = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_32 = {{uops_0_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19]
assign out_uop_taken = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][19:0] _GEN_33 = {{uops_0_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19]
assign out_uop_imm_packed = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][11:0] _GEN_34 = {{uops_0_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19]
assign out_uop_csr_addr = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_35 = {{uops_0_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rob_idx = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_36 = {{uops_0_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldq_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_37 = {{uops_0_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_stq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_38 = {{uops_0_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rxq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_39 = {{uops_0_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_pdst = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_40 = {{uops_0_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1 = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_41 = {{uops_0_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_42 = {{uops_0_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_43 = {{uops_0_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_44 = {{uops_0_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1_busy = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_45 = {{uops_0_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_46 = {{uops_0_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_47 = {{uops_0_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_48 = {{uops_0_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_stale_pdst = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_49 = {{uops_0_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19]
assign out_uop_exception = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][63:0] _GEN_50 = {{uops_0_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19]
assign out_uop_exc_cause = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_51 = {{uops_0_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19]
assign out_uop_bypassable = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_52 = {{uops_0_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_cmd = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_53 = {{uops_0_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_size = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_54 = {{uops_0_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_signed = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_55 = {{uops_0_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fence = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_56 = {{uops_0_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fencei = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_57 = {{uops_0_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_amo = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_58 = {{uops_0_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_ldq = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_59 = {{uops_0_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_stq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_60 = {{uops_0_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sys_pc2epc = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_61 = {{uops_0_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_unique = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_62 = {{uops_0_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19]
assign out_uop_flush_on_commit = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_63 = {{uops_0_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_is_rs1 = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_64 = {{uops_0_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_65 = {{uops_0_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1 = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_66 = {{uops_0_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_67 = {{uops_0_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs3 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_68 = {{uops_0_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_val = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_69 = {{uops_0_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_dst_rtype = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_70 = {{uops_0_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_71 = {{uops_0_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_72 = {{uops_0_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19]
assign out_uop_frs3_en = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_73 = {{uops_0_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_val = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_74 = {{uops_0_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_single = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_75 = {{uops_0_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_pf_if = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_76 = {{uops_0_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ae_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_77 = {{uops_0_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ma_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_78 = {{uops_0_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_debug_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_79 = {{uops_0_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_xcpt_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_80 = {{uops_0_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_fsrc = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_81 = {{uops_0_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_tsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30]
wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:476:42, :509:{30,40}]
wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17]
wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}]
wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68]
wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}]
wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}]
wire _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}]
wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
wire [15:0] _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17]
assign io_deq_valid_0 = io_empty_0 ? io_enq_valid_0 : _io_deq_valid_T_8; // @[util.scala:448:7, :509:{27,108}, :515:21, :516:20]
assign io_deq_bits_uop_uopc_0 = io_empty_0 ? io_enq_bits_uop_uopc_0 : out_uop_uopc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_inst_0 = io_empty_0 ? io_enq_bits_uop_inst_0 : out_uop_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_debug_inst_0 = io_empty_0 ? io_enq_bits_uop_debug_inst_0 : out_uop_debug_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_rvc_0 = io_empty_0 ? io_enq_bits_uop_is_rvc_0 : out_uop_is_rvc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_debug_pc_0 = io_empty_0 ? io_enq_bits_uop_debug_pc_0 : out_uop_debug_pc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_iq_type_0 = io_empty_0 ? io_enq_bits_uop_iq_type_0 : out_uop_iq_type; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_fu_code_0 = io_empty_0 ? io_enq_bits_uop_fu_code_0 : out_uop_fu_code; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_br_type_0 = io_empty_0 ? io_enq_bits_uop_ctrl_br_type_0 : out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_op1_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op1_sel_0 : out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_op2_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op2_sel_0 : out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_imm_sel_0 = io_empty_0 ? io_enq_bits_uop_ctrl_imm_sel_0 : out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_op_fcn_0 = io_empty_0 ? io_enq_bits_uop_ctrl_op_fcn_0 : out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_fcn_dw_0 = io_empty_0 ? io_enq_bits_uop_ctrl_fcn_dw_0 : out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_csr_cmd_0 = io_empty_0 ? io_enq_bits_uop_ctrl_csr_cmd_0 : out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_is_load_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_load_0 : out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_is_sta_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_sta_0 : out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ctrl_is_std_0 = io_empty_0 ? io_enq_bits_uop_ctrl_is_std_0 : out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_iw_state_0 = io_empty_0 ? io_enq_bits_uop_iw_state_0 : out_uop_iw_state; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_iw_p1_poisoned_0 = io_empty_0 ? io_enq_bits_uop_iw_p1_poisoned_0 : out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_iw_p2_poisoned_0 = io_empty_0 ? io_enq_bits_uop_iw_p2_poisoned_0 : out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_br_0 = io_empty_0 ? io_enq_bits_uop_is_br_0 : out_uop_is_br; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_jalr_0 = io_empty_0 ? io_enq_bits_uop_is_jalr_0 : out_uop_is_jalr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_jal_0 = io_empty_0 ? io_enq_bits_uop_is_jal_0 : out_uop_is_jal; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_sfb_0 = io_empty_0 ? io_enq_bits_uop_is_sfb_0 : out_uop_is_sfb; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_br_tag_0 = io_empty_0 ? io_enq_bits_uop_br_tag_0 : out_uop_br_tag; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ftq_idx_0 = io_empty_0 ? io_enq_bits_uop_ftq_idx_0 : out_uop_ftq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_edge_inst_0 = io_empty_0 ? io_enq_bits_uop_edge_inst_0 : out_uop_edge_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_pc_lob_0 = io_empty_0 ? io_enq_bits_uop_pc_lob_0 : out_uop_pc_lob; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_taken_0 = io_empty_0 ? io_enq_bits_uop_taken_0 : out_uop_taken; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_imm_packed_0 = io_empty_0 ? io_enq_bits_uop_imm_packed_0 : out_uop_imm_packed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_csr_addr_0 = io_empty_0 ? io_enq_bits_uop_csr_addr_0 : out_uop_csr_addr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_rob_idx_0 = io_empty_0 ? io_enq_bits_uop_rob_idx_0 : out_uop_rob_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ldq_idx_0 = io_empty_0 ? io_enq_bits_uop_ldq_idx_0 : out_uop_ldq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_stq_idx_0 = io_empty_0 ? io_enq_bits_uop_stq_idx_0 : out_uop_stq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_rxq_idx_0 = io_empty_0 ? io_enq_bits_uop_rxq_idx_0 : out_uop_rxq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_pdst_0 = io_empty_0 ? io_enq_bits_uop_pdst_0 : out_uop_pdst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_prs1_0 = io_empty_0 ? io_enq_bits_uop_prs1_0 : out_uop_prs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_prs2_0 = io_empty_0 ? io_enq_bits_uop_prs2_0 : out_uop_prs2; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_prs3_0 = io_empty_0 ? io_enq_bits_uop_prs3_0 : out_uop_prs3; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ppred_0 = io_empty_0 ? io_enq_bits_uop_ppred_0 : out_uop_ppred; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_prs1_busy_0 = io_empty_0 ? io_enq_bits_uop_prs1_busy_0 : out_uop_prs1_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_prs2_busy_0 = io_empty_0 ? io_enq_bits_uop_prs2_busy_0 : out_uop_prs2_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_prs3_busy_0 = io_empty_0 ? io_enq_bits_uop_prs3_busy_0 : out_uop_prs3_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ppred_busy_0 = io_empty_0 ? io_enq_bits_uop_ppred_busy_0 : out_uop_ppred_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_stale_pdst_0 = io_empty_0 ? io_enq_bits_uop_stale_pdst_0 : out_uop_stale_pdst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_exception_0 = io_empty_0 ? io_enq_bits_uop_exception_0 : out_uop_exception; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_exc_cause_0 = io_empty_0 ? io_enq_bits_uop_exc_cause_0 : out_uop_exc_cause; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_bypassable_0 = io_empty_0 ? io_enq_bits_uop_bypassable_0 : out_uop_bypassable; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_mem_cmd_0 = io_empty_0 ? io_enq_bits_uop_mem_cmd_0 : out_uop_mem_cmd; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_mem_size_0 = io_empty_0 ? io_enq_bits_uop_mem_size_0 : out_uop_mem_size; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_mem_signed_0 = io_empty_0 ? io_enq_bits_uop_mem_signed_0 : out_uop_mem_signed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_fence_0 = io_empty_0 ? io_enq_bits_uop_is_fence_0 : out_uop_is_fence; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_fencei_0 = io_empty_0 ? io_enq_bits_uop_is_fencei_0 : out_uop_is_fencei; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_amo_0 = io_empty_0 ? io_enq_bits_uop_is_amo_0 : out_uop_is_amo; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_uses_ldq_0 = io_empty_0 ? io_enq_bits_uop_uses_ldq_0 : out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_uses_stq_0 = io_empty_0 ? io_enq_bits_uop_uses_stq_0 : out_uop_uses_stq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = io_empty_0 ? io_enq_bits_uop_is_sys_pc2epc_0 : out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_is_unique_0 = io_empty_0 ? io_enq_bits_uop_is_unique_0 : out_uop_is_unique; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_flush_on_commit_0 = io_empty_0 ? io_enq_bits_uop_flush_on_commit_0 : out_uop_flush_on_commit; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = io_empty_0 ? io_enq_bits_uop_ldst_is_rs1_0 : out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ldst_0 = io_empty_0 ? io_enq_bits_uop_ldst_0 : out_uop_ldst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_lrs1_0 = io_empty_0 ? io_enq_bits_uop_lrs1_0 : out_uop_lrs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_lrs2_0 = io_empty_0 ? io_enq_bits_uop_lrs2_0 : out_uop_lrs2; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_lrs3_0 = io_empty_0 ? io_enq_bits_uop_lrs3_0 : out_uop_lrs3; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_ldst_val_0 = io_empty_0 ? io_enq_bits_uop_ldst_val_0 : out_uop_ldst_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_dst_rtype_0 = io_empty_0 ? io_enq_bits_uop_dst_rtype_0 : out_uop_dst_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_lrs1_rtype_0 = io_empty_0 ? io_enq_bits_uop_lrs1_rtype_0 : out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_lrs2_rtype_0 = io_empty_0 ? io_enq_bits_uop_lrs2_rtype_0 : out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_frs3_en_0 = io_empty_0 ? io_enq_bits_uop_frs3_en_0 : out_uop_frs3_en; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_fp_val_0 = io_empty_0 ? io_enq_bits_uop_fp_val_0 : out_uop_fp_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_fp_single_0 = io_empty_0 ? io_enq_bits_uop_fp_single_0 : out_uop_fp_single; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_pf_if_0 : out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_ae_if_0 : out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = io_empty_0 ? io_enq_bits_uop_xcpt_ma_if_0 : out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_bp_debug_if_0 = io_empty_0 ? io_enq_bits_uop_bp_debug_if_0 : out_uop_bp_debug_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = io_empty_0 ? io_enq_bits_uop_bp_xcpt_if_0 : out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_debug_fsrc_0 = io_empty_0 ? io_enq_bits_uop_debug_fsrc_0 : out_uop_debug_fsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_uop_debug_tsrc_0 = io_empty_0 ? io_enq_bits_uop_debug_tsrc_0 : out_uop_debug_tsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_data_0 = io_empty_0 ? io_enq_bits_data_0 : out_data; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_predicated_0 = ~io_empty_0 & out_predicated; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_valid_0 = ~io_empty_0 & out_fflags_valid; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_uopc_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_uopc; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_inst_0 = io_empty_0 ? 32'h0 : out_fflags_bits_uop_inst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_debug_inst_0 = io_empty_0 ? 32'h0 : out_fflags_bits_uop_debug_inst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_rvc_0 = ~io_empty_0 & out_fflags_bits_uop_is_rvc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_debug_pc_0 = io_empty_0 ? 40'h0 : out_fflags_bits_uop_debug_pc; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_iq_type_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_iq_type; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_fu_code_0 = io_empty_0 ? 10'h0 : out_fflags_bits_uop_fu_code; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_br_type_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_ctrl_br_type; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_op2_sel; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_imm_sel; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_ctrl_op_fcn; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_empty_0 ? 3'h0 : out_fflags_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_is_load_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_load; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_is_sta_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ctrl_is_std_0 = ~io_empty_0 & out_fflags_bits_uop_ctrl_is_std; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_iw_state_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_iw_state; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0 = ~io_empty_0 & out_fflags_bits_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0 = ~io_empty_0 & out_fflags_bits_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_br_0 = ~io_empty_0 & out_fflags_bits_uop_is_br; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_jalr_0 = ~io_empty_0 & out_fflags_bits_uop_is_jalr; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_jal_0 = ~io_empty_0 & out_fflags_bits_uop_is_jal; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_sfb_0 = ~io_empty_0 & out_fflags_bits_uop_is_sfb; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_br_mask_0 = io_empty_0 ? 16'h0 : out_fflags_bits_uop_br_mask; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_br_tag_0 = io_empty_0 ? 4'h0 : out_fflags_bits_uop_br_tag; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ftq_idx_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_ftq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_edge_inst_0 = ~io_empty_0 & out_fflags_bits_uop_edge_inst; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_pc_lob_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_pc_lob; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_taken_0 = ~io_empty_0 & out_fflags_bits_uop_taken; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_imm_packed_0 = io_empty_0 ? 20'h0 : out_fflags_bits_uop_imm_packed; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_csr_addr_0 = io_empty_0 ? 12'h0 : out_fflags_bits_uop_csr_addr; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_rob_idx_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_rob_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ldq_idx_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_ldq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_stq_idx_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_stq_idx; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_rxq_idx_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_rxq_idx; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_pdst_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_pdst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_prs1_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_prs1; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_prs2_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_prs2; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_prs3_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_prs3; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ppred_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_ppred; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_prs1_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs1_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_prs2_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs2_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_prs3_busy_0 = ~io_empty_0 & out_fflags_bits_uop_prs3_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ppred_busy_0 = ~io_empty_0 & out_fflags_bits_uop_ppred_busy; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_stale_pdst_0 = io_empty_0 ? 7'h0 : out_fflags_bits_uop_stale_pdst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_exception_0 = ~io_empty_0 & out_fflags_bits_uop_exception; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_exc_cause_0 = io_empty_0 ? 64'h0 : out_fflags_bits_uop_exc_cause; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_bypassable_0 = ~io_empty_0 & out_fflags_bits_uop_bypassable; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_mem_cmd_0 = io_empty_0 ? 5'h0 : out_fflags_bits_uop_mem_cmd; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_mem_size_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_mem_size; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_mem_signed_0 = ~io_empty_0 & out_fflags_bits_uop_mem_signed; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_fence_0 = ~io_empty_0 & out_fflags_bits_uop_is_fence; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_fencei_0 = ~io_empty_0 & out_fflags_bits_uop_is_fencei; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_amo_0 = ~io_empty_0 & out_fflags_bits_uop_is_amo; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_uses_ldq_0 = ~io_empty_0 & out_fflags_bits_uop_uses_ldq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_uses_stq_0 = ~io_empty_0 & out_fflags_bits_uop_uses_stq; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0 = ~io_empty_0 & out_fflags_bits_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_is_unique_0 = ~io_empty_0 & out_fflags_bits_uop_is_unique; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_flush_on_commit_0 = ~io_empty_0 & out_fflags_bits_uop_flush_on_commit; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ldst_is_rs1_0 = ~io_empty_0 & out_fflags_bits_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ldst_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_ldst; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_lrs1_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs1; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_lrs2_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs2; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_lrs3_0 = io_empty_0 ? 6'h0 : out_fflags_bits_uop_lrs3; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_ldst_val_0 = ~io_empty_0 & out_fflags_bits_uop_ldst_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_dst_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_dst_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_lrs1_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_lrs1_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_lrs2_rtype_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_lrs2_rtype; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_frs3_en_0 = ~io_empty_0 & out_fflags_bits_uop_frs3_en; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_fp_val_0 = ~io_empty_0 & out_fflags_bits_uop_fp_val; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_fp_single_0 = ~io_empty_0 & out_fflags_bits_uop_fp_single; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_xcpt_pf_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_xcpt_ae_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_xcpt_ma_if_0 = ~io_empty_0 & out_fflags_bits_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_bp_debug_if_0 = ~io_empty_0 & out_fflags_bits_uop_bp_debug_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_bp_xcpt_if_0 = ~io_empty_0 & out_fflags_bits_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_debug_fsrc_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_debug_fsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_uop_debug_tsrc_0 = io_empty_0 ? 2'h0 : out_fflags_bits_uop_debug_tsrc; // @[util.scala:448:7, :506:17, :510:27, :515:21, :517:19]
assign io_deq_bits_fflags_bits_flags_0 = io_empty_0 ? 5'h0 : out_fflags_bits_flags; // @[util.scala:448:7, :453:14, :506:17, :510:27, :515:21, :517:19]
wire [15:0] _io_deq_bits_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
wire [15:0] _io_deq_bits_uop_br_mask_T_3 = io_enq_bits_uop_br_mask_0 & _io_deq_bits_uop_br_mask_T_2; // @[util.scala:85:{25,27}, :448:7]
assign io_deq_bits_uop_br_mask_0 = io_empty_0 ? _io_deq_bits_uop_br_mask_T_3 : _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7, :511:27, :515:21, :518:31]
assign do_deq = ~io_empty_0 & _do_deq_T_3; // @[util.scala:448:7, :476:{24,66}, :510:27, :515:21, :517:19, :520:14]
assign do_enq = ~(io_empty_0 & io_deq_ready_0) & _do_enq_T; // @[Decoupled.scala:51:35]
wire [2:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24]
wire [1:0] ptr_diff = _ptr_diff_T[1:0]; // @[util.scala:524:40]
wire [1:0] _io_count_T = {2{maybe_full}}; // @[util.scala:470:27, :530:24]
wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40]
wire [2:0] _io_count_T_2 = {1'h0, ptr_diff} + 3'h3; // @[util.scala:524:40, :533:40]
wire [1:0] _io_count_T_3 = _io_count_T_2[1:0]; // @[util.scala:533:40]
wire [1:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:524:40, :532:{24,39}, :533:40]
assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:472:33, :529:20, :530:24, :532:24]
assign io_count = _io_count_T_5; // @[util.scala:448:7, :529:20]
wire _GEN_82 = enq_ptr_value == 2'h0; // @[Counter.scala:61:40]
wire _GEN_83 = do_enq & _GEN_82; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_84 = enq_ptr_value == 2'h1; // @[Counter.scala:61:40]
wire _GEN_85 = do_enq & _GEN_84; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_86 = do_enq & wrap; // @[Counter.scala:73:24]
always @(posedge clock) begin // @[util.scala:448:7]
if (reset) begin // @[util.scala:448:7]
valids_0 <= 1'h0; // @[util.scala:465:24]
valids_1 <= 1'h0; // @[util.scala:465:24]
valids_2 <= 1'h0; // @[util.scala:465:24]
enq_ptr_value <= 2'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 2'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:470:27]
end
else begin // @[util.scala:448:7]
valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_83 | _valids_0_T_6); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_85 | _valids_1_T_6); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & wrap_1) & (_GEN_86 | _valids_2_T_6); // @[Counter.scala:73:24]
if (do_enq) // @[util.scala:475:24]
enq_ptr_value <= wrap ? 2'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (do_deq) // @[util.scala:476:24]
deq_ptr_value <= wrap_1 ? 2'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16]
maybe_full <= do_enq; // @[util.scala:470:27, :475:24]
end
if (_GEN_83) begin // @[util.scala:481:16, :487:17, :489:33]
uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_82) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_0) // @[util.scala:465:24]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_85) begin // @[util.scala:481:16, :487:17, :489:33]
uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_84) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_1) // @[util.scala:465:24]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33]
uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & wrap) // @[Counter.scala:73:24]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_2) // @[util.scala:465:24]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20]
always @(posedge)
ram_3x483 ram_ext ( // @[util.scala:464:20]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:475:24]
.W0_clk (clock),
.W0_data ({418'h0, io_enq_bits_data_0}) // @[util.scala:448:7, :464:20]
); // @[util.scala:464:20]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7]
assign io_deq_bits_predicated = io_deq_bits_predicated_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_valid = io_deq_bits_fflags_valid_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_uopc = io_deq_bits_fflags_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_inst = io_deq_bits_fflags_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_debug_inst = io_deq_bits_fflags_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_rvc = io_deq_bits_fflags_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_debug_pc = io_deq_bits_fflags_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_iq_type = io_deq_bits_fflags_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_fu_code = io_deq_bits_fflags_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_br_type = io_deq_bits_fflags_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_op1_sel = io_deq_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_op2_sel = io_deq_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_imm_sel = io_deq_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_op_fcn = io_deq_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_fcn_dw = io_deq_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_csr_cmd = io_deq_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_is_load = io_deq_bits_fflags_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_is_sta = io_deq_bits_fflags_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ctrl_is_std = io_deq_bits_fflags_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_iw_state = io_deq_bits_fflags_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_iw_p1_poisoned = io_deq_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_iw_p2_poisoned = io_deq_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_br = io_deq_bits_fflags_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_jalr = io_deq_bits_fflags_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_jal = io_deq_bits_fflags_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_sfb = io_deq_bits_fflags_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_br_mask = io_deq_bits_fflags_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_br_tag = io_deq_bits_fflags_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ftq_idx = io_deq_bits_fflags_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_edge_inst = io_deq_bits_fflags_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_pc_lob = io_deq_bits_fflags_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_taken = io_deq_bits_fflags_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_imm_packed = io_deq_bits_fflags_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_csr_addr = io_deq_bits_fflags_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_rob_idx = io_deq_bits_fflags_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ldq_idx = io_deq_bits_fflags_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_stq_idx = io_deq_bits_fflags_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_rxq_idx = io_deq_bits_fflags_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_pdst = io_deq_bits_fflags_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_prs1 = io_deq_bits_fflags_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_prs2 = io_deq_bits_fflags_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_prs3 = io_deq_bits_fflags_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ppred = io_deq_bits_fflags_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_prs1_busy = io_deq_bits_fflags_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_prs2_busy = io_deq_bits_fflags_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_prs3_busy = io_deq_bits_fflags_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ppred_busy = io_deq_bits_fflags_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_stale_pdst = io_deq_bits_fflags_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_exception = io_deq_bits_fflags_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_exc_cause = io_deq_bits_fflags_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_bypassable = io_deq_bits_fflags_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_mem_cmd = io_deq_bits_fflags_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_mem_size = io_deq_bits_fflags_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_mem_signed = io_deq_bits_fflags_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_fence = io_deq_bits_fflags_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_fencei = io_deq_bits_fflags_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_amo = io_deq_bits_fflags_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_uses_ldq = io_deq_bits_fflags_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_uses_stq = io_deq_bits_fflags_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_sys_pc2epc = io_deq_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_is_unique = io_deq_bits_fflags_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_flush_on_commit = io_deq_bits_fflags_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ldst_is_rs1 = io_deq_bits_fflags_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ldst = io_deq_bits_fflags_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_lrs1 = io_deq_bits_fflags_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_lrs2 = io_deq_bits_fflags_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_lrs3 = io_deq_bits_fflags_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_ldst_val = io_deq_bits_fflags_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_dst_rtype = io_deq_bits_fflags_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_lrs1_rtype = io_deq_bits_fflags_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_lrs2_rtype = io_deq_bits_fflags_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_frs3_en = io_deq_bits_fflags_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_fp_val = io_deq_bits_fflags_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_fp_single = io_deq_bits_fflags_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_xcpt_pf_if = io_deq_bits_fflags_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_xcpt_ae_if = io_deq_bits_fflags_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_xcpt_ma_if = io_deq_bits_fflags_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_bp_debug_if = io_deq_bits_fflags_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_bp_xcpt_if = io_deq_bits_fflags_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_debug_fsrc = io_deq_bits_fflags_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_uop_debug_tsrc = io_deq_bits_fflags_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_fflags_bits_flags = io_deq_bits_fflags_bits_flags_0; // @[util.scala:448:7]
assign io_empty = io_empty_0; // @[util.scala:448:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_110( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_186 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_14( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ppred = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [7:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? 4'h0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_87( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyRoCC.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.experimental.IntParam
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.rocket.{
MStatus, HellaCacheIO, TLBPTWIO, CanHavePTW, CanHavePTWModule,
SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ
}
import freechips.rocketchip.tilelink.{
TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters
}
import freechips.rocketchip.util.InOrderArbiter
case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil)
class RoCCInstruction extends Bundle {
val funct = Bits(7.W)
val rs2 = Bits(5.W)
val rs1 = Bits(5.W)
val xd = Bool()
val xs1 = Bool()
val xs2 = Bool()
val rd = Bits(5.W)
val opcode = Bits(7.W)
}
class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) {
val inst = new RoCCInstruction
val rs1 = Bits(xLen.W)
val rs2 = Bits(xLen.W)
val status = new MStatus
}
class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
val rd = Bits(5.W)
val data = Bits(xLen.W)
}
class RoCCCoreIO(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) {
val cmd = Flipped(Decoupled(new RoCCCommand))
val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO
val busy = Output(Bool())
val interrupt = Output(Bool())
val exception = Input(Bool())
val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO))
}
class RoCCIO(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIO(nRoCCCSRs)(p) {
val ptw = Vec(nPTWPorts, new TLBPTWIO)
val fpu_req = Decoupled(new FPInput)
val fpu_resp = Flipped(Decoupled(new FPResult))
}
/** Base classes for Diplomatic TL2 RoCC units **/
abstract class LazyRoCC(
val opcodes: OpcodeSet,
val nPTWPorts: Int = 0,
val usesFPU: Boolean = false,
val roccCSRs: Seq[CustomCSR] = Nil
)(implicit p: Parameters) extends LazyModule {
val module: LazyRoCCModuleImp
require(roccCSRs.map(_.id).toSet.size == roccCSRs.size)
val atlNode: TLNode = TLIdentityNode()
val tlNode: TLNode = TLIdentityNode()
val stlNode: TLNode = TLIdentityNode()
}
class LazyRoCCModuleImp(outer: LazyRoCC) extends LazyModuleImp(outer) {
val io = IO(new RoCCIO(outer.nPTWPorts, outer.roccCSRs.size))
io := DontCare
}
/** Mixins for including RoCC **/
trait HasLazyRoCC extends CanHavePTW { this: BaseTile =>
val roccs = p(BuildRoCC).map(_(p))
val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs
require(roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size,
"LazyRoCC instantiations require overlapping CSRs")
roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl }
roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl }
roccs.map(_.stlNode).foreach { stl => stl :*= tlSlaveXbar.node }
nPTWPorts += roccs.map(_.nPTWPorts).sum
nDCachePorts += roccs.size
}
trait HasLazyRoCCModule extends CanHavePTWModule
with HasCoreParameters { this: RocketTileModuleImp =>
val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) {
val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size))
val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p))
outer.roccs.zipWithIndex.foreach { case (rocc, i) =>
rocc.module.io.ptw ++=: ptwPorts
rocc.module.io.cmd <> cmdRouter.io.out(i)
val dcIF = Module(new SimpleHellaCacheIF()(outer.p))
dcIF.io.requestor <> rocc.module.io.mem
dcachePorts += dcIF.io.cache
respArb.io.in(i) <> Queue(rocc.module.io.resp)
}
(Some(respArb), Some(cmdRouter))
} else {
(None, None)
}
val roccCSRIOs = outer.roccs.map(_.module.io.csrs)
}
class AccumulatorExample(opcodes: OpcodeSet, val n: Int = 4)(implicit p: Parameters) extends LazyRoCC(opcodes) {
override lazy val module = new AccumulatorExampleModuleImp(this)
}
class AccumulatorExampleModuleImp(outer: AccumulatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
with HasCoreParameters {
val regfile = Mem(outer.n, UInt(xLen.W))
val busy = RegInit(VecInit(Seq.fill(outer.n){false.B}))
val cmd = Queue(io.cmd)
val funct = cmd.bits.inst.funct
val addr = cmd.bits.rs2(log2Up(outer.n)-1,0)
val doWrite = funct === 0.U
val doRead = funct === 1.U
val doLoad = funct === 2.U
val doAccum = funct === 3.U
val memRespTag = io.mem.resp.bits.tag(log2Up(outer.n)-1,0)
// datapath
val addend = cmd.bits.rs1
val accum = regfile(addr)
val wdata = Mux(doWrite, addend, accum + addend)
when (cmd.fire && (doWrite || doAccum)) {
regfile(addr) := wdata
}
when (io.mem.resp.valid) {
regfile(memRespTag) := io.mem.resp.bits.data
busy(memRespTag) := false.B
}
// control
when (io.mem.req.fire) {
busy(addr) := true.B
}
val doResp = cmd.bits.inst.xd
val stallReg = busy(addr)
val stallLoad = doLoad && !io.mem.req.ready
val stallResp = doResp && !io.resp.ready
cmd.ready := !stallReg && !stallLoad && !stallResp
// command resolved if no stalls AND not issuing a load that will need a request
// PROC RESPONSE INTERFACE
io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
// valid response if valid command, need a response, and no stalls
io.resp.bits.rd := cmd.bits.inst.rd
// Must respond with the appropriate tag or undefined behavior
io.resp.bits.data := accum
// Semantics is to always send out prior accumulator register value
io.busy := cmd.valid || busy.reduce(_||_)
// Be busy when have pending memory requests or committed possibility of pending requests
io.interrupt := false.B
// Set this true to trigger an interrupt on the processor (please refer to supervisor documentation)
// MEMORY REQUEST INTERFACE
io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
io.mem.req.bits.addr := addend
io.mem.req.bits.tag := addr
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.size := log2Ceil(8).U
io.mem.req.bits.signed := false.B
io.mem.req.bits.data := 0.U // we're not performing any stores...
io.mem.req.bits.phys := false.B
io.mem.req.bits.dprv := cmd.bits.status.dprv
io.mem.req.bits.dv := cmd.bits.status.dv
io.mem.req.bits.no_resp := false.B
}
class TranslatorExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes, nPTWPorts = 1) {
override lazy val module = new TranslatorExampleModuleImp(this)
}
class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
with HasCoreParameters {
val req_addr = Reg(UInt(coreMaxAddrBits.W))
val req_rd = Reg(chiselTypeOf(io.resp.bits.rd))
val req_offset = req_addr(pgIdxBits - 1, 0)
val req_vpn = req_addr(coreMaxAddrBits - 1, pgIdxBits)
val pte = Reg(new PTE)
val s_idle :: s_ptw_req :: s_ptw_resp :: s_resp :: Nil = Enum(4)
val state = RegInit(s_idle)
io.cmd.ready := (state === s_idle)
when (io.cmd.fire) {
req_rd := io.cmd.bits.inst.rd
req_addr := io.cmd.bits.rs1
state := s_ptw_req
}
private val ptw = io.ptw(0)
when (ptw.req.fire) { state := s_ptw_resp }
when (state === s_ptw_resp && ptw.resp.valid) {
pte := ptw.resp.bits.pte
state := s_resp
}
when (io.resp.fire) { state := s_idle }
ptw.req.valid := (state === s_ptw_req)
ptw.req.bits.valid := true.B
ptw.req.bits.bits.addr := req_vpn
io.resp.valid := (state === s_resp)
io.resp.bits.rd := req_rd
io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), -1.S(xLen.W).asUInt)
io.busy := (state =/= s_idle)
io.interrupt := false.B
io.mem.req.valid := false.B
}
class CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) {
override lazy val module = new CharacterCountExampleModuleImp(this)
override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC")))))
}
class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
with HasCoreParameters
with HasL1CacheParameters {
val cacheParams = tileParams.dcache.get
private val blockOffset = blockOffBits
private val beatOffset = log2Up(cacheDataBits/8)
val needle = Reg(UInt(8.W))
val addr = Reg(UInt(coreMaxAddrBits.W))
val count = Reg(UInt(xLen.W))
val resp_rd = Reg(chiselTypeOf(io.resp.bits.rd))
val addr_block = addr(coreMaxAddrBits - 1, blockOffset)
val offset = addr(blockOffset - 1, 0)
val next_addr = (addr_block + 1.U) << blockOffset.U
val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(5)
val state = RegInit(s_idle)
val (tl_out, edgesOut) = outer.atlNode.out(0)
val gnt = tl_out.d.bits
val recv_data = Reg(UInt(cacheDataBits.W))
val recv_beat = RegInit(0.U(log2Up(cacheDataBeats+1).W))
val data_bytes = VecInit(Seq.tabulate(cacheDataBits/8) { i => recv_data(8 * (i + 1) - 1, 8 * i) })
val zero_match = data_bytes.map(_ === 0.U)
val needle_match = data_bytes.map(_ === needle)
val first_zero = PriorityEncoder(zero_match)
val chars_found = PopCount(needle_match.zipWithIndex.map {
case (matches, i) =>
val idx = Cat(recv_beat - 1.U, i.U(beatOffset.W))
matches && idx >= offset && i.U <= first_zero
})
val zero_found = zero_match.reduce(_ || _)
val finished = Reg(Bool())
io.cmd.ready := (state === s_idle)
io.resp.valid := (state === s_resp)
io.resp.bits.rd := resp_rd
io.resp.bits.data := count
tl_out.a.valid := (state === s_acq)
tl_out.a.bits := edgesOut.Get(
fromSource = 0.U,
toAddress = addr_block << blockOffset,
lgSize = lgCacheBlockBytes.U)._2
tl_out.d.ready := (state === s_gnt)
when (io.cmd.fire) {
addr := io.cmd.bits.rs1
needle := io.cmd.bits.rs2
resp_rd := io.cmd.bits.inst.rd
count := 0.U
finished := false.B
state := s_acq
}
when (tl_out.a.fire) { state := s_gnt }
when (tl_out.d.fire) {
recv_beat := recv_beat + 1.U
recv_data := gnt.data
state := s_check
}
when (state === s_check) {
when (!finished) {
count := count + chars_found
}
when (zero_found) { finished := true.B }
when (recv_beat === cacheDataBeats.U) {
addr := next_addr
state := Mux(zero_found || finished, s_resp, s_acq)
recv_beat := 0.U
} .otherwise {
state := s_gnt
}
}
when (io.resp.fire) { state := s_idle }
io.busy := (state =/= s_idle)
io.interrupt := false.B
io.mem.req.valid := false.B
// Tie off unused channels
tl_out.b.ready := true.B
tl_out.c.valid := false.B
tl_out.e.valid := false.B
}
class BlackBoxExample(opcodes: OpcodeSet, blackBoxFile: String)(implicit p: Parameters)
extends LazyRoCC(opcodes) {
override lazy val module = new BlackBoxExampleModuleImp(this, blackBoxFile)
}
class BlackBoxExampleModuleImp(outer: BlackBoxExample, blackBoxFile: String)(implicit p: Parameters)
extends LazyRoCCModuleImp(outer)
with RequireSyncReset
with HasCoreParameters {
val blackbox = {
val roccIo = io
Module(
new BlackBox( Map( "xLen" -> IntParam(xLen),
"PRV_SZ" -> IntParam(PRV.SZ),
"coreMaxAddrBits" -> IntParam(coreMaxAddrBits),
"dcacheReqTagBits" -> IntParam(roccIo.mem.req.bits.tag.getWidth),
"M_SZ" -> IntParam(M_SZ),
"mem_req_bits_size_width" -> IntParam(roccIo.mem.req.bits.size.getWidth),
"coreDataBits" -> IntParam(coreDataBits),
"coreDataBytes" -> IntParam(coreDataBytes),
"paddrBits" -> IntParam(paddrBits),
"vaddrBitsExtended" -> IntParam(vaddrBitsExtended),
"FPConstants_RM_SZ" -> IntParam(FPConstants.RM_SZ),
"fLen" -> IntParam(fLen),
"FPConstants_FLAGS_SZ" -> IntParam(FPConstants.FLAGS_SZ)
) ) with HasBlackBoxResource {
val io = IO( new Bundle {
val clock = Input(Clock())
val reset = Input(Reset())
val rocc = chiselTypeOf(roccIo)
})
override def desiredName: String = blackBoxFile
addResource(s"/vsrc/$blackBoxFile.v")
}
)
}
blackbox.io.clock := clock
blackbox.io.reset := reset
blackbox.io.rocc.cmd <> io.cmd
io.resp <> blackbox.io.rocc.resp
io.mem <> blackbox.io.rocc.mem
io.busy := blackbox.io.rocc.busy
io.interrupt := blackbox.io.rocc.interrupt
blackbox.io.rocc.exception := io.exception
io.ptw <> blackbox.io.rocc.ptw
io.fpu_req <> blackbox.io.rocc.fpu_req
blackbox.io.rocc.fpu_resp <> io.fpu_resp
}
class OpcodeSet(val opcodes: Seq[UInt]) {
def |(set: OpcodeSet) =
new OpcodeSet(this.opcodes ++ set.opcodes)
def matches(oc: UInt) = opcodes.map(_ === oc).reduce(_ || _)
}
object OpcodeSet {
def custom0 = new OpcodeSet(Seq("b0001011".U))
def custom1 = new OpcodeSet(Seq("b0101011".U))
def custom2 = new OpcodeSet(Seq("b1011011".U))
def custom3 = new OpcodeSet(Seq("b1111011".U))
def all = custom0 | custom1 | custom2 | custom3
}
class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters)
extends CoreModule()(p) {
val io = IO(new Bundle {
val in = Flipped(Decoupled(new RoCCCommand))
val out = Vec(opcodes.size, Decoupled(new RoCCCommand))
val busy = Output(Bool())
})
val cmd = Queue(io.in)
val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) =>
val me = opcode.matches(cmd.bits.inst.opcode)
out.valid := cmd.valid && me
out.bits := cmd.bits
out.ready && me
}
cmd.ready := cmdReadys.reduce(_ || _)
io.busy := cmd.valid
assert(PopCount(cmdReadys) <= 1.U,
"Custom opcode matched for more than one accelerator")
}
File LoopConv.scala:
package gemmini
import chisel3._
import chisel3.util._
import chisel3.experimental._
import freechips.rocketchip.tile.RoCCCommand
import org.chipsalliance.cde.config.Parameters
import GemminiISA._
import LocalAddr._
import Util._
class LoopConvOuterBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle {
val batch_size = UInt(large_iterator_bitwidth.W)
val in_row_dim = UInt(small_iterator_bitwidth.W)
val in_col_dim = UInt(small_iterator_bitwidth.W)
val in_channels = UInt(large_iterator_bitwidth.W)
val out_channels = UInt(large_iterator_bitwidth.W)
val out_col_dim = UInt(large_iterator_bitwidth.W)
val out_row_dim = UInt(large_iterator_bitwidth.W)
val out_stride = UInt(large_iterator_bitwidth.W) //stride for output activation
val in_stride = UInt(large_iterator_bitwidth.W) //stride for input activation
val weight_stride = UInt(large_iterator_bitwidth.W) //stride for weight
val pool_out_row_dim = UInt(small_iterator_bitwidth.W)
val pool_out_col_dim = UInt(small_iterator_bitwidth.W)
val stride = UInt(tiny_iterator_bitwidth.W)
val padding = UInt(tiny_iterator_bitwidth.W)
val kernel_dim = UInt(tiny_iterator_bitwidth.W)
val kernel_dilation = UInt(tiny_iterator_bitwidth.W)
val pool_size = UInt(tiny_iterator_bitwidth.W)
val pool_stride = UInt(tiny_iterator_bitwidth.W)
val pool_padding = UInt(tiny_iterator_bitwidth.W)
}
class LoopConvInnerBounds(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle {
val batches = UInt(large_iterator_bitwidth.W)
val porows = UInt(small_iterator_bitwidth.W)
val pocols = UInt(small_iterator_bitwidth.W)
val pochs = UInt(large_iterator_bitwidth.W)
val krows = UInt(tiny_iterator_bitwidth.W)
val kcols = UInt(tiny_iterator_bitwidth.W)
val kchs = UInt(large_iterator_bitwidth.W)
val lpad = UInt(tiny_iterator_bitwidth.W)
val rpad = UInt(tiny_iterator_bitwidth.W)
val upad = UInt(tiny_iterator_bitwidth.W)
val dpad = UInt(tiny_iterator_bitwidth.W)
val plpad = UInt(tiny_iterator_bitwidth.W)
val prad = UInt(tiny_iterator_bitwidth.W)
val pupad = UInt(tiny_iterator_bitwidth.W)
val pdpad = UInt(tiny_iterator_bitwidth.W)
val orows = UInt(small_iterator_bitwidth.W)
val ocols = UInt(small_iterator_bitwidth.W)
}
class LoopConvDerivedParams(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int) extends Bundle {
val ochs = UInt(large_iterator_bitwidth.W)
val irows = UInt(small_iterator_bitwidth.W)
val icols = UInt(small_iterator_bitwidth.W)
val irows_unpadded = UInt(small_iterator_bitwidth.W)
val icols_unpadded = UInt(small_iterator_bitwidth.W)
val ichs = UInt(large_iterator_bitwidth.W)
val out_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size
val in_channels_per_bank = UInt(small_iterator_bitwidth.W) // TODO this won't work for systolic arrays above 256 in size
val bias_spad_stride = UInt(large_iterator_bitwidth.W)
val input_spad_stride = UInt(large_iterator_bitwidth.W)
val weight_spad_stride = UInt(large_iterator_bitwidth.W)
// val ex_overwrite = Bool()
}
class LoopConvLdBiasReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val addr_start = UInt(log2Up(max_acc_addr).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val no_bias = Bool()
val loop_id = UInt(log2Up(concurrent_loops).W)
}
class LoopConvLdBias(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, acc_w: Int,
max_block_len_acc: Int, concurrent_loops: Int, latency: Int,
config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module {
val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val wait_for_prev_loop = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, config, ld = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopConvLdBiasReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))
import req.inner_bounds._
import req.derived_params._
val acc_addr_start = req.addr_start
// Derived parameters
val max_ochs_per_mvin = Mux(ochs < (max_block_len_acc * block_size).U, ochs, (max_block_len_acc * block_size).U)
val skip = req.dram_addr === 0.U
// Iterators
val b = Reg(UInt(large_iterator_bitwidth.W))
val orow = Reg(UInt(small_iterator_bitwidth.W))
val ocol = Reg(UInt(small_iterator_bitwidth.W))
val och = Reg(UInt(large_iterator_bitwidth.W))
// Addresses
val dram_offset = och * (acc_w/8).U
val dram_addr = Mux(req.no_bias, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset))
val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol
// Sizes
val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol)
val J = Mux(ochs - och > max_ochs_per_mvin, max_ochs_per_mvin, ochs - och)
class RoCCCommandWithAddr extends Bundle {
val cmd = new RoCCCommand
val dram_addr = UInt()
val spad_addr = UInt()
val I = UInt()
val J = UInt()
}
val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)())
// Commands
val config_cmd = Wire(new RoCCCommand)
config_cmd := DontCare
config_cmd.inst.funct := CONFIG_CMD
val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType)
config_cmd_rs1 := DontCare
config_cmd_rs1.scale := MVIN_SCALE_IDENTITY
config_cmd_rs1.stride := req.derived_params.bias_spad_stride
config_cmd_rs1.pixel_repeats := 1.U
config_cmd_rs1.state_id := 2.U
config_cmd_rs1.shrink := 0.U
config_cmd_rs1._unused := 1.U
config_cmd.rs1 := config_cmd_rs1.asUInt
config_cmd.rs2 := 0.U
val mvin_cmd = Wire(new RoCCCommand)
mvin_cmd := DontCare
mvin_cmd.inst.funct := LOAD3_CMD
mvin_cmd.rs1 := 0.U
mvin_cmd.rs2 := 0.U
// Inputs and outputs
io.req.ready := state === idle && !command_p.io.busy
io.idle := state === idle && !command_p.io.busy
io.loop_id := req.loop_id
command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && !skip
command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd)
command_p.io.in.bits.dram_addr := dram_addr
command_p.io.in.bits.spad_addr := spad_addr
command_p.io.in.bits.I := I
command_p.io.in.bits.J := J
command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded
io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded
io.cmd.bits := command_p.io.out.bits.cmd
when (command_p.io.out.bits.cmd.inst.funct === LOAD3_CMD) {
val o = command_p.io.out.bits
io.cmd.bits.rs1 := o.dram_addr
val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType)
mvin_cmd_rs2 := DontCare
mvin_cmd_rs2.num_rows := o.I.asUInt
mvin_cmd_rs2.num_cols := o.J.asUInt
mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B)
io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt
}
// Sending outputs
when (skip) {
state := idle
}.elsewhen(command_p.io.in.fire) {
when (state === config) {
state := ld
}.otherwise {
val next_och = floorAdd(och, max_ochs_per_mvin, ochs)
val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U)
val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U)
val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U)
och := next_och
ocol := next_ocol
orow := next_orow
b := next_b
state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U,
idle, ld)
}
}
// Accepting requests
when (io.req.fire) {
req := io.req.bits
state := config
b := 0.U
orow := 0.U
ocol := 0.U
och := 0.U
}
}
class LoopConvLdInputReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val addr_start = UInt(log2Up(max_acc_addr).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val downsample = Bool()
val max_pixels_per_row = UInt(small_iterator_bitwidth.W)
val input_dilated = Bool()
val trans_input_3120 = Bool()
val loop_id = UInt(log2Up(concurrent_loops).W)
}
class LoopConvLdInput(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int,
tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int, max_block_len: Int,
concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2)
(implicit p: Parameters) extends Module {
val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val wait_for_prev_loop = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, config, ld = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopConvLdInputReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))
import req.outer_bounds._
import req.inner_bounds._
import req.derived_params._
def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated
// Derived parameters
val max_ichs_per_mvin = Mux(ichs < (max_block_len * block_size).U, ichs, (max_block_len * block_size).U).zext
val max_batches_per_mvin = Mux(batches < (max_block_len * block_size).U, batches, (max_block_len * block_size).U).zext
val max_chs_per_mvin = Mux(req.trans_input_3120, max_batches_per_mvin, max_ichs_per_mvin)
// Iterators
val b = Reg(SInt(large_iterator_bitwidth.W))
val irow = Reg(SInt(small_iterator_bitwidth.W))
val icol = Reg(SInt(small_iterator_bitwidth.W))
val ich = Reg(SInt(large_iterator_bitwidth.W))
// Calculated params
val irow_padded = irow +& undilated(upad).zext
val icol_padded = icol +& undilated(lpad).zext
val is_zeros = irow < 0.S || irow >= irows_unpadded.zext || icol < 0.S || icol >= icols_unpadded.zext
val dram_stride = Mux(req.trans_input_3120, batch_size * (input_w/8).U, in_stride * (input_w/8).U)
// Addresses
val dram_offset = Mux(req.trans_input_3120, (((ich * in_col_dim * in_row_dim +& irow*in_col_dim +& icol) * batches +& b) * (input_w/8).U).asUInt,
(((b * in_row_dim * in_col_dim +& irow*in_col_dim +& icol) * in_stride +& ich) * (input_w/8).U).asUInt)
val dram_addr = Mux(is_zeros, 0.U, req.dram_addr + LoopConv.castDramOffset(dram_offset))
val spad_addr = Mux(req.trans_input_3120,
// To prevent Verilator errors, we replace some "/ block_size.U" calls here with ">> log2Up(block_size)"
req.addr_start.zext +& (b >> log2Up(block_size)) * input_spad_stride +& ich * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample),
req.addr_start.zext +& (ich >> log2Up(block_size)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow_padded >> req.downsample) * (icols >> req.downsample) +& (icol_padded >> req.downsample))
// Sizes
val block_size_downsampled = (block_size.U << req.downsample).asUInt.zext
val I = MuxCase(
Mux(icols_unpadded.zext -& icol > block_size_downsampled, block_size_downsampled, icols_unpadded.zext -& icol),
Seq(
(icol < 0.S) -> Mux((0.S-&icol) > block_size.S, block_size.S, 0.S-&icol),
(icol >= icols_unpadded.zext) -> Mux(icols_unpadded.zext +& undilated(rpad).zext -& icol > block_size.S, block_size.S, icols_unpadded.zext +& undilated(rpad).zext -& icol)
)
)
val K = Mux(req.trans_input_3120,
Mux(batches.zext -& b > max_chs_per_mvin, max_chs_per_mvin, batches.zext -& b),
Mux(ichs.zext -& ich > max_chs_per_mvin, max_chs_per_mvin, ichs.zext -& ich))
class RoCCCommandWithAddr extends Bundle {
val cmd = new RoCCCommand
val dram_addr = UInt()
val spad_addr = SInt()
val I = SInt()
val K = SInt()
}
val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)())
// Commands
val config_cmd = Wire(new RoCCCommand)
config_cmd := DontCare
config_cmd.inst.funct := CONFIG_CMD
val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType)
config_cmd_rs1 := DontCare
config_cmd_rs1.scale := MVIN_SCALE_IDENTITY
config_cmd_rs1.stride := input_spad_stride
config_cmd_rs1.pixel_repeats := req.max_pixels_per_row
config_cmd_rs1.state_id := 0.U
config_cmd_rs1.shrink := 0.U
config_cmd_rs1._unused := 1.U
config_cmd.rs1 := config_cmd_rs1.asUInt
config_cmd.rs2 := dram_stride << req.downsample
val mvin_cmd = Wire(new RoCCCommand)
mvin_cmd := DontCare
mvin_cmd.inst.funct := LOAD_CMD
mvin_cmd.rs1 := 0.U // dram_addr
mvin_cmd.rs2 := 0.U // mvin_cmd_rs2
// Inputs and outputs
io.req.ready := state === idle && !command_p.io.busy
io.idle := state === idle && !command_p.io.busy
io.loop_id := req.loop_id
command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U)
command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd)
command_p.io.in.bits.dram_addr := dram_addr
command_p.io.in.bits.spad_addr := spad_addr
command_p.io.in.bits.I := I
command_p.io.in.bits.K := K
command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded
io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded
io.cmd.bits := command_p.io.out.bits.cmd
when (command_p.io.out.bits.cmd.inst.funct === LOAD_CMD) {
val o = command_p.io.out.bits
io.cmd.bits.rs1 := o.dram_addr
val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType)
mvin_cmd_rs2 := DontCare
mvin_cmd_rs2.num_rows := (o.I >> req.downsample).asUInt
mvin_cmd_rs2.num_cols := o.K.asUInt
mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr)
io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt
}
// Sending outputs
when(req.dram_addr === 0.U){
state := idle
}.elsewhen(command_p.io.in.fire) {
when (state === config) {
state := ld
}.otherwise {
val b_it = Mux(req.trans_input_3120, max_chs_per_mvin.asUInt, 1.U)
val ich_it = Mux(req.trans_input_3120, 1.U, max_chs_per_mvin.asUInt)
val next_ich = sFloorAdd(ich, ich_it, ichs.zext, 0.S)
val next_icol = sFloorAdd(icol, I.asUInt, (icols_unpadded +& undilated(rpad)).zext, 0.S-&undilated(lpad).zext,
next_ich === 0.S)
val next_irow = sFloorAdd(irow, 1.U << req.downsample, (irows_unpadded +& undilated(dpad)).zext, 0.S-&undilated(upad).zext,
next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S)
val next_b = sFloorAdd(b, b_it, batches.zext, 0.S,
next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S)
ich := next_ich
icol := next_icol
irow := next_irow
b := next_b
state := Mux(next_b === 0.S && next_irow === 0.S-&undilated(upad).zext && next_icol === 0.S-&undilated(lpad).zext && next_ich === 0.S,
idle, ld)
}
}
// Accepting requests
when (io.req.fire) {
req := io.req.bits
state := config
b := 0.S
irow := 0.S -& ((io.req.bits.inner_bounds.upad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext
icol := 0.S -& ((io.req.bits.inner_bounds.lpad +& io.req.bits.input_dilated) >> io.req.bits.input_dilated).zext
ich := 0.S
}
}
class LoopConvLdWeightReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle {
val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val addr_end = UInt(log2Up(max_addr+1).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val trans_weight_1203 = Bool()
val trans_weight_0132 = Bool()
val dw = Bool()
val loop_id = UInt(log2Up(concurrent_loops).W)
}
class LoopConvLdWeight(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int,
small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int, input_w: Int,
max_block_len: Int, concurrent_loops: Int, latency: Int, config_mvin_rs1_t: ConfigMvinRs1,
mvin_rs2_t: MvinRs2)(implicit p: Parameters) extends Module {
val MVIN_SCALE_IDENTITY = 0x3f800000.U // TODO get this from configs somehow
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val wait_for_prev_loop = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, config, ld = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopConvLdWeightReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, concurrent_loops))
import req.outer_bounds._
import req.inner_bounds._
import req.derived_params._
// Derived parameters
val max_chs_per_mvin = {
val max_ochs_per_mvin = Mux(ochs < (max_block_len * block_size).U, ochs, (max_block_len * block_size).U)
val max_kchs_per_mvin = Mux(kchs < (max_block_len * block_size).U, kchs, (max_block_len * block_size).U)
Mux(req.trans_weight_0132, max_kchs_per_mvin, max_ochs_per_mvin)
}
val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs,
out_channels_per_bank * kcols * krows * kchs)
val addr_start = req.addr_end - B_rows
val dram_stride = MuxCase(weight_stride, Seq(
req.dw -> 1.U,
req.trans_weight_1203 -> (kernel_dim * kernel_dim * out_channels),
req.trans_weight_0132 -> in_channels
)) * (input_w/8).U
// Iterators
val och = Reg(UInt(large_iterator_bitwidth.W))
val krow = Reg(UInt(tiny_iterator_bitwidth.W))
val kcol = Reg(UInt(tiny_iterator_bitwidth.W))
val kch = Reg(UInt(large_iterator_bitwidth.W))
// Addresses
val dram_offset = MuxCase(((krow*kernel_dim*in_channels +& kcol*in_channels +& kch) * weight_stride +& och) * (input_w/8).U, Seq(
req.dw -> (krow * kernel_dim +& kcol) * (input_w/8).U,
req.trans_weight_1203 -> (((kch*kernel_dim*kernel_dim +& krow*kernel_dim +& kcol) * out_channels +& och) * (input_w/8).U),
req.trans_weight_0132 -> (((krow*kernel_dim*out_channels +& kcol*out_channels +& och) * in_channels +& kch) * (input_w/8).U)
))
val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset)
val spad_addr = Mux(req.trans_weight_0132,
// The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier
addr_start + (kch / block_size.U(kch.getWidth.W)) * krows * kcols * ochs + krow * kcols * ochs + kcol * ochs + och,
addr_start + (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs + krow * kcols * kchs + kcol * kchs + kch)
// Sizes
val J = Mux(req.trans_weight_0132,
Mux(kchs - kch > max_chs_per_mvin, max_chs_per_mvin, kchs - kch),
Mux(ochs - och > max_chs_per_mvin, max_chs_per_mvin, ochs - och))
val K = Mux(req.trans_weight_0132,
Mux(ochs - och > block_size.U, block_size.U, ochs - och),
Mux(kchs - kch > block_size.U, block_size.U, kchs - kch))
class RoCCCommandWithAddr extends Bundle {
val cmd = new RoCCCommand
val dram_addr = UInt()
val spad_addr = UInt()
val K = UInt()
val J = UInt()
}
val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)())
// Commands
val config_cmd = Wire(new RoCCCommand)
config_cmd := DontCare
config_cmd.inst.funct := CONFIG_CMD
val config_cmd_rs1 = Wire(config_mvin_rs1_t.cloneType)
config_cmd_rs1 := DontCare
config_cmd_rs1.scale := MVIN_SCALE_IDENTITY
config_cmd_rs1.stride := req.derived_params.weight_spad_stride
config_cmd_rs1.pixel_repeats := 1.U
config_cmd_rs1.state_id := 1.U
config_cmd_rs1.shrink := 0.U
config_cmd_rs1._unused := 1.U
config_cmd.rs1 := config_cmd_rs1.asUInt
config_cmd.rs2 := dram_stride
val mvin_cmd = Wire(new RoCCCommand)
mvin_cmd := DontCare
mvin_cmd.inst.funct := LOAD2_CMD
mvin_cmd.rs1 := 0.U // dram_addr
mvin_cmd.rs2 := 0.U // mvin_cmd_rs2
// Inputs and outputs
io.req.ready := state === idle && !command_p.io.busy
io.idle := state === idle && !command_p.io.busy
io.loop_id := req.loop_id
command_p.io.in.valid := state =/= idle && !io.wait_for_prev_loop && (req.dram_addr =/= 0.U)
command_p.io.in.bits.cmd := Mux(state === config, config_cmd, mvin_cmd)
command_p.io.in.bits.dram_addr := dram_addr
command_p.io.in.bits.spad_addr := spad_addr
command_p.io.in.bits.K := K
command_p.io.in.bits.J := J
command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded
io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded
io.cmd.bits := command_p.io.out.bits.cmd
when (command_p.io.out.bits.cmd.inst.funct === LOAD2_CMD) {
val o = command_p.io.out.bits
io.cmd.bits.rs1 := o.dram_addr
val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType)
mvin_cmd_rs2 := DontCare
mvin_cmd_rs2.num_rows := o.K
mvin_cmd_rs2.num_cols := o.J
mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, o.spad_addr)
io.cmd.bits.rs2 := mvin_cmd_rs2.asUInt
}
// Sending outputs
when(req.dram_addr === 0.U){
state := idle
}.elsewhen(command_p.io.in.fire) {
when (state === config) {
state := ld
}.otherwise {
val och_it = Mux(req.trans_weight_0132, block_size.U, max_chs_per_mvin)
val kch_it = Mux(req.trans_weight_0132, max_chs_per_mvin, block_size.U)
val next_kch = floorAdd(kch, kch_it, kchs)
val next_kcol = floorAdd(kcol, 1.U, kcols, next_kch === 0.U)
val next_krow = floorAdd(krow, 1.U, krows, next_kcol === 0.U && next_kch === 0.U)
val next_och = floorAdd(och, och_it, ochs, next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U)
kch := next_kch
kcol := next_kcol
krow := next_krow
och := next_och
state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U,
idle, ld)
}
}
// Accepting requests
when (io.req.fire) {
req := io.req.bits
state := config
kch := 0.U
kcol := 0.U
krow := 0.U
och := 0.U
}
}
class LoopConvExecuteReq(val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val a_addr_start = UInt(log2Up(max_addr).W)
val b_addr_end = UInt(log2Up(max_addr+1).W)
val c_addr_start = UInt(log2Up(max_acc_addr).W)
val wrot180 = Bool()
val downsample = Bool()
val max_pixels_per_row = UInt(small_iterator_bitwidth.W)
val input_dilated = Bool()
val trans_weight_0132 = Bool()
val trans_input_3120 = Bool()
val loop_id = UInt(log2Up(concurrent_loops).W)
}
class LoopConvExecute(block_size: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_addr: Int,
max_acc_addr: Int, concurrent_loops: Int, latency: Int,
config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val lda_completed = Input(Bool())
val ldb_completed = Input(Bool())
val ldd_completed = Input(Bool())
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, config, pre, comp = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopConvExecuteReq(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth,
max_addr, max_acc_addr, concurrent_loops))
import req.outer_bounds._
import req.inner_bounds._
import req.derived_params._
def undilated(x: UInt): UInt = (x +& req.input_dilated) >> req.input_dilated
// Derived parameters
val B_rows = Mux(req.trans_weight_0132, in_channels_per_bank * kcols * krows * ochs,
out_channels_per_bank * kcols * krows * kchs)
val a_addr_start = req.a_addr_start
val b_addr_start = req.b_addr_end - B_rows
val c_addr_start = /*(BigInt(3) << 30).U |*/ req.c_addr_start
// Iterators
val och = Reg(UInt(large_iterator_bitwidth.W))
val krow = Reg(UInt(tiny_iterator_bitwidth.W))
val kcol = Reg(UInt(tiny_iterator_bitwidth.W))
val kch = Reg(UInt(large_iterator_bitwidth.W))
val b = Reg(UInt(large_iterator_bitwidth.W))
val orow = Reg(UInt(small_iterator_bitwidth.W))
val ocol = Reg(UInt(small_iterator_bitwidth.W))
// TODO kernel-dilation and input-dilation can never be activated at the same time, so we can optimize out some multiplications by kernel_dilation
val skip_iteration = state >= pre && req.input_dilated && (((krow * kernel_dilation +& orow -& upad)(0) & req.input_dilated).asBool ||
((kcol * kernel_dilation +& ocol -& lpad)(0) & req.input_dilated).asBool)
val pixels = Mux(kcols - kcol > req.max_pixels_per_row, req.max_pixels_per_row, kcols - kcol)
val irow = undilated(orow * stride +& krow * kernel_dilation)
val icol = undilated(ocol * stride +& kcol * kernel_dilation)
val I = Mux(req.trans_input_3120,
Mux(batches - b > block_size.U, block_size.U, batches - b),
undilated(Mux(ocols - ocol > (block_size.U << req.input_dilated).asUInt, (block_size.U << req.input_dilated).asUInt, ocols - ocol)))
val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och)
val K = pixels * Mux(kchs - kch > block_size.U, block_size.U, kchs - kch)
// Addresses
val a_addr = Mux(req.trans_input_3120,
a_addr_start +& (b / block_size.U) * input_spad_stride +& kch * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample),
a_addr_start +& (kch / block_size.U(kch.getWidth.W)) * input_spad_stride +& b * (irows >> req.downsample) * (icols >> req.downsample) +& (irow >> req.downsample) * (icols >> req.downsample) +& (icol >> req.downsample))
// val c_addr = Mux(ex_overwrite && krow === 0.U && kcol === 0.U && kch === 0.U, d_addr_start, c_addr_start) +&
// (och / block_size.U) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol
// The width expansions are added here solely to prevent Verilator's "WIDTH" warnings, despite making the code uglier
val c_addr = c_addr_start +&
(och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol
// val new_weights = b === 0.U && orow === 0.U && ocol === 0.U
val new_weights = Reg(Bool())
val krow_rot = Mux(req.wrot180, krows - krow - 1.U, krow)
val kcol_rot = Mux(req.wrot180, kcols - kcol - 1.U, kcol)
val b_addr = Mux(req.trans_weight_0132,
b_addr_start +& (kch / block_size.U(och.getWidth.W)) * krows * kcols * ochs +& krow_rot * kcols * ochs +& kcol_rot * ochs +& och,
b_addr_start +& (och / block_size.U(och.getWidth.W)) * krows * kcols * kchs +& krow_rot * kcols * kchs +& kcol_rot * kchs +& kch)
class RoCCCommandWithAddr extends Bundle {
val cmd = new RoCCCommand
val a_addr = UInt()
val b_addr = UInt()
val c_addr = UInt()
val I = UInt()
val J = UInt()
val K = UInt()
val new_weights = Bool()
}
val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)())
// Commands
val config_cmd = Wire(new RoCCCommand)
config_cmd := DontCare
config_cmd.inst.funct := CONFIG_CMD
val config_cmd_rs1 = Wire(config_ex_rs1_t.cloneType)
config_cmd_rs1 := DontCare
config_cmd_rs1.a_stride := (irows * icols).asUInt
config_cmd_rs1.set_only_strides := 1.U
config_cmd_rs1.cmd_type := 0.U
val config_cmd_rs2 = Wire(new ConfigExRs2)
config_cmd_rs2 := DontCare
config_cmd_rs2.c_stride := (orows * ocols).asUInt
config_cmd.rs1 := config_cmd_rs1.asUInt
config_cmd.rs2 := config_cmd_rs2.asUInt
val pre_cmd = Wire(new RoCCCommand) // preload
pre_cmd := DontCare
pre_cmd.inst.funct := PRELOAD_CMD
pre_cmd.rs1 := 0.U//(K << 48) | (J << 32) | pre_addr
pre_cmd.rs2 := 0.U//(I << 48) | (J << 32) | c_addr
val comp_cmd = Wire(new RoCCCommand()) // compute.preloaded
comp_cmd := DontCare
comp_cmd.inst.funct := Mux(new_weights, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD)
comp_cmd.rs1 := 0.U//(I << 48) | (K << 32) | a_addr
comp_cmd.rs2 := 0.U//(I << 48) | (J << 32) | GARBAGE_ADDR
val ld_ahead = io.lda_completed && io.ldb_completed && io.ldd_completed
// Inputs and outputs
io.req.ready := state === idle && !command_p.io.busy
io.idle := state === idle && !command_p.io.busy
io.loop_id := req.loop_id
command_p.io.in.valid := state =/= idle && !skip_iteration && ld_ahead
command_p.io.in.bits.cmd := MuxCase(config_cmd, Seq((state === pre) -> pre_cmd, (state === comp) -> comp_cmd))
command_p.io.in.bits.a_addr := a_addr
command_p.io.in.bits.b_addr := b_addr
command_p.io.in.bits.c_addr := c_addr
command_p.io.in.bits.I := I
command_p.io.in.bits.J := J
command_p.io.in.bits.K := K
command_p.io.in.bits.new_weights := new_weights
command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded
io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded
io.cmd.bits := command_p.io.out.bits.cmd
when (command_p.io.out.bits.cmd.inst.funct === PRELOAD_CMD) {
val o = command_p.io.out.bits
val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType)
pre_cmd_rs1 := DontCare
pre_cmd_rs1.num_rows := o.K.asUInt
pre_cmd_rs1.num_cols := o.J.asUInt
pre_cmd_rs1.local_addr := Mux(o.new_weights, cast_to_sp_addr(pre_cmd_rs1.local_addr, o.b_addr),
garbage_addr(pre_cmd_rs1.local_addr))
val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType)
pre_cmd_rs2 := DontCare
pre_cmd_rs2.num_rows := o.I.asUInt
pre_cmd_rs2.num_cols := o.J.asUInt
pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, o.c_addr, accumulate = true.B, read_full = false.B)
io.cmd.bits.rs1 := pre_cmd_rs1.asUInt
io.cmd.bits.rs2 := pre_cmd_rs2.asUInt
}.elsewhen(command_p.io.out.bits.cmd.inst.funct =/= CONFIG_CMD) {
val o = command_p.io.out.bits
val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType)
comp_cmd_rs1 := DontCare
comp_cmd_rs1.num_rows := o.I.asUInt
comp_cmd_rs1.num_cols := o.K.asUInt
comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, o.a_addr)
val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType)
comp_cmd_rs2 := DontCare
comp_cmd_rs2.num_rows := o.I.asUInt
comp_cmd_rs2.num_cols := o.J.asUInt
comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr)
io.cmd.bits.rs1 := comp_cmd_rs1.asUInt
io.cmd.bits.rs2 := comp_cmd_rs2.asUInt
}
// Updating "new_weights"
when (state === comp && command_p.io.in.fire) {
new_weights := false.B
}
// Sending outputs
when (command_p.io.in.fire || skip_iteration) {
when (state === config) {
state := pre
}.elsewhen (state === pre) {
state := comp
}.otherwise {
val b_it = Mux(req.trans_input_3120, block_size.U, 1.U)
val ocol_it = Mux(skip_iteration || req.trans_input_3120, 1.U, block_size.U << req.input_dilated).asUInt
val next_ocol = floorAdd(ocol, ocol_it, ocols)
val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U)
val next_b = floorAdd(b, b_it, batches, next_orow === 0.U && next_ocol === 0.U)
val next_kch = floorAdd(kch, block_size.U, kchs,
next_b === 0.U && next_orow === 0.U && next_ocol === 0.U)
val next_kcol = floorAdd(kcol, req.max_pixels_per_row, kcols,
next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U)
val next_krow = floorAdd(krow, 1.U, krows,
next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U)
val next_och = floorAdd(och, block_size.U, ochs, next_krow === 0.U &&
next_kcol === 0.U && next_kch === 0.U && next_b === 0.U && next_orow === 0.U && next_ocol === 0.U)
ocol := next_ocol
orow := next_orow
b := next_b
kch := next_kch
kcol := next_kcol
krow := next_krow
och := next_och
when (next_b === 0.U && next_orow === 0.U && next_ocol === 0.U) {
new_weights := true.B
}
state := Mux(next_och === 0.U && next_krow === 0.U && next_kcol === 0.U && next_kch === 0.U && next_b === 0.U &&
next_orow === 0.U && next_ocol === 0.U,
idle, pre)
}
}
// Accepting requests
when (io.req.fire) {
req := io.req.bits
state := Mux(io.req.bits.trans_input_3120, config, pre)
b := 0.U
orow := 0.U
ocol := 0.U
och := 0.U
krow := 0.U
kcol := 0.U
kch := 0.U
new_weights := true.B
}
}
class LoopConvStReq(val coreMaxAddrBits: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val derived_params = new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val addr_start = UInt(log2Up(max_acc_addr).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val no_pool = Bool()
val activation = UInt(2.W) // TODO magic number
val trans_output_1203 = Bool()
val loop_id = UInt(log2Up(concurrent_loops).W)
}
class LoopConvSt(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: Int, small_iterator_bitwidth: Int, tiny_iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, concurrent_loops: Int, latency: Int, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2)(implicit p: Parameters) extends Module {
val ACC_SCALE_NO_CHANGE = ~(0.U(32.W)) // TODO get this from ISA description somehow
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val ex_completed = Input(Bool())
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, st, pre_pool_config, pool, post_pool_config = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopConvStReq(coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth: Int, max_acc_addr, concurrent_loops))
import req.outer_bounds._
import req.inner_bounds._
import req.derived_params._
val acc_addr_start = req.addr_start
// Derived parameters
val skip = req.dram_addr === 0.U
// Iterators
val b = Reg(UInt(large_iterator_bitwidth.W))
val orow = Reg(UInt(small_iterator_bitwidth.W))
val ocol = Reg(UInt(small_iterator_bitwidth.W))
val och = Reg(UInt(large_iterator_bitwidth.W))
// Addresses
val dram_offset = Mux(req.trans_output_1203,
((orow*out_col_dim*batch_size +& ocol*batch_size +& b) * out_channels +& och) * (input_w/8).U,
((b*out_row_dim*out_col_dim +& orow*out_col_dim +& ocol) * out_stride +& och) * (input_w/8).U)
val dram_addr = req.dram_addr + LoopConv.castDramOffset(dram_offset)
val spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols +& orow * ocols +& ocol
val pool_dram_addr = req.dram_addr + ((b * pool_out_col_dim * pool_out_row_dim) * out_stride + och) * (input_w/8).U
val pool_spad_addr = acc_addr_start +& (och / block_size.U(och.getWidth.W)) * batches * orows * ocols +& b * orows * ocols
// Sizes
val I = Mux(ocols - ocol > block_size.U, block_size.U, ocols - ocol)
val J = Mux(ochs - och > block_size.U, block_size.U, ochs - och)
val channels = J
class RoCCCommandWithAddr extends Bundle {
val cmd = new RoCCCommand
val dram_addr = UInt()
val spad_addr = UInt()
val pool_dram_addr = UInt()
val pool_spad_addr = UInt()
val channels = UInt()
val is_pool = Bool()
val I = UInt()
val J = UInt()
}
val command_p = Module(new Pipeline[RoCCCommandWithAddr](new RoCCCommandWithAddr, latency)())
// Commands
val mvout_cmd = Wire(new RoCCCommand)
mvout_cmd := DontCare
mvout_cmd.inst.funct := STORE_CMD
mvout_cmd.rs1 := 0.U // dram_addr
mvout_cmd.rs2 := 0.U // mvout_cmd_rs2
val pre_pool_config_cmd = Wire(new RoCCCommand)
pre_pool_config_cmd := DontCare
pre_pool_config_cmd.inst.funct := CONFIG_CMD
val pre_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1)
pre_pool_config_cmd_rs1 := DontCare
pre_pool_config_cmd_rs1.ocols := ocols
pre_pool_config_cmd_rs1.orows := orows
pre_pool_config_cmd_rs1.pocols := pocols
pre_pool_config_cmd_rs1.porows := porows
pre_pool_config_cmd_rs1.pool_out_dim := pool_out_col_dim
pre_pool_config_cmd_rs1.lpad := plpad
pre_pool_config_cmd_rs1.upad := pupad
pre_pool_config_cmd_rs1.pool_size := pool_size
pre_pool_config_cmd_rs1.pool_stride := pool_stride
pre_pool_config_cmd_rs1.activation := req.activation
pre_pool_config_cmd_rs1.cmd_type := CONFIG_STORE
pre_pool_config_cmd.rs1 := pre_pool_config_cmd_rs1.asUInt
val pre_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType)
pre_pool_config_cmd_rs2 := DontCare
pre_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE
pre_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U
pre_pool_config_cmd.rs2 := pre_pool_config_cmd_rs2.asUInt
val post_pool_config_cmd = Wire(new RoCCCommand)
post_pool_config_cmd := DontCare
post_pool_config_cmd.inst.funct := CONFIG_CMD
val post_pool_config_cmd_rs1 = Wire(new ConfigMvoutRs1)
post_pool_config_cmd_rs1 := DontCare
post_pool_config_cmd_rs1.activation := req.activation
post_pool_config_cmd_rs1.cmd_type := CONFIG_STORE
post_pool_config_cmd.rs1 := post_pool_config_cmd_rs1.asUInt
val post_pool_config_cmd_rs2 = Wire(config_mvout_rs2_t.cloneType)
post_pool_config_cmd_rs2 := DontCare
post_pool_config_cmd_rs2.acc_scale := ACC_SCALE_NO_CHANGE
post_pool_config_cmd_rs2.stride := out_stride * (input_w / 8).U
post_pool_config_cmd.rs2 := post_pool_config_cmd_rs2.asUInt
val pool_cmd = Wire(new RoCCCommand)
pool_cmd := DontCare
pool_cmd.inst.funct := STORE_CMD
pool_cmd.rs1 := 0.U//pool_dram_addr
pool_cmd.rs2 := 0.U//(channels << 32.U) | pool_spad_addr
// Inputs and outputs
io.req.ready := state === idle && !command_p.io.busy
io.idle := state === idle && !command_p.io.busy
io.loop_id := req.loop_id
command_p.io.in.valid := state =/= idle && !skip && io.ex_completed
command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd)(Seq(
pre_pool_config.asUInt -> pre_pool_config_cmd,
pool.asUInt -> pool_cmd,
post_pool_config.asUInt -> post_pool_config_cmd)
)
command_p.io.in.bits.is_pool := state === pool
command_p.io.in.bits.dram_addr := dram_addr
command_p.io.in.bits.spad_addr := spad_addr
command_p.io.in.bits.pool_spad_addr := pool_spad_addr
command_p.io.in.bits.pool_dram_addr := pool_dram_addr
command_p.io.in.bits.channels := channels
command_p.io.in.bits.I := I
command_p.io.in.bits.J := J
command_p.io.out.ready := io.cmd.ready && !io.rob_overloaded
io.cmd.valid := command_p.io.out.valid && !io.rob_overloaded
io.cmd.bits := command_p.io.out.bits.cmd
when (command_p.io.out.bits.cmd.inst.funct === STORE_CMD) {
val o = command_p.io.out.bits
when (o.is_pool) {
val pool_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType)
pool_mvout_cmd_rs2 := DontCare
pool_mvout_cmd_rs2.num_cols := o.channels
pool_mvout_cmd_rs2.local_addr := cast_to_acc_addr(pool_mvout_cmd_rs2.local_addr, o.pool_spad_addr, accumulate = false.B, read_full = false.B)
io.cmd.bits.rs1 := o.pool_dram_addr
io.cmd.bits.rs2 := pool_mvout_cmd_rs2.asUInt
} .otherwise {
val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType)
mvout_cmd_rs2 := DontCare
mvout_cmd_rs2.num_rows := o.I.asUInt
mvout_cmd_rs2.num_cols := o.J.asUInt
mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, o.spad_addr, accumulate = false.B, read_full = false.B)
io.cmd.bits.rs1 := o.dram_addr
io.cmd.bits.rs2 := mvout_cmd_rs2.asUInt
}
}
// Sending outputs
when (skip) {
state := idle
}.elsewhen(command_p.io.in.fire) {
when (req.no_pool) {
val next_och = floorAdd(och, block_size.U, ochs)
val next_ocol = floorAdd(ocol, block_size.U, ocols, next_och === 0.U)
val next_orow = floorAdd(orow, 1.U, orows, next_ocol === 0.U && next_och === 0.U)
val next_b = floorAdd(b, 1.U, batches, next_orow === 0.U && next_ocol === 0.U && next_och === 0.U)
och := next_och
ocol := next_ocol
orow := next_orow
b := next_b
state := Mux(next_b === 0.U && next_orow === 0.U && next_ocol === 0.U && next_och === 0.U,
idle, st)
}.elsewhen(state === pre_pool_config) {
state := pool
}.elsewhen(state === post_pool_config) {
state := idle
}.otherwise {
val next_och = floorAdd(och, block_size.U, ochs)
val next_b = floorAdd(b, 1.U, batches, next_och === 0.U)
och := next_och
b := next_b
state := Mux(next_b === 0.U && next_och === 0.U,
post_pool_config, pool)
}
}
// Accepting requests
when (io.req.fire) {
req := io.req.bits
state := Mux(io.req.bits.no_pool, st, pre_pool_config)
b := 0.U
orow := 0.U
ocol := 0.U
och := 0.U
}
}
class LoopConvState(val block_size: Int, val large_iterator_bitwidth: Int, val small_iterator_bitwidth: Int, val tiny_iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle {
val outer_bounds = new LoopConvOuterBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val inner_bounds = new LoopConvInnerBounds(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth)
val bias_dram_addr = UInt(coreMaxAddrBits.W)
val weights_dram_addr = UInt(coreMaxAddrBits.W)
val input_dram_addr = UInt(coreMaxAddrBits.W)
val output_dram_addr = UInt(coreMaxAddrBits.W)
val no_bias = Bool()
val wrot180 = Bool()
val no_pool = Bool()
val downsample = Bool()
val input_dilated = Bool()
val activation = UInt(2.W) // TODO magic number
val trans_output_1203 = Bool()
val trans_weight_1203 = Bool()
val trans_weight_0132 = Bool()
val trans_input_3120 = Bool()
val dw = Bool()
val max_pixels_per_row = UInt(small_iterator_bitwidth.W)
val a_ex_spad_id = UInt(2.W)
val b_ex_spad_id = UInt(2.W)
val configured = Bool()
val running = Bool()
val ld_bias_started = Bool()
val ld_input_started = Bool()
val ld_weights_started = Bool()
val ex_started = Bool()
val st_started = Bool()
val ld_bias_completed = Bool()
val ld_input_completed = Bool()
val ld_weights_completed = Bool()
val ex_completed = Bool()
val st_completed = Bool()
def all_completed(dummy: Int=0): Bool = ld_bias_completed && ld_input_completed && ld_weights_completed && ex_completed && st_completed
val a_addr_start = UInt(log2Up(max_addr).W)
val b_addr_end = UInt(log2Up(max_addr+1).W)
def derived_params(dummy: Int=0): LoopConvDerivedParams = {
import outer_bounds.{stride, kernel_dilation}
import inner_bounds.{batches, pochs, orows, ocols, krows, kcols, upad, dpad, lpad, rpad, kchs}
val result = Wire(new LoopConvDerivedParams(large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth))
result.ochs := pochs
val dilated_krows = krows + (kernel_dilation - 1.U)*(krows - 1.U)
val dilated_kcols = kcols + (kernel_dilation - 1.U)*(kcols - 1.U)
val irows_without_dilation = orows * stride +& dilated_krows -& 1.U
val icols_without_dilation = ocols * stride +& dilated_kcols -& 1.U
val irows_unpadded_without_dilation = irows_without_dilation -& upad -& dpad
val icols_unpadded_without_dilation = icols_without_dilation -& lpad -& rpad
def undilated(x: UInt): UInt = (x +& input_dilated) >> input_dilated
val irows_unpadded = undilated(irows_unpadded_without_dilation)
val icols_unpadded = undilated(icols_unpadded_without_dilation)
result.irows := Mux(input_dilated, irows_unpadded +& undilated(upad) +& undilated(dpad), irows_without_dilation)
result.icols := Mux(input_dilated, icols_unpadded +& undilated(lpad) +& undilated(rpad), icols_without_dilation)
result.irows_unpadded := irows_unpadded
result.icols_unpadded := icols_unpadded
result.ichs := kchs
result.out_channels_per_bank := result.ochs / block_size.U(result.ochs.getWidth.W) +& (result.ochs % block_size.U =/= 0.U)
result.in_channels_per_bank := result.ichs / block_size.U(result.ochs.getWidth.W) +& (result.ichs % block_size.U =/= 0.U)
result.bias_spad_stride := batches * orows * ocols
result.input_spad_stride := Mux(trans_input_3120,
result.ichs * (result.irows >> downsample) * (result.icols >> downsample),
batches * (result.irows >> downsample) * (result.icols >> downsample))
result.weight_spad_stride := Mux(trans_weight_0132, krows * kcols * pochs, krows * kcols * kchs)
// result.ex_overwrite := bias_dram_addr =/= 0.U && no_bias
result
}
def reset(): Unit = {
configured := false.B
running := false.B
ld_bias_started := false.B
ld_input_started := false.B
ld_weights_started := false.B
ex_started := false.B
st_started := false.B
ld_bias_completed := false.B
ld_input_completed := false.B
ld_weights_completed := false.B
ex_completed := false.B
st_completed := false.B
}
}
class LoopConv (block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int,
max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int,
config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2, mvout_rs2_t: MvoutRs2,
config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs,
has_training_convs: Boolean, has_max_pool: Boolean, has_first_layer_optimizations: Boolean,
has_dw_convs: Boolean)
(implicit p: Parameters) extends Module {
val large_iterator_bitwidth = 16
val small_iterator_bitwidth = 16 // 8
val tiny_iterator_bitwidth = 16 // 4
val max_block_len = (dma_max_bytes / (block_size * (input_w / 8))) max 1
val max_block_len_acc = (dma_max_bytes / (block_size * (acc_w / 8))) max 1
val io = IO(new Bundle {
val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size)))
val out = Decoupled(new GemminiCmd(reservation_station_size))
val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W))
val st_completed = Input(UInt(log2Up(reservation_station_size+1).W))
val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W))
val busy = Output(Bool())
})
// Create states
val concurrent_loops = 2
val loops = Reg(Vec(concurrent_loops, new LoopConvState(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr)))
val head_loop_id = RegInit(0.U(log2Up(concurrent_loops).W))
val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available
val head_loop = loops(head_loop_id)
val tail_loop = loops(tail_loop_id)
val loop_configured = loops.map(_.configured).reduce(_ || _)
val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id)
val loop_being_configured = loops(loop_being_configured_id)
// Create inner modules
val latency = 2
val ld_bias = Module(new LoopConvLdBias(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, acc_w, max_block_len_acc, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t))
val ld_input = Module(new LoopConvLdInput(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t))
val ld_weights = Module(new LoopConvLdWeight(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, input_w, max_block_len, concurrent_loops, latency, config_mvin_rs1_t, mvin_rs2_t))
val ex = Module(new LoopConvExecute(block_size, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, latency, config_ex_rs1_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t))
val st = Module(new LoopConvSt(block_size, coreMaxAddrBits, large_iterator_bitwidth, small_iterator_bitwidth, tiny_iterator_bitwidth, max_acc_addr, input_w, concurrent_loops, latency, config_mvout_rs2_t, mvout_rs2_t))
// Create command queue
val cmd = Queue(io.in)
io.busy := cmd.valid || loop_configured
// Create arbiter
val arb = Module(new Arbiter(new RoCCCommand, 5))
arb.io.in(0) <> st.io.cmd
arb.io.in(1) <> ex.io.cmd
arb.io.in(2) <> ld_bias.io.cmd
arb.io.in(3) <> ld_weights.io.cmd
arb.io.in(4) <> ld_input.io.cmd
val unrolled_cmd = arb.io.out
// Create reservation station utilization counters
val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W))
val st_utilization = RegInit(0.U(log2Up(max_sts+1).W))
val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W))
ld_utilization := ld_utilization +& (ld_bias.io.cmd.fire || ld_weights.io.cmd.fire || ld_input.io.cmd.fire) -& io.ld_completed
st_utilization := st_utilization +& st.io.cmd.fire -& io.st_completed
ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed
assert(ld_utilization >= io.ld_completed, "ld utilization underflow")
assert(st_utilization >= io.st_completed, "st utilization underflow")
assert(ex_utilization >= io.ex_completed, "ex utilization underflow")
// Wire up unrolled command output
val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_CONV_WS
val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_CONV_WS_CONFIG_1 && cmd.bits.cmd.inst.funct <= LOOP_CONV_WS_CONFIG_6
val is_loop_cmd = is_loop_run_cmd || is_loop_config_cmd
io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd)
io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this
io.out.bits.rob_id := DontCare
io.out.bits.from_matmul_fsm := Mux(loop_configured, false.B, cmd.bits.from_matmul_fsm)
io.out.bits.from_conv_fsm := Mux(loop_configured, true.B, cmd.bits.from_conv_fsm)
io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd)
cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready)
arb.io.out.ready := io.out.ready
// Wire up waiting-for-loads signals
val ex_is_waiting_for_loads = loops(ex.io.loop_id).ex_started && !loops(ex.io.loop_id).ex_completed &&
!(loops(ex.io.loop_id).ld_input_completed && loops(ex.io.loop_id).ld_weights_completed &&
loops(ex.io.loop_id).ld_bias_completed)
ld_bias.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_bias.io.loop_id =/= ex.io.loop_id
ld_weights.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_weights.io.loop_id =/= ex.io.loop_id
ld_input.io.wait_for_prev_loop := ex_is_waiting_for_loads && ld_input.io.loop_id =/= ex.io.loop_id
// Wire up overloaded signals
ld_bias.io.rob_overloaded := ld_utilization >= max_lds.U
ld_input.io.rob_overloaded := ld_utilization >= max_lds.U
ld_weights.io.rob_overloaded := ld_utilization >= max_lds.U
ex.io.rob_overloaded := ex_utilization >= max_exs.U
st.io.rob_overloaded := st_utilization >= max_sts.U
// Wire up iterator inputs
ex.io.lda_completed := (ld_input.io.loop_id =/= ex.io.loop_id) || ld_input.io.idle
ex.io.ldb_completed := (ld_weights.io.loop_id =/= ex.io.loop_id) || ld_weights.io.idle
ex.io.ldd_completed := (ld_bias.io.loop_id =/= ex.io.loop_id) || ld_bias.io.idle
st.io.ex_completed := (ex.io.loop_id =/= st.io.loop_id) || ex.io.idle
// Create config registers
when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) {
switch (cmd.bits.cmd.inst.funct) {
is (LOOP_CONV_WS_CONFIG_1) {
loop_being_configured.outer_bounds.out_channels := cmd.bits.cmd.rs1(63, 48)
loop_being_configured.outer_bounds.in_channels := cmd.bits.cmd.rs1(47, 32)
loop_being_configured.outer_bounds.in_row_dim := cmd.bits.cmd.rs1(31, 16)
loop_being_configured.outer_bounds.batch_size := cmd.bits.cmd.rs1(15, 0)
loop_being_configured.outer_bounds.padding := cmd.bits.cmd.rs2(63, 56)
loop_being_configured.outer_bounds.stride := cmd.bits.cmd.rs2(55, 48)
loop_being_configured.outer_bounds.out_col_dim := cmd.bits.cmd.rs2(47, 32)
loop_being_configured.outer_bounds.pool_out_row_dim := cmd.bits.cmd.rs2(31, 16)
loop_being_configured.outer_bounds.out_row_dim := cmd.bits.cmd.rs2(15, 0)
}
is (LOOP_CONV_WS_CONFIG_2) {
loop_being_configured.outer_bounds.kernel_dim := cmd.bits.cmd.rs1(63, 48)
loop_being_configured.outer_bounds.pool_out_col_dim := cmd.bits.cmd.rs1(47, 32)
loop_being_configured.outer_bounds.pool_size := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(31, 16))
loop_being_configured.outer_bounds.pool_stride := (if (!has_max_pool) 1.U else cmd.bits.cmd.rs1(15, 8))
loop_being_configured.outer_bounds.pool_padding := (if (!has_max_pool) 0.U else cmd.bits.cmd.rs1(7, 0))
loop_being_configured.inner_bounds.batches := cmd.bits.cmd.rs2(63, 48)
loop_being_configured.inner_bounds.porows := cmd.bits.cmd.rs2(47, 32)
loop_being_configured.inner_bounds.pocols := cmd.bits.cmd.rs2(31, 16)
loop_being_configured.inner_bounds.pochs := cmd.bits.cmd.rs2(15, 0)
}
is (LOOP_CONV_WS_CONFIG_3) {
loop_being_configured.inner_bounds.krows := cmd.bits.cmd.rs1(63, 48)
loop_being_configured.inner_bounds.kcols := cmd.bits.cmd.rs1(47, 32)
loop_being_configured.inner_bounds.kchs := cmd.bits.cmd.rs1(31, 16)
loop_being_configured.inner_bounds.lpad := cmd.bits.cmd.rs1(15, 0)
loop_being_configured.inner_bounds.rpad := cmd.bits.cmd.rs2(63, 48)
loop_being_configured.inner_bounds.upad := cmd.bits.cmd.rs2(47, 32)
loop_being_configured.inner_bounds.dpad := cmd.bits.cmd.rs2(31, 24)
loop_being_configured.inner_bounds.plpad := cmd.bits.cmd.rs2(23, 16)
loop_being_configured.outer_bounds.in_col_dim := cmd.bits.cmd.rs2(15, 0)
}
is (LOOP_CONV_WS_CONFIG_4) {
loop_being_configured.inner_bounds.orows := cmd.bits.cmd.rs1(63, 48)
loop_being_configured.inner_bounds.prad := cmd.bits.cmd.rs1(47, 32)
loop_being_configured.inner_bounds.pupad := cmd.bits.cmd.rs1(31, 21)
loop_being_configured.inner_bounds.pdpad := cmd.bits.cmd.rs1(20, 10)
loop_being_configured.outer_bounds.kernel_dilation := cmd.bits.cmd.rs1(9, 0)
loop_being_configured.inner_bounds.ocols := cmd.bits.cmd.rs2(15, 0)
loop_being_configured.outer_bounds.in_stride := cmd.bits.cmd.rs2(63, 48)
loop_being_configured.outer_bounds.weight_stride := cmd.bits.cmd.rs2(47, 32)
loop_being_configured.outer_bounds.out_stride := cmd.bits.cmd.rs2(31, 16)
}
is (LOOP_CONV_WS_CONFIG_5) {
loop_being_configured.weights_dram_addr := cmd.bits.cmd.rs1
loop_being_configured.output_dram_addr := cmd.bits.cmd.rs2
}
is (LOOP_CONV_WS_CONFIG_6) {
loop_being_configured.bias_dram_addr := cmd.bits.cmd.rs1
loop_being_configured.input_dram_addr := cmd.bits.cmd.rs2
}
is (LOOP_CONV_WS) {
loop_being_configured.no_bias := cmd.bits.cmd.rs1(0)
// TODO we added a default value for max_pixels_per_row just to maintain backwards compatibility. we should deprecate and remove it later
val config_max_pixels_per_row = cmd.bits.cmd.rs1(15, 8)
loop_being_configured.max_pixels_per_row := Mux(
!has_first_layer_optimizations.B || config_max_pixels_per_row === 0.U,
1.U, config_max_pixels_per_row)
loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18)
loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16)
loop_being_configured.wrot180 := has_training_convs.B && cmd.bits.cmd.rs1(1)
loop_being_configured.input_dilated := has_training_convs.B && cmd.bits.cmd.rs2(2)
loop_being_configured.trans_output_1203 := has_training_convs.B && cmd.bits.cmd.rs1(2)
loop_being_configured.trans_weight_1203 := has_training_convs.B && cmd.bits.cmd.rs1(3)
loop_being_configured.trans_weight_0132 := has_training_convs.B && cmd.bits.cmd.rs1(4)
loop_being_configured.trans_input_3120 := has_training_convs.B && cmd.bits.cmd.rs1(5)
loop_being_configured.dw := has_dw_convs.B && cmd.bits.cmd.rs1(6)
loop_being_configured.no_pool := !has_max_pool.B || cmd.bits.cmd.rs2(0)
loop_being_configured.activation := cmd.bits.cmd.rs2(4,3)
loop_being_configured.downsample := cmd.bits.cmd.rs2(1)
loop_being_configured.configured := true.B
// assert(!loop_being_configured.input_dilated || loop_being_configured.outer_bounds.stride === 1.U)
// assert(!loop_being_configured.downsample || (loop_being_configured.outer_bounds.kernel_dim === 1.U && loop_being_configured.outer_bounds.stride === 2.U)) // TODO add the rest of the conditions that must be true for "downsample" to be enabled
}
}
}
// Wire up request signals
val ld_bias_addr_start = RegInit(0.U(log2Up(max_acc_addr).W))
val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W))
val st_addr_start = RegInit(0.U(log2Up(max_acc_addr).W))
val loop_requesting_ld_bias_id = Mux(head_loop.ld_bias_started, tail_loop_id, head_loop_id)
val loop_requesting_ld_bias = loops(loop_requesting_ld_bias_id)
ld_bias.io.req.bits.outer_bounds := loop_requesting_ld_bias.outer_bounds
ld_bias.io.req.bits.inner_bounds := loop_requesting_ld_bias.inner_bounds
ld_bias.io.req.bits.derived_params := loop_requesting_ld_bias.derived_params()
ld_bias.io.req.bits.addr_start := ld_bias_addr_start
ld_bias.io.req.bits.dram_addr := loop_requesting_ld_bias.bias_dram_addr
ld_bias.io.req.bits.no_bias := loop_requesting_ld_bias.no_bias
ld_bias.io.req.bits.loop_id := loop_requesting_ld_bias_id
ld_bias.io.req.valid := !loop_requesting_ld_bias.ld_bias_started && loop_requesting_ld_bias.configured
when (ld_bias.io.req.fire) {
loop_requesting_ld_bias.running := true.B
loop_requesting_ld_bias.ld_bias_started := true.B
// when (loop_requesting_ld_bias.bias_dram_addr =/= 0.U) {
when (loop_requesting_ld_bias.output_dram_addr =/= 0.U) {
ld_bias_addr_start := floorAdd(ld_bias_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U)
}
}
val loop_requesting_ld_input_id = Mux(head_loop.ld_input_started, tail_loop_id, head_loop_id)
val loop_requesting_ld_input = loops(loop_requesting_ld_input_id)
ld_input.io.req.bits.outer_bounds := loop_requesting_ld_input.outer_bounds
ld_input.io.req.bits.inner_bounds := loop_requesting_ld_input.inner_bounds
ld_input.io.req.bits.derived_params := loop_requesting_ld_input.derived_params()
ld_input.io.req.bits.addr_start := Mux(loop_requesting_ld_input.a_ex_spad_id === 0.U, loop_requesting_ld_input.a_addr_start, (loop_requesting_ld_input.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U)
ld_input.io.req.bits.dram_addr := loop_requesting_ld_input.input_dram_addr
ld_input.io.req.bits.downsample := loop_requesting_ld_input.downsample
ld_input.io.req.bits.max_pixels_per_row := loop_requesting_ld_input.max_pixels_per_row
ld_input.io.req.bits.input_dilated := loop_requesting_ld_input.input_dilated
ld_input.io.req.bits.trans_input_3120 := loop_requesting_ld_input.trans_input_3120
ld_input.io.req.bits.loop_id := loop_requesting_ld_input_id
ld_input.io.req.valid := !loop_requesting_ld_input.ld_input_started && loop_requesting_ld_input.configured
when (ld_input.io.req.fire) {
loop_requesting_ld_input.running := true.B
loop_requesting_ld_input.ld_input_started := true.B
}
val loop_requesting_ld_weights_id = Mux(head_loop.ld_weights_started, tail_loop_id, head_loop_id)
val loop_requesting_ld_weights = loops(loop_requesting_ld_weights_id)
ld_weights.io.req.bits.outer_bounds := loop_requesting_ld_weights.outer_bounds
ld_weights.io.req.bits.inner_bounds := loop_requesting_ld_weights.inner_bounds
ld_weights.io.req.bits.derived_params := loop_requesting_ld_weights.derived_params()
ld_weights.io.req.bits.addr_end := Mux(loop_requesting_ld_weights.b_ex_spad_id === 0.U, loop_requesting_ld_weights.b_addr_end, (loop_requesting_ld_weights.b_ex_spad_id) * (max_addr / concurrent_loops).U)
ld_weights.io.req.bits.dram_addr := loop_requesting_ld_weights.weights_dram_addr
ld_weights.io.req.bits.trans_weight_1203 := loop_requesting_ld_weights.trans_weight_1203
ld_weights.io.req.bits.trans_weight_0132 := loop_requesting_ld_weights.trans_weight_0132
ld_weights.io.req.bits.dw := loop_requesting_ld_weights.dw
ld_weights.io.req.bits.loop_id := loop_requesting_ld_weights_id
ld_weights.io.req.valid := !loop_requesting_ld_weights.ld_weights_started && loop_requesting_ld_weights.configured
when (ld_weights.io.req.fire) {
loop_requesting_ld_weights.running := true.B
loop_requesting_ld_weights.ld_weights_started := true.B
}
val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id)
val loop_requesting_ex = loops(loop_requesting_ex_id)
ex.io.req.bits.outer_bounds := loop_requesting_ex.outer_bounds
ex.io.req.bits.inner_bounds := loop_requesting_ex.inner_bounds
ex.io.req.bits.derived_params := loop_requesting_ex.derived_params()
ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U)
ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U)
ex.io.req.bits.c_addr_start := ex_c_addr_start
ex.io.req.bits.wrot180 := loop_requesting_ex.wrot180
ex.io.req.bits.downsample := loop_requesting_ex.downsample
ex.io.req.bits.max_pixels_per_row := loop_requesting_ex.max_pixels_per_row
ex.io.req.bits.input_dilated := loop_requesting_ex.input_dilated
ex.io.req.bits.trans_weight_0132 := loop_requesting_ex.trans_weight_0132
ex.io.req.bits.trans_input_3120 := loop_requesting_ex.trans_input_3120
ex.io.req.bits.loop_id := loop_requesting_ex_id
ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.ld_bias_started &&
loop_requesting_ex.ld_input_started && loop_requesting_ex.ld_weights_started && loop_requesting_ex.configured
when (ex.io.req.fire) {
loop_requesting_ex.running := true.B
loop_requesting_ex.ex_started := true.B
when (loop_requesting_ex.output_dram_addr =/= 0.U) {
ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U)
}
}
val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id)
val loop_requesting_st = loops(loop_requesting_st_id)
st.io.req.bits.outer_bounds := loop_requesting_st.outer_bounds
st.io.req.bits.inner_bounds := loop_requesting_st.inner_bounds
st.io.req.bits.derived_params := loop_requesting_st.derived_params()
st.io.req.bits.addr_start := st_addr_start
st.io.req.bits.dram_addr := loop_requesting_st.output_dram_addr
st.io.req.bits.no_pool := loop_requesting_st.no_pool
st.io.req.bits.activation := loop_requesting_st.activation
st.io.req.bits.trans_output_1203 := loop_requesting_st.trans_output_1203
st.io.req.bits.loop_id := loop_requesting_st_id
st.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured
when (st.io.req.fire) {
loop_requesting_st.running := true.B
loop_requesting_st.st_started := true.B
when (loop_requesting_st.output_dram_addr =/= 0.U) {
st_addr_start := floorAdd(st_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U)
}
}
// Handle completed signals
when (ld_bias.io.idle && loops(ld_bias.io.loop_id).running && loops(ld_bias.io.loop_id).ld_bias_started) {
loops(ld_bias.io.loop_id).ld_bias_completed := true.B
}
when (ld_input.io.idle && loops(ld_input.io.loop_id).running && loops(ld_input.io.loop_id).ld_input_started) {
loops(ld_input.io.loop_id).ld_input_completed := true.B
}
when (ld_weights.io.idle && loops(ld_weights.io.loop_id).running && loops(ld_weights.io.loop_id).ld_weights_started) {
loops(ld_weights.io.loop_id).ld_weights_completed := true.B
}
when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) {
loops(ex.io.loop_id).ex_completed := true.B
}
when (st.io.idle && loops(st.io.loop_id).running && loops(st.io.loop_id).st_started) {
loops(st.io.loop_id).st_completed := true.B
}
when (head_loop.running && head_loop.all_completed()) {
head_loop.reset()
head_loop_id := ~head_loop_id
}
// Resets
when (reset.asBool) {
loops.zipWithIndex.foreach { case (l, i) =>
l.reset()
l.a_addr_start := (i * (max_addr / concurrent_loops)).U
l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U
}
}
}
object LoopConv {
def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt,
block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int,
max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int,
config_mvin_rs1_t: ConfigMvinRs1, mvin_rs2_t: MvinRs2, config_mvout_rs2_t: ConfigMvoutRs2,
mvout_rs2_t: MvoutRs2, config_ex_rs1_t: ConfigExRs1, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, has_training_convs: Boolean, has_max_pool: Boolean,
has_first_layer_optimizations: Boolean, has_dw_convs: Boolean)
(implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = {
val mod = Module(new LoopConv(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts,
max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes,
config_mvin_rs1_t, mvin_rs2_t, config_mvout_rs2_t, mvout_rs2_t, config_ex_rs1_t, preload_rs1_t, preload_rs2_t,
compute_rs1_t, compute_rs2_t, has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs))
mod.io.in <> in
mod.io.ld_completed := ld_completed
mod.io.st_completed := st_completed
mod.io.ex_completed := ex_completed
(mod.io.out, mod.io.busy)
}
def castDramOffset(dram_offset: UInt): UInt = {
// Cast dram offsets to 32 bits max
dram_offset & "hFFFFFFFF".U
}
}
File LoopMatmul.scala:
package gemmini
import chisel3._
import chisel3.util._
import chisel3.experimental._
import freechips.rocketchip.tile.RoCCCommand
import org.chipsalliance.cde.config.Parameters
import GemminiISA._
import LocalAddr._
import Util._
// LdA
class LoopMatmulLdAReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle {
val max_i = UInt(iterator_bitwidth.W)
val max_k = UInt(iterator_bitwidth.W)
val pad_i = UInt(log2Up(block_size).W)
val pad_k = UInt(log2Up(block_size).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val dram_stride = UInt(coreMaxAddrBits.W)
val transpose = Bool()
val addr_start = UInt(log2Up(max_addr).W)
val loop_id = UInt(log2Up(concurrent_loops).W)
val is_resadd = Bool()
}
class LoopMatmulLdA(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_addr: Int, input_w: Int,
max_block_len: Int, concurrent_loops: Int, mvin_rs2_t: MvinRs2)
(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopMatmulLdAReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val i = Output(UInt(iterator_bitwidth.W))
val k = Output(UInt(iterator_bitwidth.W))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, ld = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopMatmulLdAReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops))
val i = Reg(UInt(iterator_bitwidth.W))
val k = Reg(UInt(iterator_bitwidth.W))
val row_iterator = Mux(req.transpose, k, i)
val col_iterator = Mux(req.transpose, i, k)
val max_row_iterator = Mux(req.transpose, req.max_k, req.max_i)
val max_col_iterator = Mux(req.transpose, req.max_i, req.max_k)
val row_pad = Mux(req.transpose, req.pad_k, req.pad_i)
val col_pad = Mux(req.transpose, req.pad_i, req.pad_k)
val max_col_dim = Mux(req.transpose, req.max_i, req.max_k)
val max_blocks = Mux(max_col_dim <= max_block_len.U, max_col_dim, max_block_len.U)
val sp_addr_start = req.addr_start
val dram_offset = (row_iterator * req.dram_stride + col_iterator) * block_size.U * (input_w/8).U
val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset)
val sp_addr = sp_addr_start + (row_iterator * max_col_iterator + col_iterator) * block_size.U
val blocks = Mux(col_iterator + max_blocks <= max_col_iterator, max_blocks, max_col_iterator-col_iterator)
val cols = (blocks * block_size.U) - Mux(col_iterator + blocks >= max_col_iterator, col_pad, 0.U)
val rows = block_size.U - Mux(row_iterator === max_row_iterator-1.U, row_pad, 0.U)
val mvin_cmd = Wire(new RoCCCommand)
mvin_cmd := DontCare
mvin_cmd.inst.funct := LOAD_CMD
mvin_cmd.rs1 := dram_addr
val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType)
mvin_cmd_rs2 := DontCare
mvin_cmd_rs2.num_rows := rows.asUInt
mvin_cmd_rs2.num_cols := cols.asUInt
mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, sp_addr)
mvin_cmd.rs2 := mvin_cmd_rs2.asUInt
when(req.is_resadd){
mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, sp_addr, accumulate = false.B, read_full = false.B)
}
io.req.ready := state === idle
io.i := i
io.k := k
io.idle := state === idle
io.cmd.valid := state =/= idle && !io.rob_overloaded && req.dram_addr =/= 0.U
io.cmd.bits := mvin_cmd
io.loop_id := req.loop_id
when(req.dram_addr === 0.U){
state := idle
}.elsewhen(io.cmd.fire) {
// The order here is k, j, i
val i_blocks = Mux(req.transpose, max_blocks, 1.U)
val k_blocks = Mux(req.transpose, 1.U, max_blocks)
val next_i = floorAdd(i, i_blocks, req.max_i)
val next_k = floorAdd(k, k_blocks, req.max_k, next_i === 0.U)
i := next_i
k := next_k
when (next_i === 0.U && next_k === 0.U) {
state := idle
}
}
when (io.req.fire) {
req := io.req.bits
state := ld
i := 0.U
k := 0.U
}
}
// LdB
class LoopMatmulLdBReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_addr: Int, val concurrent_loops: Int) extends Bundle {
val max_k = UInt(iterator_bitwidth.W)
val max_j = UInt(iterator_bitwidth.W)
val pad_k = UInt(log2Up(block_size).W)
val pad_j = UInt(log2Up(block_size).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val dram_stride = UInt(coreMaxAddrBits.W)
val transpose = Bool()
val addr_end = UInt(log2Up(max_addr+1).W)
val loop_id = UInt(log2Up(concurrent_loops).W)
val is_resadd = Bool()
}
class LoopMatmulLdB(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_addr: Int, input_w: Int,
max_block_len: Int, concurrent_loops: Int, mvin_rs2_t: MvinRs2)
(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopMatmulLdBReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val k = Output(UInt(iterator_bitwidth.W))
val j = Output(UInt(iterator_bitwidth.W))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, ld = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopMatmulLdBReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, concurrent_loops))
val k = Reg(UInt(iterator_bitwidth.W))
val j = Reg(UInt(iterator_bitwidth.W))
val row_iterator = Mux(req.transpose, j, k)
val col_iterator = Mux(req.transpose, k, j)
val max_row_iterator = Mux(req.transpose, req.max_j, req.max_k)
val max_col_iterator = Mux(req.transpose, req.max_k, req.max_j)
val row_pad = Mux(req.transpose, req.pad_j, req.pad_k)
val col_pad = Mux(req.transpose, req.pad_k, req.pad_j)
val max_col_dim = Mux(req.transpose, req.max_k, req.max_j)
val max_blocks = Mux(max_col_dim <= max_block_len.U, max_col_dim, max_block_len.U)
val sp_addr_start = Mux(req.is_resadd, req.addr_end, req.addr_end - req.max_k * req.max_j * block_size.U)
val dram_offset = (row_iterator * req.dram_stride + col_iterator) * block_size.U * (input_w/8).U
val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset)
val sp_addr = sp_addr_start + (row_iterator * max_col_iterator + col_iterator) * block_size.U
val blocks = Mux(col_iterator + max_blocks <= max_col_iterator, max_blocks, max_col_iterator-col_iterator)
val cols = (blocks * block_size.U) - Mux(col_iterator + blocks >= max_col_iterator, col_pad, 0.U)
val rows = block_size.U - Mux(max_row_iterator === max_row_iterator-1.U, row_pad, 0.U)
val mvin_cmd = Wire(new RoCCCommand)
mvin_cmd := DontCare
mvin_cmd.inst.funct := LOAD2_CMD
mvin_cmd.rs1 := dram_addr
val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType)
mvin_cmd_rs2 := DontCare
mvin_cmd_rs2.num_rows := rows.asUInt
mvin_cmd_rs2.num_cols := cols.asUInt
mvin_cmd_rs2.local_addr := cast_to_sp_addr(mvin_cmd_rs2.local_addr, sp_addr)
mvin_cmd.rs2 := mvin_cmd_rs2.asUInt
when (req.is_resadd){
mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, sp_addr, accumulate = true.B, read_full = false.B)
}
io.req.ready := state === idle
io.k := k
io.j := j
io.idle := state === idle
io.cmd.valid := state =/= idle && !io.rob_overloaded && req.dram_addr =/= 0.U
io.cmd.bits := mvin_cmd
io.loop_id := req.loop_id
when(req.dram_addr === 0.U){
state := idle
}.elsewhen(io.cmd.fire) {
// The order here is k, j, i
val j_blocks = Mux(req.transpose, 1.U, max_blocks)
val k_blocks = Mux(req.transpose, max_blocks, 1.U)
val next_j = floorAdd(j, j_blocks, req.max_j)
val next_k = floorAdd(k, k_blocks, req.max_k, next_j === 0.U)
j := next_j
k := next_k
when (next_j === 0.U && next_k === 0.U) {
state := idle
}
}
when (io.req.fire) {
req := io.req.bits
state := ld
j := 0.U
k := 0.U
}
}
// LdD
class LoopMatmulLdDReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val max_j = UInt(iterator_bitwidth.W)
val max_i = UInt(iterator_bitwidth.W)
val pad_j = UInt(log2Up(block_size).W)
val pad_i = UInt(log2Up(block_size).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val dram_stride = UInt(coreMaxAddrBits.W)
val low_d = Bool()
val addr_start = UInt(log2Up(max_acc_addr).W)
val loop_id = UInt(log2Up(concurrent_loops).W)
}
class LoopMatmulLdD(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int,
acc_w: Int, max_block_len: Int, max_block_len_acc: Int, concurrent_loops: Int, mvin_rs2_t: MvinRs2)
(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopMatmulLdDReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, ld = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopMatmulLdDReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops))
val max_blocks = Mux(req.low_d, Mux(req.max_j <= max_block_len.U, req.max_j, max_block_len.U),
Mux(req.max_j <= max_block_len_acc.U, req.max_j, max_block_len_acc.U))
val j = Reg(UInt(iterator_bitwidth.W))
val i = Reg(UInt(iterator_bitwidth.W))
val acc_addr_start = req.addr_start
val dram_offset = Mux(req.low_d, (i * req.dram_stride + j) * block_size.U * (input_w/8).U,
(i * req.dram_stride + j) * block_size.U * (acc_w/8).U)
val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset)
val sp_addr = acc_addr_start + (i * req.max_j + j) * block_size.U
val blocks = Mux(j + max_blocks <= req.max_j, max_blocks, req.max_j-j)
val cols = (blocks * block_size.U) - Mux(j + blocks >= req.max_j, req.pad_j, 0.U)
val rows = block_size.U - Mux(i === req.max_i-1.U, req.pad_i, 0.U)
val mvin_cmd = Wire(new RoCCCommand)
mvin_cmd := DontCare
mvin_cmd.inst.funct := LOAD3_CMD
mvin_cmd.rs1 := dram_addr
val mvin_cmd_rs2 = Wire(mvin_rs2_t.cloneType)
mvin_cmd_rs2 := DontCare
mvin_cmd_rs2.num_rows := rows.asUInt
mvin_cmd_rs2.num_cols := cols.asUInt
mvin_cmd_rs2.local_addr := cast_to_acc_addr(mvin_cmd_rs2.local_addr, sp_addr, accumulate = false.B, read_full = false.B)
mvin_cmd.rs2 := mvin_cmd_rs2.asUInt
io.req.ready := state === idle
io.idle := state === idle
// The order here is k, j, i
io.cmd.valid := state =/= idle && !io.rob_overloaded && req.dram_addr =/= 0.U
io.cmd.bits := mvin_cmd
io.loop_id := req.loop_id
when (req.dram_addr === 0.U) {
state := idle
}.elsewhen (io.cmd.fire) {
// The order here is k, j, i
val next_i = floorAdd(i, 1.U, req.max_i)
val next_j = floorAdd(j, max_blocks, req.max_j, next_i === 0.U)
i := next_i
j := next_j
when (next_i === 0.U && next_j === 0.U) {
state := idle
}
}
when (io.req.fire) {
req := io.req.bits
state := ld
j := 0.U
i := 0.U
}
}
// Compute
class LoopMatmulExecuteReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_addr: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val max_j = UInt(iterator_bitwidth.W)
val max_k = UInt(iterator_bitwidth.W)
val max_i = UInt(iterator_bitwidth.W)
val pad_j = UInt(log2Up(block_size).W)
val pad_k = UInt(log2Up(block_size).W)
val pad_i = UInt(log2Up(block_size).W)
val a_tranpose = Bool()
val b_tranpose = Bool()
val accumulate = Bool()
val a_addr_start = UInt(log2Up(max_addr).W)
val b_addr_end = UInt(log2Up(max_addr+1).W)
val c_addr_start = UInt(log2Up(max_acc_addr).W)
val loop_id = UInt(log2Up(concurrent_loops).W)
val skip = Bool()
}
class LoopMatmulExecute(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_addr: Int, max_acc_addr: Int, concurrent_loops: Int,
preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs)
(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopMatmulExecuteReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val k = Output(UInt(iterator_bitwidth.W))
val j = Output(UInt(iterator_bitwidth.W))
val i = Output(UInt(iterator_bitwidth.W))
val ld_ka = Input(UInt(iterator_bitwidth.W))
val ld_kb = Input(UInt(iterator_bitwidth.W))
val ld_j = Input(UInt(iterator_bitwidth.W))
val ld_i = Input(UInt(iterator_bitwidth.W))
val lda_completed = Input(Bool())
val ldb_completed = Input(Bool())
val ldd_completed = Input(Bool())
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, pre, comp = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopMatmulExecuteReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops))
val c_addr_start = /*(BigInt(1) << 31).U |*/ req.c_addr_start
val b_addr_start = req.b_addr_end - req.max_k * req.max_j * block_size.U
val k = Reg(UInt(iterator_bitwidth.W))
val j = Reg(UInt(iterator_bitwidth.W))
val i = Reg(UInt(iterator_bitwidth.W))
val a_row = Mux(req.a_tranpose, k, i)
val a_col = Mux(req.a_tranpose, i, k)
val b_row = Mux(req.b_tranpose, j, k)
val b_col = Mux(req.b_tranpose, k, j)
val a_max_col = Mux(req.a_tranpose, req.max_i, req.max_k)
val b_max_col = Mux(req.b_tranpose, req.max_k, req.max_j)
val a_addr = req.a_addr_start + (a_row * a_max_col + a_col) * block_size.U
val b_addr = b_addr_start + (b_row * b_max_col + b_col) * block_size.U
val c_addr = c_addr_start + (i * req.max_j + j) * block_size.U
val a_cols = block_size.U - Mux(k === req.max_k - 1.U, req.pad_k, 0.U)
val a_rows = block_size.U - Mux(i === req.max_i - 1.U, req.pad_i, 0.U)
val b_cols = block_size.U - Mux(j === req.max_j - 1.U, req.pad_j, 0.U)
val b_rows = block_size.U - Mux(k === req.max_k - 1.U, req.pad_k, 0.U)
val c_cols = block_size.U - Mux(j === req.max_j - 1.U, req.pad_j, 0.U)
val c_rows = block_size.U - Mux(i === req.max_i - 1.U, req.pad_i, 0.U)
val pre_cmd = Wire(new RoCCCommand)
pre_cmd := DontCare
pre_cmd.inst.funct := PRELOAD_CMD
val pre_cmd_rs1 = Wire(preload_rs1_t.cloneType)
pre_cmd_rs1 := DontCare
pre_cmd_rs1.num_rows := b_rows.asUInt
pre_cmd_rs1.num_cols := b_cols.asUInt
pre_cmd_rs1.local_addr := Mux(i === 0.U, cast_to_sp_addr(pre_cmd_rs1.local_addr, b_addr),
garbage_addr(pre_cmd_rs1.local_addr))
val pre_cmd_rs2 = Wire(preload_rs2_t.cloneType)
pre_cmd_rs2 := DontCare
pre_cmd_rs2.num_rows := c_rows.asUInt
pre_cmd_rs2.num_cols := c_cols.asUInt
pre_cmd_rs2.local_addr := cast_to_acc_addr(pre_cmd_rs2.local_addr, c_addr, accumulate = req.accumulate || k =/= 0.U, read_full = false.B)
pre_cmd.rs1 := pre_cmd_rs1.asUInt
pre_cmd.rs2 := pre_cmd_rs2.asUInt
val comp_cmd = Wire(new RoCCCommand())
comp_cmd := DontCare
comp_cmd.inst.funct := Mux(i === 0.U, COMPUTE_AND_FLIP_CMD, COMPUTE_AND_STAY_CMD)
val comp_cmd_rs1 = Wire(compute_rs1_t.cloneType)
comp_cmd_rs1 := DontCare
comp_cmd_rs1.num_rows := a_rows.asUInt
comp_cmd_rs1.num_cols := a_cols.asUInt
comp_cmd_rs1.local_addr := cast_to_sp_addr(comp_cmd_rs1.local_addr, a_addr)
val comp_cmd_rs2 = Wire(compute_rs2_t.cloneType)
comp_cmd_rs2 := DontCare
comp_cmd_rs2.num_rows := block_size.U
comp_cmd_rs2.num_cols := block_size.U
comp_cmd_rs2.local_addr := garbage_addr(comp_cmd_rs2.local_addr)
comp_cmd.rs1 := comp_cmd_rs1.asUInt
comp_cmd.rs2 := comp_cmd_rs2.asUInt
io.req.ready := state === idle
io.k := k
io.j := j
io.i := i
io.idle := state === idle
// The order here is k, j, i
val lda_ahead = io.lda_completed || io.ld_ka > k || (io.ld_ka === k && io.ld_i > i)
val ldb_ahead = io.ldb_completed || io.ld_kb > k || (io.ld_ka === k && io.ld_j > j)
val ldd_ahead = io.ldd_completed
val ld_ahead = lda_ahead && ldb_ahead && ldd_ahead
io.cmd.valid := state =/= idle && !io.rob_overloaded && ld_ahead && !req.skip
io.cmd.bits := Mux(state === pre, pre_cmd, comp_cmd)
io.loop_id := req.loop_id
when(req.skip) {
state := idle
}.elsewhen (io.cmd.fire) {
when (state === pre) {
state := comp
}.otherwise {
val next_i = floorAdd(i, 1.U, req.max_i)
val next_j = floorAdd(j, 1.U, req.max_j, next_i === 0.U)
val next_k = floorAdd(k, 1.U, req.max_k, next_j === 0.U && next_i === 0.U)
k := next_k
j := next_j
i := next_i
state := Mux(next_k === 0.U && next_j === 0.U && next_i === 0.U, idle, pre)
}
}
when (io.req.fire) {
req := io.req.bits
state := pre
j := 0.U
k := 0.U
i := 0.U
}
assert(!(state =/= idle && req.a_tranpose && req.b_tranpose))
}
// StC
class LoopMatmulStCReq(val block_size: Int, val coreMaxAddrBits: Int, val iterator_bitwidth: Int, val max_acc_addr: Int, val concurrent_loops: Int) extends Bundle {
val max_k = UInt(iterator_bitwidth.W)
val max_j = UInt(iterator_bitwidth.W)
val max_i = UInt(iterator_bitwidth.W)
val pad_j = UInt(log2Up(block_size).W)
val pad_i = UInt(log2Up(block_size).W)
val dram_addr = UInt(coreMaxAddrBits.W)
val dram_stride = UInt(coreMaxAddrBits.W)
val full_c = Bool()
val act = UInt(Activation.bitwidth.W)
val addr_start = UInt(log2Up(max_acc_addr).W)
val loop_id = UInt(log2Up(concurrent_loops).W)
val is_resadd = Bool()
}
class LoopMatmulStC(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, max_block_len: Int, concurrent_loops: Int, mvout_rs2_t: MvoutRs2)
(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new LoopMatmulStCReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops)))
val cmd = Decoupled(Output(new RoCCCommand))
val ex_k = Input(UInt(iterator_bitwidth.W))
val ex_j = Input(UInt(iterator_bitwidth.W))
val ex_i = Input(UInt(iterator_bitwidth.W))
val ex_completed = Input(Bool())
val j = Output(UInt(iterator_bitwidth.W))
val i = Output(UInt(iterator_bitwidth.W))
val idle = Output(Bool())
val rob_overloaded = Input(Bool())
val loop_id = Output(UInt(log2Up(concurrent_loops).W))
})
object State extends ChiselEnum {
val idle, st, ln_config, ln_st = Value
}
import State._
val state = RegInit(idle)
val req = Reg(new LoopMatmulStCReq(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, concurrent_loops))
val max_blocks = Mux(req.full_c, 1.U, Mux(req.max_j <= max_block_len.U, req.max_j, max_block_len.U))
// Non-normalization-related iterators and calculations
val j = Reg(UInt(iterator_bitwidth.W))
val i = Reg(UInt(iterator_bitwidth.W))
val acc_addr_start = /*(BigInt(1) << 31).U | (req.full_c << 29.U).asUInt |*/ req.addr_start
val dram_offset = Mux(req.full_c, (i * req.dram_stride + j) * block_size.U * (acc_w/8).U,
(i * req.dram_stride + j) * block_size.U * (input_w/8).U)
val dram_addr = req.dram_addr + LoopMatmul.castDramOffset(dram_offset)
val sp_addr = acc_addr_start + (i * req.max_j + j) * block_size.U
val blocks = Mux(j + max_blocks <= req.max_j, max_blocks, req.max_j-j)
val cols = (blocks * block_size.U) - Mux(j + blocks >= req.max_j, req.pad_j, 0.U)
val rows = block_size.U - Mux(i === req.max_i-1.U, req.pad_i, 0.U)
val mvout_cmd = Wire(new RoCCCommand)
mvout_cmd := DontCare
mvout_cmd.inst.funct := STORE_CMD
mvout_cmd.rs1 := dram_addr
val mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType)
mvout_cmd_rs2 := DontCare
mvout_cmd_rs2.num_rows := rows.asUInt
mvout_cmd_rs2.num_cols := cols.asUInt
mvout_cmd_rs2.local_addr := cast_to_acc_addr(mvout_cmd_rs2.local_addr, sp_addr, accumulate = false.B, read_full = req.full_c)
mvout_cmd.rs2 := mvout_cmd_rs2.asUInt
// Layernorm iterators and calculations
val ln_row = Reg(UInt(iterator_bitwidth.W))
val ln_cmd = Reg(UInt(iterator_bitwidth.W))
val ln_stat_id = Reg(UInt(iterator_bitwidth.W))
val NORM_STAT_IDS = 2 // TODO magic number
val ln_norm_cmds = VecInit(VecInit(NormCmd.SUM, NormCmd.MEAN), VecInit(NormCmd.VARIANCE, NormCmd.INV_STDDEV),
VecInit(NormCmd.RESET, NormCmd.RESET))
val sm_norm_cmds = VecInit(VecInit(NormCmd.MAX, NormCmd.MAX), VecInit(NormCmd.SUM_EXP, NormCmd.INV_SUM_EXP),
VecInit(NormCmd.RESET, NormCmd.RESET))
val ln_stat_ids = Mux(rows -& ln_row > NORM_STAT_IDS.U, NORM_STAT_IDS.U, rows -& ln_row)
val ln_r = ln_row +& ln_stat_id
val ln_sp_addr = acc_addr_start +& (i * req.max_j +& j) * block_size.U +& ln_r
val ln_norm_cmd = Mux(j +& max_blocks >= req.max_j,
Mux(req.act === Activation.LAYERNORM, ln_norm_cmds(ln_cmd)(1), sm_norm_cmds(ln_cmd)(1)),
Mux(req.act === Activation.LAYERNORM, ln_norm_cmds(ln_cmd)(0), sm_norm_cmds(ln_cmd)(0)))
// TODO we assume for now that full_C and layernorm aren't true at the same
val ln_dram_offset = ((i * req.dram_stride +& j) * block_size.U +& ln_r * req.dram_stride) * (input_w/8).U
val ln_dram_addr = req.dram_addr + LoopMatmul.castDramOffset(ln_dram_offset)
val ln_config_norm_rs1 = Wire(new GemminiISA.ConfigNormRs1)
ln_config_norm_rs1 := DontCare
ln_config_norm_rs1.set_stats_id_only := 1.U
ln_config_norm_rs1.cmd_type := CONFIG_NORM
ln_config_norm_rs1.norm_stats_id := ln_stat_id
val ln_config_norm = Wire(new RoCCCommand)
ln_config_norm := DontCare
ln_config_norm.inst.funct := CONFIG_CMD
ln_config_norm.rs1 := ln_config_norm_rs1.asUInt
ln_config_norm.rs2 := DontCare
val ln_mvout_cmd = Wire(new RoCCCommand)
ln_mvout_cmd := DontCare
ln_mvout_cmd.inst.funct := STORE_CMD
ln_mvout_cmd.rs1 := ln_dram_addr
val ln_mvout_cmd_rs2 = Wire(mvout_rs2_t.cloneType)
ln_mvout_cmd_rs2 := DontCare
ln_mvout_cmd_rs2.num_rows := 1.U
ln_mvout_cmd_rs2.num_cols := cols.asUInt
ln_mvout_cmd_rs2.local_addr := cast_to_acc_addr(ln_mvout_cmd_rs2.local_addr, ln_sp_addr, accumulate = false.B, read_full = req.full_c)
ln_mvout_cmd_rs2.local_addr.norm_cmd := ln_norm_cmd
ln_mvout_cmd.rs2 := ln_mvout_cmd_rs2.asUInt
io.req.ready := state === idle
io.j := j
io.i := i
io.idle := state === idle
// The order here is k, j, i when not doing LAYERNORM or SOFTMAX
val ex_ahead = WireInit(io.ex_completed ||
((req.act =/= Activation.LAYERNORM) && (req.act =/= Activation.SOFTMAX) &&
(io.ex_k === req.max_k - 1.U &&
(io.ex_j >= j + blocks ||
((io.ex_j === j + blocks - 1.U) && io.ex_i > i)))))
when(req.is_resadd){
ex_ahead := io.ex_completed || (io.ex_i > i || (io.ex_i === i && io.ex_j >= j + blocks))
}
io.cmd.valid := state =/= idle && !io.rob_overloaded && ex_ahead && req.dram_addr =/= 0.U
io.cmd.bits := MuxCase(mvout_cmd, Seq(
(state === ln_config) -> ln_config_norm,
(state === ln_st) -> ln_mvout_cmd,
))
io.loop_id := req.loop_id
when (req.dram_addr === 0.U) {
state := idle
}.elsewhen (io.cmd.fire && state === st) {
// The order here is k, j, i
val next_i = floorAdd(i, 1.U, req.max_i)
val next_j = floorAdd(j, max_blocks, req.max_j, next_i === 0.U)
i := next_i
j := next_j
when (next_i === 0.U && next_j === 0.U) {
state := idle
}
}.elsewhen (io.cmd.fire && state === ln_config) {
state := ln_st
}.elsewhen (io.cmd.fire && state === ln_st) {
val next_j = floorAdd(j, max_blocks, req.max_j)
val next_stat_id = floorAdd(ln_stat_id, 1.U, ln_stat_ids, next_j === 0.U)
val next_cmd = floorAdd(ln_cmd, 1.U, ln_norm_cmds.size.U, next_j === 0.U && next_stat_id === 0.U)
val next_row = floorAdd(ln_row, NORM_STAT_IDS.U, rows, next_j === 0.U && next_stat_id === 0.U && next_cmd === 0.U)
val next_i = floorAdd(i, 1.U, req.max_i,
next_j === 0.U && next_stat_id === 0.U && next_cmd === 0.U && next_row === 0.U)
j := next_j
ln_stat_id := next_stat_id
ln_cmd := next_cmd
ln_row := next_row
i := next_i
when (next_i === 0.U && next_row === 0.U && next_cmd === 0.U && next_stat_id === 0.U && next_j === 0.U) {
state := idle
}.elsewhen (next_j === 0.U) {
state := ln_config
}
}
when (io.req.fire) {
req := io.req.bits
state := Mux((io.req.bits.act === Activation.LAYERNORM) || (io.req.bits.act === Activation.SOFTMAX), ln_config, st)
j := 0.U
i := 0.U
ln_row := 0.U
ln_cmd := 0.U
ln_stat_id := 0.U
}
}
// Combined loop
class LoopMatmulState(val iterator_bitwidth: Int, val coreMaxAddrBits: Int, val max_addr: Int, val max_acc_addr: Int) extends Bundle {
val max_k = UInt(iterator_bitwidth.W)
val max_j = UInt(iterator_bitwidth.W)
val max_i = UInt(iterator_bitwidth.W)
val pad_k = UInt(iterator_bitwidth.W)
val pad_j = UInt(iterator_bitwidth.W)
val pad_i = UInt(iterator_bitwidth.W)
val a_dram_addr = UInt(coreMaxAddrBits.W)
val b_dram_addr = UInt(coreMaxAddrBits.W)
val d_dram_addr = UInt(coreMaxAddrBits.W)
val c_dram_addr = UInt(coreMaxAddrBits.W)
val a_dram_stride = UInt(coreMaxAddrBits.W)
val b_dram_stride = UInt(coreMaxAddrBits.W)
val d_dram_stride = UInt(coreMaxAddrBits.W)
val c_dram_stride = UInt(coreMaxAddrBits.W)
val a_transpose = Bool()
val b_transpose = Bool()
val act = UInt(Activation.bitwidth.W)
val low_d = Bool()
val full_c = Bool()
val ex_accumulate = Bool()
val a_ex_spad_id = UInt(2.W)
val b_ex_spad_id = UInt(2.W)
val configured = Bool()
val running = Bool()
val lda_started = Bool()
val ldb_started = Bool()
val ex_started = Bool()
val ldd_started = Bool()
val st_started = Bool()
val lda_completed = Bool()
val ldb_completed = Bool()
val ex_completed = Bool()
val ldd_completed = Bool()
val st_completed = Bool()
def all_completed(dummy: Int=0): Bool = lda_completed && ldb_completed && ldd_completed && ex_completed && st_completed
val a_addr_start = UInt(log2Up(max_addr).W)
val b_addr_end = UInt(log2Up(max_addr+1).W)
val resadd_addr_start = UInt(log2Up(max_acc_addr).W)
def reset(): Unit = {
configured := false.B
running := false.B
lda_started := false.B
ldb_started := false.B
ex_started := false.B
ldd_started := false.B
st_started := false.B
lda_completed := false.B
ldb_completed := false.B
ex_completed := false.B
ldd_completed := false.B
st_completed := false.B
//is_resadd := false.B
}
}
class LoopMatmul(block_size: Int, coreMaxAddrBits: Int, reservation_station_size: Int, max_lds: Int, max_exs: Int, max_sts: Int,
max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int,
mvin_rs2_t: MvinRs2, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, mvout_rs2_t: MvoutRs2)
(implicit p: Parameters) extends Module {
val iterator_bitwidth = 16
val max_block_len = (dma_max_bytes / (block_size * input_w / 8)) max 1
val max_block_len_acc = (dma_max_bytes / (block_size * acc_w / 8)) max 1
val io = IO(new Bundle {
val in = Flipped(Decoupled(new GemminiCmd(reservation_station_size)))
val out = Decoupled(new GemminiCmd(reservation_station_size))
val ld_completed = Input(UInt(log2Up(reservation_station_size+1).W))
val st_completed = Input(UInt(log2Up(reservation_station_size+1).W))
val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W))
val busy = Output(Bool())
})
// Create states
val concurrent_loops = 2
val loops = Reg(Vec(concurrent_loops, new LoopMatmulState(iterator_bitwidth, coreMaxAddrBits, max_addr, max_acc_addr)))
val head_loop_id = Reg(UInt(log2Up(concurrent_loops).W))
val tail_loop_id = (~head_loop_id).asUInt // This is the loop that we always try to configure if available
val head_loop = loops(head_loop_id)
val tail_loop = loops(tail_loop_id)
val loop_configured = loops.map(_.configured).reduce(_ || _)
val loop_being_configured_id = Mux(head_loop.configured, tail_loop_id, head_loop_id)
val loop_being_configured = loops(loop_being_configured_id)
val is_resadd = RegInit(false.B)
val max_all_addr = if(max_addr > max_acc_addr) max_addr else max_acc_addr
// Create inner modules
val ldA = Module(new LoopMatmulLdA(block_size, coreMaxAddrBits, iterator_bitwidth, max_all_addr, input_w, max_block_len, concurrent_loops, mvin_rs2_t))
val ldB = Module(new LoopMatmulLdB(block_size, coreMaxAddrBits, iterator_bitwidth, max_all_addr, input_w, max_block_len, concurrent_loops, mvin_rs2_t))
val ldD = Module(new LoopMatmulLdD(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, input_w, acc_w, max_block_len, max_block_len_acc, concurrent_loops, mvin_rs2_t))
val ex = Module(new LoopMatmulExecute(block_size, coreMaxAddrBits, iterator_bitwidth, max_addr, max_acc_addr, concurrent_loops, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t))
val stC = Module(new LoopMatmulStC(block_size, coreMaxAddrBits, iterator_bitwidth, max_acc_addr, input_w, acc_w, max_block_len, concurrent_loops, mvout_rs2_t))
// Create command queue
val cmd = Queue(io.in)
io.busy := cmd.valid || loop_configured
// Create ld arbiters
val ldab_arb = Module(new WeightedArbiter(new RoCCCommand(), maxWeightA=255, staticWeightAEnabled=true)) // TODO magic numbers
ldab_arb.io.inA <> ldA.io.cmd
ldab_arb.io.inB <> ldB.io.cmd
val ab_loads_on_same_loop = ldA.io.loop_id === ldB.io.loop_id
val forceA = !ab_loads_on_same_loop && ldA.io.loop_id === head_loop_id
val forceB = !ab_loads_on_same_loop && ldB.io.loop_id === head_loop_id
ldab_arb.io.forceA := Mux(is_resadd, ab_loads_on_same_loop && !ldA.io.idle, forceA)
ldab_arb.io.forceB := Mux(is_resadd, forceB || ldA.io.idle, forceB)
ldab_arb.io.weightA := 0.U
ldab_arb.io.inA_idle := ldA.io.idle
ldab_arb.io.inB_idle := ldB.io.idle
ldab_arb.io.inA_k := ldA.io.k
ldab_arb.io.inA_i := ldA.io.i
ldab_arb.io.inB_k := ldB.io.k
ldab_arb.io.inB_j := ldB.io.j
// Create global arbiter
val arb = Module(new Arbiter(new RoCCCommand(), 4))
arb.io.in(0) <> stC.io.cmd
arb.io.in(1) <> ex.io.cmd
arb.io.in(2) <> ldD.io.cmd
arb.io.in(3) <> ldab_arb.io.out
val unrolled_cmd = arb.io.out
// Create reservation station utilization counters
val ld_utilization = RegInit(0.U(log2Up(max_lds+1).W))
val st_utilization = RegInit(0.U(log2Up(max_sts+1).W))
val ex_utilization = RegInit(0.U(log2Up(max_exs+1).W))
ld_utilization := ld_utilization +& (ldA.io.cmd.fire || ldB.io.cmd.fire || ldD.io.cmd.fire) -& io.ld_completed
st_utilization := st_utilization +& stC.io.cmd.fire -& io.st_completed
ex_utilization := ex_utilization +& ex.io.cmd.fire -& io.ex_completed
assert(ld_utilization >= io.ld_completed, "ld utilization underflow")
assert(st_utilization >= io.st_completed, "st utilization underflow")
assert(ex_utilization >= io.ex_completed, "ex utilization underflow")
// Wire up unrolled command output
val is_loop_run_cmd = cmd.bits.cmd.inst.funct === LOOP_WS
val is_loop_config_cmd = cmd.bits.cmd.inst.funct >= LOOP_WS_CONFIG_BOUNDS && cmd.bits.cmd.inst.funct <= LOOP_WS_CONFIG_STRIDES_DC
val is_loop_cmd = is_loop_run_cmd || is_loop_config_cmd
io.out.bits.cmd := Mux(loop_configured, unrolled_cmd.bits, cmd.bits.cmd)
io.out.bits.cmd.status := cmd.bits.cmd.status // TODO This is not guaranteed to be the correct fix! We must fix this
io.out.bits.rob_id := DontCare
io.out.bits.from_matmul_fsm := Mux(loop_configured, true.B, cmd.bits.from_matmul_fsm)
io.out.bits.from_conv_fsm := Mux(loop_configured, false.B, cmd.bits.from_conv_fsm)
io.out.valid := Mux(loop_configured, unrolled_cmd.valid, cmd.valid && !is_loop_config_cmd && !is_loop_run_cmd)
cmd.ready := Mux(is_loop_cmd, !loop_being_configured.configured, !loop_configured && io.out.ready)
arb.io.out.ready := io.out.ready
// Wire up overloaded signals
ldA.io.rob_overloaded := ld_utilization >= max_lds.U
ldB.io.rob_overloaded := ld_utilization >= max_lds.U
ex.io.rob_overloaded := ex_utilization >= max_exs.U
ldD.io.rob_overloaded := ld_utilization >= max_lds.U
stC.io.rob_overloaded := st_utilization >= max_sts.U
// Wire up iterator inputs
ex.io.lda_completed := (ldA.io.loop_id =/= ex.io.loop_id) || ldA.io.idle
ex.io.ldb_completed := (ldB.io.loop_id =/= ex.io.loop_id) || ldB.io.idle
ex.io.ldd_completed := (ldD.io.loop_id =/= ex.io.loop_id) || ldD.io.idle
ex.io.ld_ka := ldA.io.k
ex.io.ld_kb := ldB.io.k
ex.io.ld_j := ldB.io.j
ex.io.ld_i := ldA.io.i
stC.io.ex_completed := (ex.io.loop_id =/= stC.io.loop_id) || ex.io.idle
stC.io.ex_k := ex.io.k
stC.io.ex_j := ex.io.j
stC.io.ex_i := ex.io.i
// when loop matmul is used as resadd unroller
// skip ex
// track ldB instead of ex
when(is_resadd){
stC.io.ex_completed := (ldA.io.loop_id =/= stC.io.loop_id || ldA.io.idle) && (ldB.io.loop_id =/= stC.io.loop_id || ldB.io.idle)
stC.io.ex_k := 0.U // req.max_k shall be 1
stC.io.ex_j := ldB.io.j
stC.io.ex_i := ldB.io.k
//ldB.io.rob_overloaded := ld_utilization >= max_lds.U || !((ldA.io.loop_id =/= ldB.io.loop_id) || ldA.io.idle)
}
val loops_configured = RegInit(0.U(16.W))
dontTouch(loops_configured)
// Create config registers
when(cmd.valid && is_loop_cmd && !loop_being_configured.configured) {
switch (cmd.bits.cmd.inst.funct) {
is (LOOP_WS_CONFIG_BOUNDS) {
loop_being_configured.max_k := cmd.bits.cmd.rs2(iterator_bitwidth * 3 - 1, iterator_bitwidth * 2)
loop_being_configured.max_j := cmd.bits.cmd.rs2(iterator_bitwidth * 2 - 1, iterator_bitwidth)
loop_being_configured.max_i := cmd.bits.cmd.rs2(iterator_bitwidth-1, 0)
loop_being_configured.pad_k := cmd.bits.cmd.rs1(iterator_bitwidth * 3 - 1, iterator_bitwidth * 2)
loop_being_configured.pad_j := cmd.bits.cmd.rs1(iterator_bitwidth * 2 - 1, iterator_bitwidth)
loop_being_configured.pad_i := cmd.bits.cmd.rs1(iterator_bitwidth-1, 0)
}
is (LOOP_WS_CONFIG_ADDRS_AB) {
loop_being_configured.a_dram_addr := cmd.bits.cmd.rs1
loop_being_configured.b_dram_addr := cmd.bits.cmd.rs2
}
is (LOOP_WS_CONFIG_ADDRS_DC) {
loop_being_configured.d_dram_addr := cmd.bits.cmd.rs1
loop_being_configured.c_dram_addr := cmd.bits.cmd.rs2
}
is (LOOP_WS_CONFIG_STRIDES_AB) {
loop_being_configured.a_dram_stride := cmd.bits.cmd.rs1
loop_being_configured.b_dram_stride := cmd.bits.cmd.rs2
}
is (LOOP_WS_CONFIG_STRIDES_DC) {
loop_being_configured.d_dram_stride := cmd.bits.cmd.rs1
loop_being_configured.c_dram_stride := cmd.bits.cmd.rs2
}
is (LOOP_WS) {
loop_being_configured.ex_accumulate := cmd.bits.cmd.rs1(0)
loop_being_configured.full_c := cmd.bits.cmd.rs1(1)
loop_being_configured.low_d := cmd.bits.cmd.rs1(2)
loop_being_configured.act := cmd.bits.cmd.rs1(8+Activation.bitwidth-1, 8) // TODO magic numbers
loop_being_configured.a_ex_spad_id := cmd.bits.cmd.rs1(19, 18)
loop_being_configured.b_ex_spad_id := cmd.bits.cmd.rs1(17, 16)
loop_being_configured.a_transpose := cmd.bits.cmd.rs2(0)
loop_being_configured.b_transpose := cmd.bits.cmd.rs2(1)
is_resadd := cmd.bits.cmd.rs2(2)
loop_being_configured.configured := true.B
loops_configured := loops_configured + 1.U
}
}
}
// Wire up request signals
val ld_d_addr_start = RegInit(0.U(log2Up(max_acc_addr).W))
val ex_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W))
val st_c_addr_start = RegInit(0.U(log2Up(max_acc_addr).W))
val loop_requesting_ldA_id = Mux(head_loop.lda_started, tail_loop_id, head_loop_id)
val loop_requesting_ldA = loops(loop_requesting_ldA_id)
ldA.io.req.bits.max_k := Mux(is_resadd, loop_requesting_ldA.max_j, loop_requesting_ldA.max_k)
ldA.io.req.bits.max_i := loop_requesting_ldA.max_i
ldA.io.req.bits.pad_k := Mux(is_resadd, loop_requesting_ldA.pad_j, loop_requesting_ldA.pad_k)
ldA.io.req.bits.pad_i := loop_requesting_ldA.pad_i
ldA.io.req.bits.dram_addr := loop_requesting_ldA.a_dram_addr
ldA.io.req.bits.dram_stride := loop_requesting_ldA.a_dram_stride
ldA.io.req.bits.transpose := loop_requesting_ldA.a_transpose
ldA.io.req.bits.addr_start := Mux(loop_requesting_ldA.a_ex_spad_id === 0.U, loop_requesting_ldA.a_addr_start, (loop_requesting_ldA.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U)
ldA.io.req.bits.loop_id := loop_requesting_ldA_id
ldA.io.req.bits.is_resadd := is_resadd
ldA.io.req.valid := !loop_requesting_ldA.lda_started && loop_requesting_ldA.configured
when (ldA.io.req.fire) {
loop_requesting_ldA.running := true.B
loop_requesting_ldA.lda_started := true.B
}
val loop_requesting_ldB_id = Mux(head_loop.ldb_started, tail_loop_id, head_loop_id)
val loop_requesting_ldB = loops(loop_requesting_ldB_id)
ldB.io.req.bits.max_j := loop_requesting_ldB.max_j
ldB.io.req.bits.max_k := Mux(is_resadd, loop_requesting_ldB.max_i, loop_requesting_ldB.max_k)
ldB.io.req.bits.pad_j := loop_requesting_ldB.pad_j
ldB.io.req.bits.pad_k := Mux(is_resadd, loop_requesting_ldB.pad_i, loop_requesting_ldB.pad_k)
ldB.io.req.bits.dram_addr := loop_requesting_ldB.b_dram_addr
ldB.io.req.bits.dram_stride := loop_requesting_ldB.b_dram_stride
ldB.io.req.bits.transpose := loop_requesting_ldB.b_transpose
ldB.io.req.bits.addr_end := Mux(loop_requesting_ldB.b_ex_spad_id === 0.U, loop_requesting_ldB.b_addr_end, (loop_requesting_ldB.b_ex_spad_id) * (max_addr / concurrent_loops).U)
ldB.io.req.bits.loop_id := loop_requesting_ldB_id
ldB.io.req.bits.is_resadd := is_resadd
ldB.io.req.valid := !loop_requesting_ldB.ldb_started && loop_requesting_ldB.configured
when (ldB.io.req.fire) {
loop_requesting_ldB.running := true.B
loop_requesting_ldB.ldb_started := true.B
}
val loop_requesting_ex_id = Mux(head_loop.ex_started, tail_loop_id, head_loop_id)
val loop_requesting_ex = loops(loop_requesting_ex_id)
ex.io.req.bits.max_j := loop_requesting_ex.max_j
ex.io.req.bits.max_k := loop_requesting_ex.max_k
ex.io.req.bits.max_i := loop_requesting_ex.max_i
ex.io.req.bits.pad_j := loop_requesting_ex.pad_j
ex.io.req.bits.pad_k := loop_requesting_ex.pad_k
ex.io.req.bits.pad_i := loop_requesting_ex.pad_i
ex.io.req.bits.accumulate := loop_requesting_ex.ex_accumulate
ex.io.req.bits.a_addr_start := Mux(loop_requesting_ex.a_ex_spad_id === 0.U, loop_requesting_ex.a_addr_start, (loop_requesting_ex.a_ex_spad_id - 1.U) * (max_addr / concurrent_loops).U)
ex.io.req.bits.b_addr_end := Mux(loop_requesting_ex.b_ex_spad_id === 0.U, loop_requesting_ex.b_addr_end, (loop_requesting_ex.b_ex_spad_id) * (max_addr / concurrent_loops).U)
ex.io.req.bits.a_tranpose := loop_requesting_ex.a_transpose
ex.io.req.bits.b_tranpose := loop_requesting_ex.b_transpose
ex.io.req.bits.c_addr_start := ex_c_addr_start
ex.io.req.bits.loop_id := loop_requesting_ex_id
ex.io.req.bits.skip := is_resadd
ex.io.req.valid := !loop_requesting_ex.ex_started && loop_requesting_ex.lda_started &&
loop_requesting_ex.ldb_started && loop_requesting_ex.ldd_started && loop_requesting_ex.configured
when (ex.io.req.fire) {
loop_requesting_ex.running := true.B
loop_requesting_ex.ex_started := true.B
when (loop_requesting_ex.c_dram_addr =/= 0.U) {
ex_c_addr_start := floorAdd(ex_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U)
}
}
val loop_requesting_ldD_id = Mux(head_loop.ldd_started, tail_loop_id, head_loop_id)
val loop_requesting_ldD = loops(loop_requesting_ldD_id)
ldD.io.req.bits.max_j := loop_requesting_ldD.max_j
ldD.io.req.bits.max_i := loop_requesting_ldD.max_i
ldD.io.req.bits.pad_j := loop_requesting_ldD.pad_j
ldD.io.req.bits.pad_i := loop_requesting_ldD.pad_i
ldD.io.req.bits.dram_addr := loop_requesting_ldD.d_dram_addr
ldD.io.req.bits.dram_stride := loop_requesting_ldD.d_dram_stride
ldD.io.req.bits.low_d := loop_requesting_ldD.low_d
ldD.io.req.bits.addr_start := ld_d_addr_start
ldD.io.req.bits.loop_id := loop_requesting_ldD_id
ldD.io.req.valid := !loop_requesting_ldD.ldd_started && loop_requesting_ldD.configured
when (ldD.io.req.fire) {
loop_requesting_ldD.running := true.B
loop_requesting_ldD.ldd_started := true.B
when (loop_requesting_ldD.c_dram_addr =/= 0.U) {
ld_d_addr_start := floorAdd(ld_d_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U)
}
}
val loop_requesting_st_id = Mux(head_loop.st_started, tail_loop_id, head_loop_id)
val loop_requesting_st = loops(loop_requesting_st_id)
stC.io.req.bits.max_k := Mux(is_resadd, 1.U, loop_requesting_st.max_k)
stC.io.req.bits.max_j := loop_requesting_st.max_j
stC.io.req.bits.max_i := loop_requesting_st.max_i
stC.io.req.bits.pad_j := loop_requesting_st.pad_j
stC.io.req.bits.pad_i := loop_requesting_st.pad_i
stC.io.req.bits.dram_addr := loop_requesting_st.c_dram_addr
stC.io.req.bits.dram_stride := loop_requesting_st.c_dram_stride
stC.io.req.bits.full_c := loop_requesting_st.full_c
stC.io.req.bits.act := loop_requesting_st.act
stC.io.req.bits.addr_start := st_c_addr_start
stC.io.req.bits.loop_id := loop_requesting_st_id
stC.io.req.bits.is_resadd := is_resadd
stC.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.ex_started && loop_requesting_st.configured
when (stC.io.req.fire) {
loop_requesting_st.running := true.B
loop_requesting_st.st_started := true.B
when (loop_requesting_st.c_dram_addr =/= 0.U) {
st_c_addr_start := floorAdd(st_c_addr_start, (max_acc_addr / concurrent_loops).U, max_acc_addr.U)
}
}
when(is_resadd){
ldA.io.req.bits.addr_start := loop_requesting_ldA.resadd_addr_start
ldB.io.req.bits.addr_end := loop_requesting_ldB.resadd_addr_start
stC.io.req.bits.addr_start := loop_requesting_st.resadd_addr_start
stC.io.req.valid := !loop_requesting_st.st_started && loop_requesting_st.configured
}
// Handle completed signals
when (ldA.io.idle && loops(ldA.io.loop_id).running && loops(ldA.io.loop_id).lda_started) {
loops(ldA.io.loop_id).lda_completed := true.B
}
when (ldB.io.idle && loops(ldB.io.loop_id).running && loops(ldB.io.loop_id).ldb_started) {
loops(ldB.io.loop_id).ldb_completed := true.B
}
when (ex.io.idle && loops(ex.io.loop_id).running && loops(ex.io.loop_id).ex_started) {
loops(ex.io.loop_id).ex_completed := true.B
}
when (ldD.io.idle && loops(ldD.io.loop_id).running && loops(ldD.io.loop_id).ldd_started) {
loops(ldD.io.loop_id).ldd_completed := true.B
}
when (stC.io.idle && loops(stC.io.loop_id).running && loops(stC.io.loop_id).st_started) {
loops(stC.io.loop_id).st_completed := true.B
}
when (head_loop.running && head_loop.all_completed()) {
head_loop.reset()
head_loop_id := ~head_loop_id
}
// Resets
when (reset.asBool) {
loops.zipWithIndex.foreach { case (l, i) =>
l.reset()
l.a_addr_start := (i * (max_addr / concurrent_loops)).U
l.b_addr_end := ((i+1) * (max_addr / concurrent_loops)).U
l.resadd_addr_start := (i * (max_acc_addr / concurrent_loops)).U
}
}
}
object LoopMatmul {
def apply(in: DecoupledIO[GemminiCmd], ld_completed: UInt, st_completed: UInt, ex_completed: UInt,
block_size: Int, coreMaxAddrBits: Int, rob_size: Int, max_lds: Int, max_exs: Int, max_sts: Int,
max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int,
mvin_rs2_t: MvinRs2, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, mvout_rs2_t: MvoutRs2)
(implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool) = {
val mod = Module(new LoopMatmul(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts,
max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes,
mvin_rs2_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, mvout_rs2_t))
mod.io.in <> in
mod.io.ld_completed := ld_completed
mod.io.st_completed := st_completed
mod.io.ex_completed := ex_completed
(mod.io.out, mod.io.busy)
}
def castDramOffset(dram_offset: UInt): UInt = {
// Cast dram offsets to 32 bits max
dram_offset & "hFFFFFFFF".U
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File FrontendTLB.scala:
package gemmini
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile.{CoreBundle, CoreModule}
import freechips.rocketchip.tilelink.TLEdgeOut
import Util._
import midas.targetutils.PerfCounter
class DecoupledTLBReq(val lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle {
val tlb_req = new TLBReq(lgMaxSize)
val status = new MStatus
}
class TLBExceptionIO extends Bundle {
val interrupt = Output(Bool())
val flush_retry = Input(Bool())
val flush_skip = Input(Bool())
def flush(dummy: Int = 0): Bool = flush_retry || flush_skip
}
// TODO can we make TLB hits only take one cycle?
class DecoupledTLB(entries: Int, maxSize: Int, use_firesim_simulation_counters: Boolean)(implicit edge: TLEdgeOut, p: Parameters)
extends CoreModule {
val lgMaxSize = log2Ceil(maxSize)
val io = IO(new Bundle {
val req = Flipped(Valid(new DecoupledTLBReq(lgMaxSize)))
val resp = new TLBResp
val ptw = new TLBPTWIO
val exp = new TLBExceptionIO
val counter = new CounterEventIO()
})
val interrupt = RegInit(false.B)
io.exp.interrupt := interrupt
val tlb = Module(new TLB(false, lgMaxSize, TLBConfig(nSets=1, nWays=entries)))
tlb.io.req.valid := io.req.valid
tlb.io.req.bits := io.req.bits.tlb_req
io.resp := tlb.io.resp
tlb.io.kill := false.B
tlb.io.sfence.valid := io.exp.flush()
tlb.io.sfence.bits.rs1 := false.B
tlb.io.sfence.bits.rs2 := false.B
tlb.io.sfence.bits.addr := DontCare
tlb.io.sfence.bits.asid := DontCare
tlb.io.sfence.bits.hv := false.B
tlb.io.sfence.bits.hg := false.B
io.ptw <> tlb.io.ptw
tlb.io.ptw.status := io.req.bits.status
val exception = io.req.valid && Mux(io.req.bits.tlb_req.cmd === M_XRD, tlb.io.resp.pf.ld || tlb.io.resp.ae.ld, tlb.io.resp.pf.st || tlb.io.resp.ae.st)
when (exception) { interrupt := true.B }
when (interrupt && tlb.io.sfence.fire) {
interrupt := false.B
}
assert(!io.exp.flush_retry || !io.exp.flush_skip, "TLB: flushing with both retry and skip at same time")
CounterEventIO.init(io.counter)
io.counter.connectEventSignal(CounterEvent.DMA_TLB_HIT_REQ, io.req.fire && !tlb.io.resp.miss)
io.counter.connectEventSignal(CounterEvent.DMA_TLB_TOTAL_REQ, io.req.fire)
io.counter.connectEventSignal(CounterEvent.DMA_TLB_MISS_CYCLE, tlb.io.resp.miss)
if (use_firesim_simulation_counters) {
PerfCounter(io.req.fire && !tlb.io.resp.miss, "tlb_hits", "total number of tlb hits")
PerfCounter(io.req.fire, "tlb_reqs", "total number of tlb reqs")
PerfCounter(tlb.io.resp.miss, "tlb_miss_cycles", "total number of cycles where the tlb is resolving a miss")
}
}
class FrontendTLBIO(implicit p: Parameters) extends CoreBundle {
val lgMaxSize = log2Ceil(coreDataBytes)
// val req = Decoupled(new TLBReq(lgMaxSize))
val req = Valid(new DecoupledTLBReq(lgMaxSize))
val resp = Flipped(new TLBResp)
}
class FrontendTLB(nClients: Int, entries: Int, maxSize: Int, use_tlb_register_filter: Boolean, use_firesim_simulation_counters: Boolean, use_shared_tlb: Boolean)
(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule {
val num_tlbs = if (use_shared_tlb) 1 else nClients
val lgMaxSize = log2Ceil(coreDataBytes)
val io = IO(new Bundle {
val clients = Flipped(Vec(nClients, new FrontendTLBIO))
val ptw = Vec(num_tlbs, new TLBPTWIO)
val exp = Vec(num_tlbs, new TLBExceptionIO)
val counter = new CounterEventIO()
})
val tlbs = Seq.fill(num_tlbs)(Module(new DecoupledTLB(entries, maxSize, use_firesim_simulation_counters)))
io.ptw <> VecInit(tlbs.map(_.io.ptw))
io.exp <> VecInit(tlbs.map(_.io.exp))
val tlbArbOpt = if (use_shared_tlb) Some(Module(new RRArbiter(new DecoupledTLBReq(lgMaxSize), nClients))) else None
if (use_shared_tlb) {
val tlbArb = tlbArbOpt.get
val tlb = tlbs.head
tlb.io.req.valid := tlbArb.io.out.valid
tlb.io.req.bits := tlbArb.io.out.bits
tlbArb.io.out.ready := true.B
}
io.clients.zipWithIndex.foreach { case (client, i) =>
val last_translated_valid = RegInit(false.B)
val last_translated_vpn = RegInit(0.U(vaddrBits.W))
val last_translated_ppn = RegInit(0.U(paddrBits.W))
val l0_tlb_hit = last_translated_valid && ((client.req.bits.tlb_req.vaddr >> pgIdxBits).asUInt === (last_translated_vpn >> pgIdxBits).asUInt)
val l0_tlb_paddr = Cat(last_translated_ppn >> pgIdxBits, client.req.bits.tlb_req.vaddr(pgIdxBits-1,0))
val tlb = if (use_shared_tlb) tlbs.head else tlbs(i)
val tlbReq = if (use_shared_tlb) tlbArbOpt.get.io.in(i).bits else tlb.io.req.bits
val tlbReqValid = if (use_shared_tlb) tlbArbOpt.get.io.in(i).valid else tlb.io.req.valid
val tlbReqFire = if (use_shared_tlb) tlbArbOpt.get.io.in(i).fire else tlb.io.req.fire
tlbReqValid := RegNext(client.req.valid && !l0_tlb_hit)
tlbReq := RegNext(client.req.bits)
when (tlbReqFire && !tlb.io.resp.miss) {
last_translated_valid := true.B
last_translated_vpn := tlbReq.tlb_req.vaddr
last_translated_ppn := tlb.io.resp.paddr
}
when (tlb.io.exp.flush()) {
last_translated_valid := false.B
}
when (tlbReqFire) {
client.resp := tlb.io.resp
}.otherwise {
client.resp := DontCare
client.resp.paddr := RegNext(l0_tlb_paddr)
client.resp.miss := !RegNext(l0_tlb_hit)
}
// If we're not using the TLB filter register, then we set this value to always be false
if (!use_tlb_register_filter) {
last_translated_valid := false.B
}
}
// TODO Return the sum of the TLB counters, rather than just the counters of the first TLB. This only matters if we're
// not using the shared TLB
io.counter := DontCare
tlbs.foreach(_.io.counter.external_reset := false.B)
io.counter.collect(tlbs.head.io.counter)
}
File Controller.scala:
package gemmini
import java.nio.charset.StandardCharsets
import java.nio.file.{Files, Paths}
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.util.ClockGate
import freechips.rocketchip.tilelink.TLIdentityNode
import GemminiISA._
import Util._
class GemminiCmd(rob_entries: Int)(implicit p: Parameters) extends Bundle {
val cmd = new RoCCCommand
val rob_id = UDValid(UInt(log2Up(rob_entries).W))
val from_matmul_fsm = Bool()
val from_conv_fsm = Bool()
}
class Gemmini[T <: Data : Arithmetic, U <: Data, V <: Data](val config: GemminiArrayConfig[T, U, V])
(implicit p: Parameters)
extends LazyRoCC (
opcodes = config.opcodes,
nPTWPorts = if (config.use_shared_tlb) 1 else 2) {
Files.write(Paths.get(config.headerFilePath), config.generateHeader().getBytes(StandardCharsets.UTF_8))
if (System.getenv("GEMMINI_ONLY_GENERATE_GEMMINI_H") == "1") {
System.exit(1)
}
val xLen = p(TileKey).core.xLen
val spad = LazyModule(new Scratchpad(config))
override lazy val module = new GemminiModule(this)
override val tlNode = if (config.use_dedicated_tl_port) spad.id_node else TLIdentityNode()
override val atlNode = if (config.use_dedicated_tl_port) TLIdentityNode() else spad.id_node
val node = if (config.use_dedicated_tl_port) tlNode else atlNode
}
class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
(outer: Gemmini[T, U, V])
extends LazyRoCCModuleImp(outer)
with HasCoreParameters {
import outer.config._
import outer.spad
val ext_mem_io = if (use_shared_ext_mem) Some(IO(new ExtSpadMemIO(sp_banks, acc_banks, acc_sub_banks))) else None
ext_mem_io.foreach(_ <> outer.spad.module.io.ext_mem.get)
val tagWidth = 32
// Counters
val counters = Module(new CounterController(outer.config.num_counter, outer.xLen))
io.resp <> counters.io.out // Counter access command will be committed immediately
counters.io.event_io.external_values(0) := 0.U
counters.io.event_io.event_signal(0) := false.B
counters.io.in.valid := false.B
counters.io.in.bits := DontCare
counters.io.event_io.collect(spad.module.io.counter)
// TLB
implicit val edge = outer.spad.id_node.edges.out.head
val tlb = Module(new FrontendTLB(2, tlb_size, dma_maxbytes, use_tlb_register_filter, use_firesim_simulation_counters, use_shared_tlb))
(tlb.io.clients zip outer.spad.module.io.tlb).foreach(t => t._1 <> t._2)
tlb.io.exp.foreach(_.flush_skip := false.B)
tlb.io.exp.foreach(_.flush_retry := false.B)
io.ptw <> tlb.io.ptw
counters.io.event_io.collect(tlb.io.counter)
spad.module.io.flush := tlb.io.exp.map(_.flush()).reduce(_ || _)
val clock_en_reg = RegInit(true.B)
val gated_clock = if (clock_gate) ClockGate(clock, clock_en_reg, "gemmini_clock_gate") else clock
outer.spad.module.clock := gated_clock
/*
//=========================================================================
// Frontends: Incoming commands and ROB
//=========================================================================
// forward cmd to correct frontend. if the rob is busy, do not forward new
// commands to tiler, and vice versa
val is_cisc_mode = RegInit(false.B)
val raw_cmd = Queue(io.cmd)
val funct = raw_cmd.bits.inst.funct
val is_cisc_funct = (funct === CISC_CONFIG) ||
(funct === ADDR_AB) ||
(funct === ADDR_CD) ||
(funct === SIZE_MN) ||
(funct === SIZE_K) ||
(funct === RPT_BIAS) ||
(funct === RESET) ||
(funct === COMPUTE_CISC)
val raw_cisc_cmd = WireInit(raw_cmd)
val raw_risc_cmd = WireInit(raw_cmd)
raw_cisc_cmd.valid := false.B
raw_risc_cmd.valid := false.B
raw_cmd.ready := false.B
//-------------------------------------------------------------------------
// cisc
val cmd_fsm = CmdFSM(outer.config)
cmd_fsm.io.cmd <> raw_cisc_cmd
val tiler = TilerController(outer.config)
tiler.io.cmd_in <> cmd_fsm.io.tiler
//-------------------------------------------------------------------------
// risc
val unrolled_cmd = LoopUnroller(raw_risc_cmd, outer.config.meshRows * outer.config.tileRows)
*/
val reservation_station = withClock (gated_clock) { Module(new ReservationStation(outer.config, new GemminiCmd(reservation_station_entries))) }
counters.io.event_io.collect(reservation_station.io.counter)
when (io.cmd.valid && io.cmd.bits.inst.funct === CLKGATE_EN && !io.busy) {
clock_en_reg := io.cmd.bits.rs1(0)
}
val raw_cmd_q = Module(new Queue(new GemminiCmd(reservation_station_entries), entries = 2))
raw_cmd_q.io.enq.valid := io.cmd.valid
io.cmd.ready := raw_cmd_q.io.enq.ready
raw_cmd_q.io.enq.bits.cmd := io.cmd.bits
raw_cmd_q.io.enq.bits.rob_id := DontCare
raw_cmd_q.io.enq.bits.from_conv_fsm := false.B
raw_cmd_q.io.enq.bits.from_matmul_fsm := false.B
val raw_cmd = raw_cmd_q.io.deq
val max_lds = reservation_station_entries_ld
val max_exs = reservation_station_entries_ex
val max_sts = reservation_station_entries_st
val (conv_cmd, loop_conv_unroller_busy) = withClock (gated_clock) { LoopConv(raw_cmd, reservation_station.io.conv_ld_completed, reservation_station.io.conv_st_completed, reservation_station.io.conv_ex_completed,
meshRows*tileRows, coreMaxAddrBits, reservation_station_entries, max_lds, max_exs, max_sts, sp_banks * sp_bank_entries, acc_banks * acc_bank_entries,
inputType.getWidth, accType.getWidth, dma_maxbytes,
new ConfigMvinRs1(mvin_scale_t_bits, block_stride_bits, pixel_repeats_bits), new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t),
new ConfigMvoutRs2(acc_scale_t_bits, 32), new MvoutRs2(mvout_rows_bits, mvout_cols_bits, local_addr_t),
new ConfigExRs1(acc_scale_t_bits), new PreloadRs(mvin_rows_bits, mvin_cols_bits, local_addr_t),
new PreloadRs(mvout_rows_bits, mvout_cols_bits, local_addr_t),
new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t),
has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs) }
val (loop_cmd, loop_matmul_unroller_busy) = withClock (gated_clock) { LoopMatmul(conv_cmd, reservation_station.io.matmul_ld_completed, reservation_station.io.matmul_st_completed, reservation_station.io.matmul_ex_completed,
meshRows*tileRows, coreMaxAddrBits, reservation_station_entries, max_lds, max_exs, max_sts, sp_banks * sp_bank_entries, acc_banks * acc_bank_entries,
inputType.getWidth, accType.getWidth, dma_maxbytes, new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t),
new PreloadRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new PreloadRs(mvout_rows_bits, mvout_cols_bits, local_addr_t),
new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t),
new MvoutRs2(mvout_rows_bits, mvout_cols_bits, local_addr_t)) }
val unrolled_cmd = Queue(loop_cmd)
unrolled_cmd.ready := false.B
counters.io.event_io.connectEventSignal(CounterEvent.LOOP_MATMUL_ACTIVE_CYCLES, loop_matmul_unroller_busy)
// Wire up controllers to ROB
reservation_station.io.alloc.valid := false.B
reservation_station.io.alloc.bits := unrolled_cmd.bits
/*
//-------------------------------------------------------------------------
// finish muxing control signals to rob (risc) or tiler (cisc)
when (raw_cmd.valid && is_cisc_funct && !rob.io.busy) {
is_cisc_mode := true.B
raw_cisc_cmd.valid := true.B
raw_cmd.ready := raw_cisc_cmd.ready
}
.elsewhen (raw_cmd.valid && !is_cisc_funct && !tiler.io.busy) {
is_cisc_mode := false.B
raw_risc_cmd.valid := true.B
raw_cmd.ready := raw_risc_cmd.ready
}
*/
//=========================================================================
// Controllers
//=========================================================================
val load_controller = withClock (gated_clock) { Module(new LoadController(outer.config, coreMaxAddrBits, local_addr_t)) }
val store_controller = withClock (gated_clock) { Module(new StoreController(outer.config, coreMaxAddrBits, local_addr_t)) }
val ex_controller = withClock (gated_clock) { Module(new ExecuteController(xLen, tagWidth, outer.config)) }
counters.io.event_io.collect(load_controller.io.counter)
counters.io.event_io.collect(store_controller.io.counter)
counters.io.event_io.collect(ex_controller.io.counter)
/*
tiler.io.issue.load.ready := false.B
tiler.io.issue.store.ready := false.B
tiler.io.issue.exec.ready := false.B
*/
reservation_station.io.issue.ld.ready := false.B
reservation_station.io.issue.st.ready := false.B
reservation_station.io.issue.ex.ready := false.B
/*
when (is_cisc_mode) {
load_controller.io.cmd <> tiler.io.issue.load
store_controller.io.cmd <> tiler.io.issue.store
ex_controller.io.cmd <> tiler.io.issue.exec
}
.otherwise {
load_controller.io.cmd.valid := rob.io.issue.ld.valid
rob.io.issue.ld.ready := load_controller.io.cmd.ready
load_controller.io.cmd.bits.cmd := rob.io.issue.ld.cmd
load_controller.io.cmd.bits.cmd.inst.funct := rob.io.issue.ld.cmd.inst.funct
load_controller.io.cmd.bits.rob_id.push(rob.io.issue.ld.rob_id)
store_controller.io.cmd.valid := rob.io.issue.st.valid
rob.io.issue.st.ready := store_controller.io.cmd.ready
store_controller.io.cmd.bits.cmd := rob.io.issue.st.cmd
store_controller.io.cmd.bits.cmd.inst.funct := rob.io.issue.st.cmd.inst.funct
store_controller.io.cmd.bits.rob_id.push(rob.io.issue.st.rob_id)
ex_controller.io.cmd.valid := rob.io.issue.ex.valid
rob.io.issue.ex.ready := ex_controller.io.cmd.ready
ex_controller.io.cmd.bits.cmd := rob.io.issue.ex.cmd
ex_controller.io.cmd.bits.cmd.inst.funct := rob.io.issue.ex.cmd.inst.funct
ex_controller.io.cmd.bits.rob_id.push(rob.io.issue.ex.rob_id)
}
*/
load_controller.io.cmd.valid := reservation_station.io.issue.ld.valid
reservation_station.io.issue.ld.ready := load_controller.io.cmd.ready
load_controller.io.cmd.bits := reservation_station.io.issue.ld.cmd
load_controller.io.cmd.bits.rob_id.push(reservation_station.io.issue.ld.rob_id)
store_controller.io.cmd.valid := reservation_station.io.issue.st.valid
reservation_station.io.issue.st.ready := store_controller.io.cmd.ready
store_controller.io.cmd.bits := reservation_station.io.issue.st.cmd
store_controller.io.cmd.bits.rob_id.push(reservation_station.io.issue.st.rob_id)
ex_controller.io.cmd.valid := reservation_station.io.issue.ex.valid
reservation_station.io.issue.ex.ready := ex_controller.io.cmd.ready
ex_controller.io.cmd.bits := reservation_station.io.issue.ex.cmd
ex_controller.io.cmd.bits.rob_id.push(reservation_station.io.issue.ex.rob_id)
// Wire up scratchpad to controllers
spad.module.io.dma.read <> load_controller.io.dma
spad.module.io.dma.write <> store_controller.io.dma
ex_controller.io.srams.read <> spad.module.io.srams.read
ex_controller.io.srams.write <> spad.module.io.srams.write
spad.module.io.acc.read_req <> ex_controller.io.acc.read_req
ex_controller.io.acc.read_resp <> spad.module.io.acc.read_resp
ex_controller.io.acc.write <> spad.module.io.acc.write
// Im2Col unit
val im2col = withClock (gated_clock) { Module(new Im2Col(outer.config)) }
// Wire up Im2col
counters.io.event_io.collect(im2col.io.counter)
// im2col.io.sram_reads <> spad.module.io.srams.read
im2col.io.req <> ex_controller.io.im2col.req
ex_controller.io.im2col.resp <> im2col.io.resp
// Wire arbiter for ExecuteController and Im2Col scratchpad reads
(ex_controller.io.srams.read, im2col.io.sram_reads, spad.module.io.srams.read).zipped.foreach { case (ex_read, im2col_read, spad_read) =>
val req_arb = Module(new Arbiter(new ScratchpadReadReq(n=sp_bank_entries), 2))
req_arb.io.in(0) <> ex_read.req
req_arb.io.in(1) <> im2col_read.req
spad_read.req <> req_arb.io.out
// TODO if necessary, change how the responses are handled when fromIm2Col is added to spad read interface
ex_read.resp.valid := spad_read.resp.valid
im2col_read.resp.valid := spad_read.resp.valid
ex_read.resp.bits := spad_read.resp.bits
im2col_read.resp.bits := spad_read.resp.bits
spad_read.resp.ready := ex_read.resp.ready || im2col_read.resp.ready
}
// Wire up controllers to ROB
reservation_station.io.alloc.valid := false.B
// rob.io.alloc.bits := compressed_cmd.bits
reservation_station.io.alloc.bits := unrolled_cmd.bits
/*
//=========================================================================
// committed insn return path to frontends
//=========================================================================
//-------------------------------------------------------------------------
// cisc
tiler.io.completed.exec.valid := ex_controller.io.completed.valid
tiler.io.completed.exec.bits := ex_controller.io.completed.bits
tiler.io.completed.load <> load_controller.io.completed
tiler.io.completed.store <> store_controller.io.completed
// mux with cisc frontend arbiter
tiler.io.completed.exec.valid := ex_controller.io.completed.valid && is_cisc_mode
tiler.io.completed.load.valid := load_controller.io.completed.valid && is_cisc_mode
tiler.io.completed.store.valid := store_controller.io.completed.valid && is_cisc_mode
*/
//-------------------------------------------------------------------------
// risc
val reservation_station_completed_arb = Module(new Arbiter(UInt(log2Up(reservation_station_entries).W), 3))
reservation_station_completed_arb.io.in(0).valid := ex_controller.io.completed.valid
reservation_station_completed_arb.io.in(0).bits := ex_controller.io.completed.bits
reservation_station_completed_arb.io.in(1) <> load_controller.io.completed
reservation_station_completed_arb.io.in(2) <> store_controller.io.completed
// mux with cisc frontend arbiter
reservation_station_completed_arb.io.in(0).valid := ex_controller.io.completed.valid // && !is_cisc_mode
reservation_station_completed_arb.io.in(1).valid := load_controller.io.completed.valid // && !is_cisc_mode
reservation_station_completed_arb.io.in(2).valid := store_controller.io.completed.valid // && !is_cisc_mode
reservation_station.io.completed.valid := reservation_station_completed_arb.io.out.valid
reservation_station.io.completed.bits := reservation_station_completed_arb.io.out.bits
reservation_station_completed_arb.io.out.ready := true.B
// Wire up global RoCC signals
io.busy := raw_cmd.valid || loop_conv_unroller_busy || loop_matmul_unroller_busy || reservation_station.io.busy || spad.module.io.busy || unrolled_cmd.valid || loop_cmd.valid || conv_cmd.valid
io.interrupt := tlb.io.exp.map(_.interrupt).reduce(_ || _)
// assert(!io.interrupt, "Interrupt handlers have not been written yet")
// Cycle counters
val incr_ld_cycles = load_controller.io.busy && !store_controller.io.busy && !ex_controller.io.busy
val incr_st_cycles = !load_controller.io.busy && store_controller.io.busy && !ex_controller.io.busy
val incr_ex_cycles = !load_controller.io.busy && !store_controller.io.busy && ex_controller.io.busy
val incr_ld_st_cycles = load_controller.io.busy && store_controller.io.busy && !ex_controller.io.busy
val incr_ld_ex_cycles = load_controller.io.busy && !store_controller.io.busy && ex_controller.io.busy
val incr_st_ex_cycles = !load_controller.io.busy && store_controller.io.busy && ex_controller.io.busy
val incr_ld_st_ex_cycles = load_controller.io.busy && store_controller.io.busy && ex_controller.io.busy
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_CYCLES, incr_ld_cycles)
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_ST_CYCLES, incr_st_cycles)
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_EX_CYCLES, incr_ex_cycles)
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_ST_CYCLES, incr_ld_st_cycles)
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_EX_CYCLES, incr_ld_ex_cycles)
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_ST_EX_CYCLES, incr_st_ex_cycles)
counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_ST_EX_CYCLES, incr_ld_st_ex_cycles)
// Issue commands to controllers
// TODO we combinationally couple cmd.ready and cmd.valid signals here
// when (compressed_cmd.valid) {
when (unrolled_cmd.valid) {
// val config_cmd_type = cmd.bits.rs1(1,0) // TODO magic numbers
//val funct = unrolled_cmd.bits.inst.funct
val risc_funct = unrolled_cmd.bits.cmd.inst.funct
val is_flush = risc_funct === FLUSH_CMD
val is_counter_op = risc_funct === COUNTER_OP
val is_clock_gate_en = risc_funct === CLKGATE_EN
/*
val is_load = (funct === LOAD_CMD) || (funct === CONFIG_CMD && config_cmd_type === CONFIG_LOAD)
val is_store = (funct === STORE_CMD) || (funct === CONFIG_CMD && config_cmd_type === CONFIG_STORE)
val is_ex = (funct === COMPUTE_AND_FLIP_CMD || funct === COMPUTE_AND_STAY_CMD || funct === PRELOAD_CMD) ||
(funct === CONFIG_CMD && config_cmd_type === CONFIG_EX)
*/
when (is_flush) {
val skip = unrolled_cmd.bits.cmd.rs1(0)
tlb.io.exp.foreach(_.flush_skip := skip)
tlb.io.exp.foreach(_.flush_retry := !skip)
unrolled_cmd.ready := true.B // TODO should we wait for an acknowledgement from the TLB?
}
.elsewhen (is_counter_op) {
// If this is a counter access/configuration command, execute immediately
counters.io.in.valid := unrolled_cmd.valid
unrolled_cmd.ready := counters.io.in.ready
counters.io.in.bits := unrolled_cmd.bits.cmd
}
.elsewhen (is_clock_gate_en) {
unrolled_cmd.ready := true.B
}
.otherwise {
reservation_station.io.alloc.valid := true.B
when(reservation_station.io.alloc.fire) {
// compressed_cmd.ready := true.B
unrolled_cmd.ready := true.B
}
}
}
// Debugging signals
val pipeline_stall_counter = RegInit(0.U(32.W))
when (io.cmd.fire) {
pipeline_stall_counter := 0.U
}.elsewhen(io.busy) {
pipeline_stall_counter := pipeline_stall_counter + 1.U
}
assert(pipeline_stall_counter < 10000000.U, "pipeline stall")
/*
//=========================================================================
// Wire up global RoCC signals
//=========================================================================
io.busy := raw_cmd.valid || unrolled_cmd.valid || rob.io.busy || spad.module.io.busy || tiler.io.busy
io.interrupt := tlb.io.exp.interrupt
// hack
when(is_cisc_mode || !(unrolled_cmd.valid || rob.io.busy || tiler.io.busy)){
tlb.io.exp.flush_retry := cmd_fsm.io.flush_retry
tlb.io.exp.flush_skip := cmd_fsm.io.flush_skip
}
*/
//=========================================================================
// Performance Counters Access
//=========================================================================
}
| module Gemmini( // @[Controller.scala:45:7]
input clock, // @[Controller.scala:45:7]
input reset, // @[Controller.scala:45:7]
input auto_spad_id_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_spad_id_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_spad_id_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_spad_id_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_spad_id_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_spad_id_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_spad_id_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_spad_id_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_spad_id_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_spad_id_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_spad_id_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_spad_id_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_spad_id_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_spad_id_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_spad_id_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_spad_id_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_spad_id_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_spad_id_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_spad_id_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_spad_id_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_cmd_ready, // @[LazyRoCC.scala:78:14]
input io_cmd_valid, // @[LazyRoCC.scala:78:14]
input [6:0] io_cmd_bits_inst_funct, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rs2, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rs1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xd, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xs1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xs2, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rd, // @[LazyRoCC.scala:78:14]
input [6:0] io_cmd_bits_inst_opcode, // @[LazyRoCC.scala:78:14]
input [63:0] io_cmd_bits_rs1, // @[LazyRoCC.scala:78:14]
input [63:0] io_cmd_bits_rs2, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_debug, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_cease, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_cmd_bits_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_dprv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_prv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_v, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sd, // @[LazyRoCC.scala:78:14]
input [22:0] io_cmd_bits_status_zero2, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mpv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_gva, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mbe, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_sxl, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_uxl, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sd_rv32, // @[LazyRoCC.scala:78:14]
input [7:0] io_cmd_bits_status_zero1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tsr, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tw, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tvm, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mxr, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sum, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_xs, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_vs, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_spp, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mpie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_ube, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_spie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_upie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_hie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_uie, // @[LazyRoCC.scala:78:14]
input io_resp_ready, // @[LazyRoCC.scala:78:14]
output io_resp_valid, // @[LazyRoCC.scala:78:14]
output [4:0] io_resp_bits_rd, // @[LazyRoCC.scala:78:14]
output [63:0] io_resp_bits_data, // @[LazyRoCC.scala:78:14]
input io_mem_req_ready, // @[LazyRoCC.scala:78:14]
input io_mem_resp_valid, // @[LazyRoCC.scala:78:14]
input [39:0] io_mem_resp_bits_addr, // @[LazyRoCC.scala:78:14]
input [7:0] io_mem_resp_bits_tag, // @[LazyRoCC.scala:78:14]
input [4:0] io_mem_resp_bits_cmd, // @[LazyRoCC.scala:78:14]
input [1:0] io_mem_resp_bits_size, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_signed, // @[LazyRoCC.scala:78:14]
input [1:0] io_mem_resp_bits_dprv, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_dv, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data, // @[LazyRoCC.scala:78:14]
input [7:0] io_mem_resp_bits_mask, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_replay, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_has_data, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data_raw, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_store_data, // @[LazyRoCC.scala:78:14]
output io_busy, // @[LazyRoCC.scala:78:14]
output io_interrupt, // @[LazyRoCC.scala:78:14]
input io_exception, // @[LazyRoCC.scala:78:14]
input io_ptw_0_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_0_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_0_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_0_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_0_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_0_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_0_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_0_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_0_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_0_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_0_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_3_value // @[LazyRoCC.scala:78:14]
);
wire tlb_io_exp_0_flush_retry; // @[Controller.scala:73:36, :358:29, :375:21, :378:40]
wire tlb_io_exp_0_flush_skip; // @[Controller.scala:72:35, :358:29, :375:21, :377:39]
wire _reservation_station_completed_arb_io_in_1_ready; // @[Controller.scala:312:49]
wire _reservation_station_completed_arb_io_in_2_ready; // @[Controller.scala:312:49]
wire _reservation_station_completed_arb_io_out_valid; // @[Controller.scala:312:49]
wire [5:0] _reservation_station_completed_arb_io_out_bits; // @[Controller.scala:312:49]
wire _req_arb_3_io_in_0_ready; // @[Controller.scala:268:25]
wire _req_arb_3_io_in_1_ready; // @[Controller.scala:268:25]
wire _req_arb_3_io_out_valid; // @[Controller.scala:268:25]
wire [11:0] _req_arb_3_io_out_bits_addr; // @[Controller.scala:268:25]
wire _req_arb_2_io_in_0_ready; // @[Controller.scala:268:25]
wire _req_arb_2_io_in_1_ready; // @[Controller.scala:268:25]
wire _req_arb_2_io_out_valid; // @[Controller.scala:268:25]
wire [11:0] _req_arb_2_io_out_bits_addr; // @[Controller.scala:268:25]
wire _req_arb_1_io_in_0_ready; // @[Controller.scala:268:25]
wire _req_arb_1_io_in_1_ready; // @[Controller.scala:268:25]
wire _req_arb_1_io_out_valid; // @[Controller.scala:268:25]
wire [11:0] _req_arb_1_io_out_bits_addr; // @[Controller.scala:268:25]
wire _req_arb_io_in_0_ready; // @[Controller.scala:268:25]
wire _req_arb_io_in_1_ready; // @[Controller.scala:268:25]
wire _req_arb_io_out_valid; // @[Controller.scala:268:25]
wire [11:0] _req_arb_io_out_bits_addr; // @[Controller.scala:268:25]
wire [7:0] _im2col_io_resp_bits_a_im2col_0; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_1; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_2; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_3; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_4; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_5; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_6; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_7; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_8; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_9; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_10; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_11; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_12; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_13; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_14; // @[Controller.scala:258:48]
wire [7:0] _im2col_io_resp_bits_a_im2col_15; // @[Controller.scala:258:48]
wire _im2col_io_resp_bits_im2col_end; // @[Controller.scala:258:48]
wire [8:0] _im2col_io_resp_bits_im2col_turn; // @[Controller.scala:258:48]
wire [6:0] _im2col_io_resp_bits_row_turn; // @[Controller.scala:258:48]
wire [11:0] _im2col_io_sram_reads_0_req_bits_addr; // @[Controller.scala:258:48]
wire [11:0] _im2col_io_sram_reads_1_req_bits_addr; // @[Controller.scala:258:48]
wire [11:0] _im2col_io_sram_reads_2_req_bits_addr; // @[Controller.scala:258:48]
wire [11:0] _im2col_io_sram_reads_3_req_bits_addr; // @[Controller.scala:258:48]
wire _im2col_io_counter_event_signal_38; // @[Controller.scala:258:48]
wire _im2col_io_counter_event_signal_39; // @[Controller.scala:258:48]
wire _im2col_io_counter_event_signal_40; // @[Controller.scala:258:48]
wire _ex_controller_io_cmd_ready; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_addr_is_acc_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_addr_accumulate; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_addr_read_full_acc_row; // @[Controller.scala:190:55]
wire [2:0] _ex_controller_io_im2col_req_bits_addr_norm_cmd; // @[Controller.scala:190:55]
wire [10:0] _ex_controller_io_im2col_req_bits_addr_garbage; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_addr_garbage_bit; // @[Controller.scala:190:55]
wire [13:0] _ex_controller_io_im2col_req_bits_addr_data; // @[Controller.scala:190:55]
wire [7:0] _ex_controller_io_im2col_req_bits_ocol; // @[Controller.scala:190:55]
wire [3:0] _ex_controller_io_im2col_req_bits_krow; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_im2col_req_bits_icol; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_im2col_req_bits_irow; // @[Controller.scala:190:55]
wire [2:0] _ex_controller_io_im2col_req_bits_stride; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_im2col_req_bits_channel; // @[Controller.scala:190:55]
wire [10:0] _ex_controller_io_im2col_req_bits_row_turn; // @[Controller.scala:190:55]
wire [7:0] _ex_controller_io_im2col_req_bits_kdim2; // @[Controller.scala:190:55]
wire [3:0] _ex_controller_io_im2col_req_bits_row_left; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_weight_double_bank; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_weight_triple_bank; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_req_bits_start_inputting; // @[Controller.scala:190:55]
wire _ex_controller_io_im2col_resp_ready; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_read_0_req_valid; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_read_0_req_bits_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_read_1_req_valid; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_read_1_req_bits_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_read_2_req_valid; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_read_2_req_bits_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_read_3_req_valid; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_read_3_req_bits_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_en; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_write_0_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_0; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_1; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_2; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_3; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_4; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_5; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_6; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_7; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_8; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_9; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_10; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_11; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_12; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_13; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_14; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_0_mask_15; // @[Controller.scala:190:55]
wire [127:0] _ex_controller_io_srams_write_0_data; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_en; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_write_1_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_0; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_1; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_2; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_3; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_4; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_5; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_6; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_7; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_8; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_9; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_10; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_11; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_12; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_13; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_14; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_1_mask_15; // @[Controller.scala:190:55]
wire [127:0] _ex_controller_io_srams_write_1_data; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_en; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_write_2_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_0; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_1; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_2; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_3; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_4; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_5; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_6; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_7; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_8; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_9; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_10; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_11; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_12; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_13; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_14; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_2_mask_15; // @[Controller.scala:190:55]
wire [127:0] _ex_controller_io_srams_write_2_data; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_en; // @[Controller.scala:190:55]
wire [11:0] _ex_controller_io_srams_write_3_addr; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_0; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_1; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_2; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_3; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_4; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_5; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_6; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_7; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_8; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_9; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_10; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_11; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_12; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_13; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_14; // @[Controller.scala:190:55]
wire _ex_controller_io_srams_write_3_mask_15; // @[Controller.scala:190:55]
wire [127:0] _ex_controller_io_srams_write_3_data; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_read_req_0_valid; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_read_req_0_bits_scale_bits; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_acc_read_req_0_bits_addr; // @[Controller.scala:190:55]
wire [2:0] _ex_controller_io_acc_read_req_0_bits_act; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_read_req_1_valid; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_read_req_1_bits_scale_bits; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_acc_read_req_1_bits_addr; // @[Controller.scala:190:55]
wire [2:0] _ex_controller_io_acc_read_req_1_bits_act; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_read_resp_0_ready; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_read_resp_1_ready; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_valid; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_acc_write_0_bits_addr; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_0_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_1_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_2_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_3_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_4_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_5_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_6_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_7_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_8_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_9_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_10_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_11_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_12_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_13_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_14_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_0_bits_data_15_0; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_acc; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_0; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_1; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_2; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_3; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_4; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_5; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_6; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_7; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_8; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_9; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_10; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_11; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_12; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_13; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_14; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_15; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_16; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_17; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_18; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_19; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_20; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_21; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_22; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_23; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_24; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_25; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_26; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_27; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_28; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_29; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_30; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_31; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_32; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_33; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_34; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_35; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_36; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_37; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_38; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_39; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_40; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_41; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_42; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_43; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_44; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_45; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_46; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_47; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_48; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_49; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_50; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_51; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_52; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_53; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_54; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_55; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_56; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_57; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_58; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_59; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_60; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_61; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_62; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_0_bits_mask_63; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_valid; // @[Controller.scala:190:55]
wire [8:0] _ex_controller_io_acc_write_1_bits_addr; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_0_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_1_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_2_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_3_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_4_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_5_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_6_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_7_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_8_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_9_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_10_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_11_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_12_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_13_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_14_0; // @[Controller.scala:190:55]
wire [31:0] _ex_controller_io_acc_write_1_bits_data_15_0; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_acc; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_0; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_1; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_2; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_3; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_4; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_5; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_6; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_7; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_8; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_9; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_10; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_11; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_12; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_13; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_14; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_15; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_16; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_17; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_18; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_19; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_20; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_21; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_22; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_23; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_24; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_25; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_26; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_27; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_28; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_29; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_30; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_31; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_32; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_33; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_34; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_35; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_36; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_37; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_38; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_39; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_40; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_41; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_42; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_43; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_44; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_45; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_46; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_47; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_48; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_49; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_50; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_51; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_52; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_53; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_54; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_55; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_56; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_57; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_58; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_59; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_60; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_61; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_62; // @[Controller.scala:190:55]
wire _ex_controller_io_acc_write_1_bits_mask_63; // @[Controller.scala:190:55]
wire _ex_controller_io_completed_valid; // @[Controller.scala:190:55]
wire [5:0] _ex_controller_io_completed_bits; // @[Controller.scala:190:55]
wire _ex_controller_io_busy; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_24; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_25; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_26; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_27; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_28; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_29; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_30; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_31; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_32; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_33; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_34; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_35; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_36; // @[Controller.scala:190:55]
wire _ex_controller_io_counter_event_signal_37; // @[Controller.scala:190:55]
wire _store_controller_io_cmd_ready; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_valid; // @[Controller.scala:189:58]
wire [39:0] _store_controller_io_dma_req_bits_vaddr; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_laddr_is_acc_addr; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_laddr_accumulate; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_laddr_read_full_acc_row; // @[Controller.scala:189:58]
wire [10:0] _store_controller_io_dma_req_bits_laddr_garbage; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_laddr_garbage_bit; // @[Controller.scala:189:58]
wire [13:0] _store_controller_io_dma_req_bits_laddr_data; // @[Controller.scala:189:58]
wire [2:0] _store_controller_io_dma_req_bits_acc_act; // @[Controller.scala:189:58]
wire [31:0] _store_controller_io_dma_req_bits_acc_scale; // @[Controller.scala:189:58]
wire [15:0] _store_controller_io_dma_req_bits_len; // @[Controller.scala:189:58]
wire [7:0] _store_controller_io_dma_req_bits_block; // @[Controller.scala:189:58]
wire [7:0] _store_controller_io_dma_req_bits_cmd_id; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_debug; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_cease; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_wfi; // @[Controller.scala:189:58]
wire [31:0] _store_controller_io_dma_req_bits_status_isa; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_dprv; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_dv; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_prv; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_v; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_sd; // @[Controller.scala:189:58]
wire [22:0] _store_controller_io_dma_req_bits_status_zero2; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_mpv; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_gva; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_mbe; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_sbe; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_sxl; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_uxl; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_sd_rv32; // @[Controller.scala:189:58]
wire [7:0] _store_controller_io_dma_req_bits_status_zero1; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_tsr; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_tw; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_tvm; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_mxr; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_sum; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_mprv; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_xs; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_fs; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_mpp; // @[Controller.scala:189:58]
wire [1:0] _store_controller_io_dma_req_bits_status_vs; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_spp; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_mpie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_ube; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_spie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_upie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_mie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_hie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_sie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_status_uie; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_pool_en; // @[Controller.scala:189:58]
wire _store_controller_io_dma_req_bits_store_en; // @[Controller.scala:189:58]
wire _store_controller_io_completed_valid; // @[Controller.scala:189:58]
wire [5:0] _store_controller_io_completed_bits; // @[Controller.scala:189:58]
wire _store_controller_io_busy; // @[Controller.scala:189:58]
wire _store_controller_io_counter_event_signal_11; // @[Controller.scala:189:58]
wire _store_controller_io_counter_event_signal_12; // @[Controller.scala:189:58]
wire _store_controller_io_counter_event_signal_13; // @[Controller.scala:189:58]
wire _store_controller_io_counter_event_signal_14; // @[Controller.scala:189:58]
wire _load_controller_io_cmd_ready; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_valid; // @[Controller.scala:188:57]
wire [39:0] _load_controller_io_dma_req_bits_vaddr; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_laddr_is_acc_addr; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_laddr_accumulate; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_laddr_read_full_acc_row; // @[Controller.scala:188:57]
wire [2:0] _load_controller_io_dma_req_bits_laddr_norm_cmd; // @[Controller.scala:188:57]
wire [10:0] _load_controller_io_dma_req_bits_laddr_garbage; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_laddr_garbage_bit; // @[Controller.scala:188:57]
wire [13:0] _load_controller_io_dma_req_bits_laddr_data; // @[Controller.scala:188:57]
wire [15:0] _load_controller_io_dma_req_bits_cols; // @[Controller.scala:188:57]
wire [15:0] _load_controller_io_dma_req_bits_repeats; // @[Controller.scala:188:57]
wire [31:0] _load_controller_io_dma_req_bits_scale; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_has_acc_bitwidth; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_all_zeros; // @[Controller.scala:188:57]
wire [15:0] _load_controller_io_dma_req_bits_block_stride; // @[Controller.scala:188:57]
wire [7:0] _load_controller_io_dma_req_bits_pixel_repeats; // @[Controller.scala:188:57]
wire [7:0] _load_controller_io_dma_req_bits_cmd_id; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_debug; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_cease; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_wfi; // @[Controller.scala:188:57]
wire [31:0] _load_controller_io_dma_req_bits_status_isa; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_dprv; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_dv; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_prv; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_v; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_sd; // @[Controller.scala:188:57]
wire [22:0] _load_controller_io_dma_req_bits_status_zero2; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_mpv; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_gva; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_mbe; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_sbe; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_sxl; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_uxl; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_sd_rv32; // @[Controller.scala:188:57]
wire [7:0] _load_controller_io_dma_req_bits_status_zero1; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_tsr; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_tw; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_tvm; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_mxr; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_sum; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_mprv; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_xs; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_fs; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_mpp; // @[Controller.scala:188:57]
wire [1:0] _load_controller_io_dma_req_bits_status_vs; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_spp; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_mpie; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_ube; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_spie; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_upie; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_mie; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_hie; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_sie; // @[Controller.scala:188:57]
wire _load_controller_io_dma_req_bits_status_uie; // @[Controller.scala:188:57]
wire _load_controller_io_completed_valid; // @[Controller.scala:188:57]
wire [5:0] _load_controller_io_completed_bits; // @[Controller.scala:188:57]
wire _load_controller_io_busy; // @[Controller.scala:188:57]
wire _load_controller_io_counter_event_signal_8; // @[Controller.scala:188:57]
wire _load_controller_io_counter_event_signal_9; // @[Controller.scala:188:57]
wire _load_controller_io_counter_event_signal_10; // @[Controller.scala:188:57]
wire _unrolled_cmd_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [6:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_funct; // @[Decoupled.scala:362:21]
wire [4:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_rs2; // @[Decoupled.scala:362:21]
wire [4:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_rs1; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_inst_xd; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_inst_xs1; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_inst_xs2; // @[Decoupled.scala:362:21]
wire [4:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_rd; // @[Decoupled.scala:362:21]
wire [6:0] _unrolled_cmd_q_io_deq_bits_cmd_inst_opcode; // @[Decoupled.scala:362:21]
wire [63:0] _unrolled_cmd_q_io_deq_bits_cmd_rs1; // @[Decoupled.scala:362:21]
wire [63:0] _unrolled_cmd_q_io_deq_bits_cmd_rs2; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_debug; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_cease; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_wfi; // @[Decoupled.scala:362:21]
wire [31:0] _unrolled_cmd_q_io_deq_bits_cmd_status_isa; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_dprv; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_dv; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_prv; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_v; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_sd; // @[Decoupled.scala:362:21]
wire [22:0] _unrolled_cmd_q_io_deq_bits_cmd_status_zero2; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_mpv; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_gva; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_mbe; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_sbe; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_sxl; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_uxl; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_sd_rv32; // @[Decoupled.scala:362:21]
wire [7:0] _unrolled_cmd_q_io_deq_bits_cmd_status_zero1; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_tsr; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_tw; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_tvm; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_mxr; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_sum; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_mprv; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_xs; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_fs; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_mpp; // @[Decoupled.scala:362:21]
wire [1:0] _unrolled_cmd_q_io_deq_bits_cmd_status_vs; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_spp; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_mpie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_ube; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_spie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_upie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_mie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_hie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_sie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_cmd_status_uie; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_rob_id_valid; // @[Decoupled.scala:362:21]
wire [5:0] _unrolled_cmd_q_io_deq_bits_rob_id_bits; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_from_matmul_fsm; // @[Decoupled.scala:362:21]
wire _unrolled_cmd_q_io_deq_bits_from_conv_fsm; // @[Decoupled.scala:362:21]
wire _mod_1_io_in_ready; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_valid; // @[LoopMatmul.scala:1127:21]
wire [6:0] _mod_1_io_out_bits_cmd_inst_funct; // @[LoopMatmul.scala:1127:21]
wire [4:0] _mod_1_io_out_bits_cmd_inst_rs2; // @[LoopMatmul.scala:1127:21]
wire [4:0] _mod_1_io_out_bits_cmd_inst_rs1; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_inst_xd; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_inst_xs1; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_inst_xs2; // @[LoopMatmul.scala:1127:21]
wire [4:0] _mod_1_io_out_bits_cmd_inst_rd; // @[LoopMatmul.scala:1127:21]
wire [6:0] _mod_1_io_out_bits_cmd_inst_opcode; // @[LoopMatmul.scala:1127:21]
wire [63:0] _mod_1_io_out_bits_cmd_rs1; // @[LoopMatmul.scala:1127:21]
wire [63:0] _mod_1_io_out_bits_cmd_rs2; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_debug; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_cease; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_wfi; // @[LoopMatmul.scala:1127:21]
wire [31:0] _mod_1_io_out_bits_cmd_status_isa; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_dprv; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_dv; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_prv; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_v; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_sd; // @[LoopMatmul.scala:1127:21]
wire [22:0] _mod_1_io_out_bits_cmd_status_zero2; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_mpv; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_gva; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_mbe; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_sbe; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_sxl; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_uxl; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_sd_rv32; // @[LoopMatmul.scala:1127:21]
wire [7:0] _mod_1_io_out_bits_cmd_status_zero1; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_tsr; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_tw; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_tvm; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_mxr; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_sum; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_mprv; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_xs; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_fs; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_mpp; // @[LoopMatmul.scala:1127:21]
wire [1:0] _mod_1_io_out_bits_cmd_status_vs; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_spp; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_mpie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_ube; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_spie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_upie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_mie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_hie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_sie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_cmd_status_uie; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_from_matmul_fsm; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_out_bits_from_conv_fsm; // @[LoopMatmul.scala:1127:21]
wire _mod_1_io_busy; // @[LoopMatmul.scala:1127:21]
wire _mod_io_in_ready; // @[LoopConv.scala:1542:21]
wire _mod_io_out_valid; // @[LoopConv.scala:1542:21]
wire [6:0] _mod_io_out_bits_cmd_inst_funct; // @[LoopConv.scala:1542:21]
wire [4:0] _mod_io_out_bits_cmd_inst_rs2; // @[LoopConv.scala:1542:21]
wire [4:0] _mod_io_out_bits_cmd_inst_rs1; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_inst_xd; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_inst_xs1; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_inst_xs2; // @[LoopConv.scala:1542:21]
wire [4:0] _mod_io_out_bits_cmd_inst_rd; // @[LoopConv.scala:1542:21]
wire [6:0] _mod_io_out_bits_cmd_inst_opcode; // @[LoopConv.scala:1542:21]
wire [63:0] _mod_io_out_bits_cmd_rs1; // @[LoopConv.scala:1542:21]
wire [63:0] _mod_io_out_bits_cmd_rs2; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_debug; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_cease; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_wfi; // @[LoopConv.scala:1542:21]
wire [31:0] _mod_io_out_bits_cmd_status_isa; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_dprv; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_dv; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_prv; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_v; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_sd; // @[LoopConv.scala:1542:21]
wire [22:0] _mod_io_out_bits_cmd_status_zero2; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_mpv; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_gva; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_mbe; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_sbe; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_sxl; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_uxl; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_sd_rv32; // @[LoopConv.scala:1542:21]
wire [7:0] _mod_io_out_bits_cmd_status_zero1; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_tsr; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_tw; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_tvm; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_mxr; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_sum; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_mprv; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_xs; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_fs; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_mpp; // @[LoopConv.scala:1542:21]
wire [1:0] _mod_io_out_bits_cmd_status_vs; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_spp; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_mpie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_ube; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_spie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_upie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_mie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_hie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_sie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_cmd_status_uie; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_from_matmul_fsm; // @[LoopConv.scala:1542:21]
wire _mod_io_out_bits_from_conv_fsm; // @[LoopConv.scala:1542:21]
wire _mod_io_busy; // @[LoopConv.scala:1542:21]
wire _raw_cmd_q_io_deq_valid; // @[Controller.scala:131:25]
wire [6:0] _raw_cmd_q_io_deq_bits_cmd_inst_funct; // @[Controller.scala:131:25]
wire [4:0] _raw_cmd_q_io_deq_bits_cmd_inst_rs2; // @[Controller.scala:131:25]
wire [4:0] _raw_cmd_q_io_deq_bits_cmd_inst_rs1; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_inst_xd; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_inst_xs1; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_inst_xs2; // @[Controller.scala:131:25]
wire [4:0] _raw_cmd_q_io_deq_bits_cmd_inst_rd; // @[Controller.scala:131:25]
wire [6:0] _raw_cmd_q_io_deq_bits_cmd_inst_opcode; // @[Controller.scala:131:25]
wire [63:0] _raw_cmd_q_io_deq_bits_cmd_rs1; // @[Controller.scala:131:25]
wire [63:0] _raw_cmd_q_io_deq_bits_cmd_rs2; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_debug; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_cease; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_wfi; // @[Controller.scala:131:25]
wire [31:0] _raw_cmd_q_io_deq_bits_cmd_status_isa; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_dprv; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_dv; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_prv; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_v; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_sd; // @[Controller.scala:131:25]
wire [22:0] _raw_cmd_q_io_deq_bits_cmd_status_zero2; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_mpv; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_gva; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_mbe; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_sbe; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_sxl; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_uxl; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_sd_rv32; // @[Controller.scala:131:25]
wire [7:0] _raw_cmd_q_io_deq_bits_cmd_status_zero1; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_tsr; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_tw; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_tvm; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_mxr; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_sum; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_mprv; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_xs; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_fs; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_mpp; // @[Controller.scala:131:25]
wire [1:0] _raw_cmd_q_io_deq_bits_cmd_status_vs; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_spp; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_mpie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_ube; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_spie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_upie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_mie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_hie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_sie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_cmd_status_uie; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_rob_id_valid; // @[Controller.scala:131:25]
wire [5:0] _raw_cmd_q_io_deq_bits_rob_id_bits; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_from_matmul_fsm; // @[Controller.scala:131:25]
wire _raw_cmd_q_io_deq_bits_from_conv_fsm; // @[Controller.scala:131:25]
wire _reservation_station_io_alloc_ready; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_valid; // @[Controller.scala:124:61]
wire [6:0] _reservation_station_io_issue_ld_cmd_cmd_inst_funct; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_ld_cmd_cmd_inst_rs2; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_ld_cmd_cmd_inst_rs1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_inst_xd; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_inst_xs1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_inst_xs2; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_ld_cmd_cmd_inst_rd; // @[Controller.scala:124:61]
wire [6:0] _reservation_station_io_issue_ld_cmd_cmd_inst_opcode; // @[Controller.scala:124:61]
wire [63:0] _reservation_station_io_issue_ld_cmd_cmd_rs1; // @[Controller.scala:124:61]
wire [63:0] _reservation_station_io_issue_ld_cmd_cmd_rs2; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_debug; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_cease; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_wfi; // @[Controller.scala:124:61]
wire [31:0] _reservation_station_io_issue_ld_cmd_cmd_status_isa; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_dprv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_dv; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_prv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_v; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_sd; // @[Controller.scala:124:61]
wire [22:0] _reservation_station_io_issue_ld_cmd_cmd_status_zero2; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_mpv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_gva; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_mbe; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_sbe; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_sxl; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_uxl; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_sd_rv32; // @[Controller.scala:124:61]
wire [7:0] _reservation_station_io_issue_ld_cmd_cmd_status_zero1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_tsr; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_tw; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_tvm; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_mxr; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_sum; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_mprv; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_xs; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_fs; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_mpp; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ld_cmd_cmd_status_vs; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_spp; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_mpie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_ube; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_spie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_upie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_mie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_hie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_sie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_cmd_status_uie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_from_matmul_fsm; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ld_cmd_from_conv_fsm; // @[Controller.scala:124:61]
wire [5:0] _reservation_station_io_issue_ld_rob_id; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_valid; // @[Controller.scala:124:61]
wire [6:0] _reservation_station_io_issue_st_cmd_cmd_inst_funct; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_st_cmd_cmd_inst_rs2; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_st_cmd_cmd_inst_rs1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_inst_xd; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_inst_xs1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_inst_xs2; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_st_cmd_cmd_inst_rd; // @[Controller.scala:124:61]
wire [6:0] _reservation_station_io_issue_st_cmd_cmd_inst_opcode; // @[Controller.scala:124:61]
wire [63:0] _reservation_station_io_issue_st_cmd_cmd_rs1; // @[Controller.scala:124:61]
wire [63:0] _reservation_station_io_issue_st_cmd_cmd_rs2; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_debug; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_cease; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_wfi; // @[Controller.scala:124:61]
wire [31:0] _reservation_station_io_issue_st_cmd_cmd_status_isa; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_dprv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_dv; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_prv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_v; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_sd; // @[Controller.scala:124:61]
wire [22:0] _reservation_station_io_issue_st_cmd_cmd_status_zero2; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_mpv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_gva; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_mbe; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_sbe; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_sxl; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_uxl; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_sd_rv32; // @[Controller.scala:124:61]
wire [7:0] _reservation_station_io_issue_st_cmd_cmd_status_zero1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_tsr; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_tw; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_tvm; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_mxr; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_sum; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_mprv; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_xs; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_fs; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_mpp; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_st_cmd_cmd_status_vs; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_spp; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_mpie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_ube; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_spie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_upie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_mie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_hie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_sie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_cmd_status_uie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_from_matmul_fsm; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_st_cmd_from_conv_fsm; // @[Controller.scala:124:61]
wire [5:0] _reservation_station_io_issue_st_rob_id; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_valid; // @[Controller.scala:124:61]
wire [6:0] _reservation_station_io_issue_ex_cmd_cmd_inst_funct; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_ex_cmd_cmd_inst_rs2; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_ex_cmd_cmd_inst_rs1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_inst_xd; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_inst_xs1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_inst_xs2; // @[Controller.scala:124:61]
wire [4:0] _reservation_station_io_issue_ex_cmd_cmd_inst_rd; // @[Controller.scala:124:61]
wire [6:0] _reservation_station_io_issue_ex_cmd_cmd_inst_opcode; // @[Controller.scala:124:61]
wire [63:0] _reservation_station_io_issue_ex_cmd_cmd_rs1; // @[Controller.scala:124:61]
wire [63:0] _reservation_station_io_issue_ex_cmd_cmd_rs2; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_debug; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_cease; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_wfi; // @[Controller.scala:124:61]
wire [31:0] _reservation_station_io_issue_ex_cmd_cmd_status_isa; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_dprv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_dv; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_prv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_v; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_sd; // @[Controller.scala:124:61]
wire [22:0] _reservation_station_io_issue_ex_cmd_cmd_status_zero2; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_mpv; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_gva; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_mbe; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_sbe; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_sxl; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_uxl; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_sd_rv32; // @[Controller.scala:124:61]
wire [7:0] _reservation_station_io_issue_ex_cmd_cmd_status_zero1; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_tsr; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_tw; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_tvm; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_mxr; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_sum; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_mprv; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_xs; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_fs; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_mpp; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_issue_ex_cmd_cmd_status_vs; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_spp; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_mpie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_ube; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_spie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_upie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_mie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_hie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_sie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_cmd_status_uie; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_from_matmul_fsm; // @[Controller.scala:124:61]
wire _reservation_station_io_issue_ex_cmd_from_conv_fsm; // @[Controller.scala:124:61]
wire [5:0] _reservation_station_io_issue_ex_rob_id; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_conv_ld_completed; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_conv_ex_completed; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_conv_st_completed; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_matmul_ld_completed; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_matmul_ex_completed; // @[Controller.scala:124:61]
wire [1:0] _reservation_station_io_matmul_st_completed; // @[Controller.scala:124:61]
wire _reservation_station_io_busy; // @[Controller.scala:124:61]
wire _reservation_station_io_counter_event_signal_41; // @[Controller.scala:124:61]
wire _reservation_station_io_counter_event_signal_42; // @[Controller.scala:124:61]
wire [31:0] _reservation_station_io_counter_external_values_1; // @[Controller.scala:124:61]
wire [31:0] _reservation_station_io_counter_external_values_2; // @[Controller.scala:124:61]
wire [31:0] _reservation_station_io_counter_external_values_3; // @[Controller.scala:124:61]
wire _tlb_io_clients_0_resp_miss; // @[Controller.scala:69:19]
wire [31:0] _tlb_io_clients_0_resp_paddr; // @[Controller.scala:69:19]
wire [39:0] _tlb_io_clients_0_resp_gpa; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_pf_ld; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_pf_st; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_pf_inst; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_ae_ld; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_ae_st; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_ae_inst; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_cacheable; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_must_alloc; // @[Controller.scala:69:19]
wire _tlb_io_clients_0_resp_prefetchable; // @[Controller.scala:69:19]
wire [4:0] _tlb_io_clients_0_resp_cmd; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_miss; // @[Controller.scala:69:19]
wire [31:0] _tlb_io_clients_1_resp_paddr; // @[Controller.scala:69:19]
wire [39:0] _tlb_io_clients_1_resp_gpa; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_pf_ld; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_pf_st; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_pf_inst; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_ae_ld; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_ae_st; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_ae_inst; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_cacheable; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_must_alloc; // @[Controller.scala:69:19]
wire _tlb_io_clients_1_resp_prefetchable; // @[Controller.scala:69:19]
wire [4:0] _tlb_io_clients_1_resp_cmd; // @[Controller.scala:69:19]
wire _tlb_io_counter_event_signal_15; // @[Controller.scala:69:19]
wire _tlb_io_counter_event_signal_16; // @[Controller.scala:69:19]
wire _tlb_io_counter_event_signal_17; // @[Controller.scala:69:19]
wire _counters_io_in_ready; // @[Controller.scala:59:24]
wire _counters_io_event_io_external_reset; // @[Controller.scala:59:24]
wire _spad_io_dma_read_req_ready; // @[Controller.scala:36:24]
wire _spad_io_dma_read_resp_valid; // @[Controller.scala:36:24]
wire [15:0] _spad_io_dma_read_resp_bits_bytesRead; // @[Controller.scala:36:24]
wire [7:0] _spad_io_dma_read_resp_bits_cmd_id; // @[Controller.scala:36:24]
wire _spad_io_dma_write_req_ready; // @[Controller.scala:36:24]
wire _spad_io_dma_write_resp_valid; // @[Controller.scala:36:24]
wire [7:0] _spad_io_dma_write_resp_bits_cmd_id; // @[Controller.scala:36:24]
wire _spad_io_srams_read_0_req_ready; // @[Controller.scala:36:24]
wire _spad_io_srams_read_0_resp_valid; // @[Controller.scala:36:24]
wire [127:0] _spad_io_srams_read_0_resp_bits_data; // @[Controller.scala:36:24]
wire _spad_io_srams_read_0_resp_bits_fromDMA; // @[Controller.scala:36:24]
wire _spad_io_srams_read_1_req_ready; // @[Controller.scala:36:24]
wire _spad_io_srams_read_1_resp_valid; // @[Controller.scala:36:24]
wire [127:0] _spad_io_srams_read_1_resp_bits_data; // @[Controller.scala:36:24]
wire _spad_io_srams_read_1_resp_bits_fromDMA; // @[Controller.scala:36:24]
wire _spad_io_srams_read_2_req_ready; // @[Controller.scala:36:24]
wire _spad_io_srams_read_2_resp_valid; // @[Controller.scala:36:24]
wire [127:0] _spad_io_srams_read_2_resp_bits_data; // @[Controller.scala:36:24]
wire _spad_io_srams_read_2_resp_bits_fromDMA; // @[Controller.scala:36:24]
wire _spad_io_srams_read_3_req_ready; // @[Controller.scala:36:24]
wire _spad_io_srams_read_3_resp_valid; // @[Controller.scala:36:24]
wire [127:0] _spad_io_srams_read_3_resp_bits_data; // @[Controller.scala:36:24]
wire _spad_io_srams_read_3_resp_bits_fromDMA; // @[Controller.scala:36:24]
wire _spad_io_acc_read_req_0_ready; // @[Controller.scala:36:24]
wire _spad_io_acc_read_req_1_ready; // @[Controller.scala:36:24]
wire _spad_io_acc_read_resp_0_valid; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_0_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_1_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_2_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_3_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_4_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_5_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_6_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_7_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_8_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_9_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_10_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_11_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_12_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_13_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_14_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_0_bits_full_data_15_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_0_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_1_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_2_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_3_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_4_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_5_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_6_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_7_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_8_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_9_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_10_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_11_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_12_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_13_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_14_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_0_bits_data_15_0; // @[Controller.scala:36:24]
wire [1:0] _spad_io_acc_read_resp_0_bits_acc_bank_id; // @[Controller.scala:36:24]
wire _spad_io_acc_read_resp_0_bits_fromDMA; // @[Controller.scala:36:24]
wire _spad_io_acc_read_resp_1_valid; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_0_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_1_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_2_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_3_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_4_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_5_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_6_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_7_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_8_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_9_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_10_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_11_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_12_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_13_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_14_0; // @[Controller.scala:36:24]
wire [7:0] _spad_io_acc_read_resp_1_bits_full_data_15_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_0_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_1_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_2_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_3_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_4_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_5_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_6_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_7_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_8_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_9_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_10_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_11_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_12_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_13_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_14_0; // @[Controller.scala:36:24]
wire [31:0] _spad_io_acc_read_resp_1_bits_data_15_0; // @[Controller.scala:36:24]
wire [1:0] _spad_io_acc_read_resp_1_bits_acc_bank_id; // @[Controller.scala:36:24]
wire _spad_io_acc_read_resp_1_bits_fromDMA; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_valid; // @[Controller.scala:36:24]
wire [39:0] _spad_io_tlb_0_req_bits_tlb_req_vaddr; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_debug; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_cease; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_wfi; // @[Controller.scala:36:24]
wire [31:0] _spad_io_tlb_0_req_bits_status_isa; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_dprv; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_dv; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_prv; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_v; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_sd; // @[Controller.scala:36:24]
wire [22:0] _spad_io_tlb_0_req_bits_status_zero2; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_mpv; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_gva; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_mbe; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_sbe; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_sxl; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_uxl; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_sd_rv32; // @[Controller.scala:36:24]
wire [7:0] _spad_io_tlb_0_req_bits_status_zero1; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_tsr; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_tw; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_tvm; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_mxr; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_sum; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_mprv; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_xs; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_fs; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_mpp; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_0_req_bits_status_vs; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_spp; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_mpie; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_ube; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_spie; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_upie; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_mie; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_hie; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_sie; // @[Controller.scala:36:24]
wire _spad_io_tlb_0_req_bits_status_uie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_valid; // @[Controller.scala:36:24]
wire [39:0] _spad_io_tlb_1_req_bits_tlb_req_vaddr; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_debug; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_cease; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_wfi; // @[Controller.scala:36:24]
wire [31:0] _spad_io_tlb_1_req_bits_status_isa; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_dprv; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_dv; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_prv; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_v; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_sd; // @[Controller.scala:36:24]
wire [22:0] _spad_io_tlb_1_req_bits_status_zero2; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_mpv; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_gva; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_mbe; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_sbe; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_sxl; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_uxl; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_sd_rv32; // @[Controller.scala:36:24]
wire [7:0] _spad_io_tlb_1_req_bits_status_zero1; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_tsr; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_tw; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_tvm; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_mxr; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_sum; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_mprv; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_xs; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_fs; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_mpp; // @[Controller.scala:36:24]
wire [1:0] _spad_io_tlb_1_req_bits_status_vs; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_spp; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_mpie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_ube; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_spie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_upie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_mie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_hie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_sie; // @[Controller.scala:36:24]
wire _spad_io_tlb_1_req_bits_status_uie; // @[Controller.scala:36:24]
wire _spad_io_busy; // @[Controller.scala:36:24]
wire _spad_io_counter_event_signal_18; // @[Controller.scala:36:24]
wire _spad_io_counter_event_signal_19; // @[Controller.scala:36:24]
wire _spad_io_counter_event_signal_20; // @[Controller.scala:36:24]
wire _spad_io_counter_event_signal_21; // @[Controller.scala:36:24]
wire _spad_io_counter_event_signal_22; // @[Controller.scala:36:24]
wire _spad_io_counter_event_signal_23; // @[Controller.scala:36:24]
wire [31:0] _spad_io_counter_external_values_4; // @[Controller.scala:36:24]
wire [31:0] _spad_io_counter_external_values_5; // @[Controller.scala:36:24]
wire [31:0] _spad_io_counter_external_values_6; // @[Controller.scala:36:24]
wire [31:0] _spad_io_counter_external_values_7; // @[Controller.scala:36:24]
wire auto_spad_id_out_a_ready_0 = auto_spad_id_out_a_ready; // @[Controller.scala:45:7]
wire auto_spad_id_out_d_valid_0 = auto_spad_id_out_d_valid; // @[Controller.scala:45:7]
wire [2:0] auto_spad_id_out_d_bits_opcode_0 = auto_spad_id_out_d_bits_opcode; // @[Controller.scala:45:7]
wire [1:0] auto_spad_id_out_d_bits_param_0 = auto_spad_id_out_d_bits_param; // @[Controller.scala:45:7]
wire [3:0] auto_spad_id_out_d_bits_size_0 = auto_spad_id_out_d_bits_size; // @[Controller.scala:45:7]
wire [4:0] auto_spad_id_out_d_bits_source_0 = auto_spad_id_out_d_bits_source; // @[Controller.scala:45:7]
wire [3:0] auto_spad_id_out_d_bits_sink_0 = auto_spad_id_out_d_bits_sink; // @[Controller.scala:45:7]
wire auto_spad_id_out_d_bits_denied_0 = auto_spad_id_out_d_bits_denied; // @[Controller.scala:45:7]
wire [127:0] auto_spad_id_out_d_bits_data_0 = auto_spad_id_out_d_bits_data; // @[Controller.scala:45:7]
wire auto_spad_id_out_d_bits_corrupt_0 = auto_spad_id_out_d_bits_corrupt; // @[Controller.scala:45:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[Controller.scala:45:7]
wire [6:0] io_cmd_bits_inst_funct_0 = io_cmd_bits_inst_funct; // @[Controller.scala:45:7]
wire [4:0] io_cmd_bits_inst_rs2_0 = io_cmd_bits_inst_rs2; // @[Controller.scala:45:7]
wire [4:0] io_cmd_bits_inst_rs1_0 = io_cmd_bits_inst_rs1; // @[Controller.scala:45:7]
wire io_cmd_bits_inst_xd_0 = io_cmd_bits_inst_xd; // @[Controller.scala:45:7]
wire io_cmd_bits_inst_xs1_0 = io_cmd_bits_inst_xs1; // @[Controller.scala:45:7]
wire io_cmd_bits_inst_xs2_0 = io_cmd_bits_inst_xs2; // @[Controller.scala:45:7]
wire [4:0] io_cmd_bits_inst_rd_0 = io_cmd_bits_inst_rd; // @[Controller.scala:45:7]
wire [6:0] io_cmd_bits_inst_opcode_0 = io_cmd_bits_inst_opcode; // @[Controller.scala:45:7]
wire [63:0] io_cmd_bits_rs1_0 = io_cmd_bits_rs1; // @[Controller.scala:45:7]
wire [63:0] io_cmd_bits_rs2_0 = io_cmd_bits_rs2; // @[Controller.scala:45:7]
wire io_cmd_bits_status_debug_0 = io_cmd_bits_status_debug; // @[Controller.scala:45:7]
wire io_cmd_bits_status_cease_0 = io_cmd_bits_status_cease; // @[Controller.scala:45:7]
wire io_cmd_bits_status_wfi_0 = io_cmd_bits_status_wfi; // @[Controller.scala:45:7]
wire [31:0] io_cmd_bits_status_isa_0 = io_cmd_bits_status_isa; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_dprv_0 = io_cmd_bits_status_dprv; // @[Controller.scala:45:7]
wire io_cmd_bits_status_dv_0 = io_cmd_bits_status_dv; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_prv_0 = io_cmd_bits_status_prv; // @[Controller.scala:45:7]
wire io_cmd_bits_status_v_0 = io_cmd_bits_status_v; // @[Controller.scala:45:7]
wire io_cmd_bits_status_sd_0 = io_cmd_bits_status_sd; // @[Controller.scala:45:7]
wire [22:0] io_cmd_bits_status_zero2_0 = io_cmd_bits_status_zero2; // @[Controller.scala:45:7]
wire io_cmd_bits_status_mpv_0 = io_cmd_bits_status_mpv; // @[Controller.scala:45:7]
wire io_cmd_bits_status_gva_0 = io_cmd_bits_status_gva; // @[Controller.scala:45:7]
wire io_cmd_bits_status_mbe_0 = io_cmd_bits_status_mbe; // @[Controller.scala:45:7]
wire io_cmd_bits_status_sbe_0 = io_cmd_bits_status_sbe; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_sxl_0 = io_cmd_bits_status_sxl; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_uxl_0 = io_cmd_bits_status_uxl; // @[Controller.scala:45:7]
wire io_cmd_bits_status_sd_rv32_0 = io_cmd_bits_status_sd_rv32; // @[Controller.scala:45:7]
wire [7:0] io_cmd_bits_status_zero1_0 = io_cmd_bits_status_zero1; // @[Controller.scala:45:7]
wire io_cmd_bits_status_tsr_0 = io_cmd_bits_status_tsr; // @[Controller.scala:45:7]
wire io_cmd_bits_status_tw_0 = io_cmd_bits_status_tw; // @[Controller.scala:45:7]
wire io_cmd_bits_status_tvm_0 = io_cmd_bits_status_tvm; // @[Controller.scala:45:7]
wire io_cmd_bits_status_mxr_0 = io_cmd_bits_status_mxr; // @[Controller.scala:45:7]
wire io_cmd_bits_status_sum_0 = io_cmd_bits_status_sum; // @[Controller.scala:45:7]
wire io_cmd_bits_status_mprv_0 = io_cmd_bits_status_mprv; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_xs_0 = io_cmd_bits_status_xs; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_fs_0 = io_cmd_bits_status_fs; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_mpp_0 = io_cmd_bits_status_mpp; // @[Controller.scala:45:7]
wire [1:0] io_cmd_bits_status_vs_0 = io_cmd_bits_status_vs; // @[Controller.scala:45:7]
wire io_cmd_bits_status_spp_0 = io_cmd_bits_status_spp; // @[Controller.scala:45:7]
wire io_cmd_bits_status_mpie_0 = io_cmd_bits_status_mpie; // @[Controller.scala:45:7]
wire io_cmd_bits_status_ube_0 = io_cmd_bits_status_ube; // @[Controller.scala:45:7]
wire io_cmd_bits_status_spie_0 = io_cmd_bits_status_spie; // @[Controller.scala:45:7]
wire io_cmd_bits_status_upie_0 = io_cmd_bits_status_upie; // @[Controller.scala:45:7]
wire io_cmd_bits_status_mie_0 = io_cmd_bits_status_mie; // @[Controller.scala:45:7]
wire io_cmd_bits_status_hie_0 = io_cmd_bits_status_hie; // @[Controller.scala:45:7]
wire io_cmd_bits_status_sie_0 = io_cmd_bits_status_sie; // @[Controller.scala:45:7]
wire io_cmd_bits_status_uie_0 = io_cmd_bits_status_uie; // @[Controller.scala:45:7]
wire io_resp_ready_0 = io_resp_ready; // @[Controller.scala:45:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[Controller.scala:45:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[Controller.scala:45:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[Controller.scala:45:7]
wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[Controller.scala:45:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[Controller.scala:45:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[Controller.scala:45:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[Controller.scala:45:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[Controller.scala:45:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[Controller.scala:45:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[Controller.scala:45:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[Controller.scala:45:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[Controller.scala:45:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[Controller.scala:45:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[Controller.scala:45:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[Controller.scala:45:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[Controller.scala:45:7]
wire io_exception_0 = io_exception; // @[Controller.scala:45:7]
wire io_ptw_0_req_ready_0 = io_ptw_0_req_ready; // @[Controller.scala:45:7]
wire io_ptw_0_resp_valid_0 = io_ptw_0_resp_valid; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_ae_ptw_0 = io_ptw_0_resp_bits_ae_ptw; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_ae_final_0 = io_ptw_0_resp_bits_ae_final; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pf_0 = io_ptw_0_resp_bits_pf; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_gf_0 = io_ptw_0_resp_bits_gf; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_hr_0 = io_ptw_0_resp_bits_hr; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_hw_0 = io_ptw_0_resp_bits_hw; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_hx_0 = io_ptw_0_resp_bits_hx; // @[Controller.scala:45:7]
wire [9:0] io_ptw_0_resp_bits_pte_reserved_for_future_0 = io_ptw_0_resp_bits_pte_reserved_for_future; // @[Controller.scala:45:7]
wire [43:0] io_ptw_0_resp_bits_pte_ppn_0 = io_ptw_0_resp_bits_pte_ppn; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_resp_bits_pte_reserved_for_software_0 = io_ptw_0_resp_bits_pte_reserved_for_software; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_d_0 = io_ptw_0_resp_bits_pte_d; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_a_0 = io_ptw_0_resp_bits_pte_a; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_g_0 = io_ptw_0_resp_bits_pte_g; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_u_0 = io_ptw_0_resp_bits_pte_u; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_x_0 = io_ptw_0_resp_bits_pte_x; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_w_0 = io_ptw_0_resp_bits_pte_w; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_r_0 = io_ptw_0_resp_bits_pte_r; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_pte_v_0 = io_ptw_0_resp_bits_pte_v; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_resp_bits_level_0 = io_ptw_0_resp_bits_level; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_homogeneous_0 = io_ptw_0_resp_bits_homogeneous; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_gpa_valid_0 = io_ptw_0_resp_bits_gpa_valid; // @[Controller.scala:45:7]
wire [38:0] io_ptw_0_resp_bits_gpa_bits_0 = io_ptw_0_resp_bits_gpa_bits; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_gpa_is_pte_0 = io_ptw_0_resp_bits_gpa_is_pte; // @[Controller.scala:45:7]
wire [3:0] io_ptw_0_ptbr_mode_0 = io_ptw_0_ptbr_mode; // @[Controller.scala:45:7]
wire [43:0] io_ptw_0_ptbr_ppn_0 = io_ptw_0_ptbr_ppn; // @[Controller.scala:45:7]
wire io_ptw_0_status_debug_0 = io_ptw_0_status_debug; // @[Controller.scala:45:7]
wire io_ptw_0_status_cease_0 = io_ptw_0_status_cease; // @[Controller.scala:45:7]
wire io_ptw_0_status_wfi_0 = io_ptw_0_status_wfi; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_status_isa_0 = io_ptw_0_status_isa; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_dprv_0 = io_ptw_0_status_dprv; // @[Controller.scala:45:7]
wire io_ptw_0_status_dv_0 = io_ptw_0_status_dv; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_prv_0 = io_ptw_0_status_prv; // @[Controller.scala:45:7]
wire io_ptw_0_status_v_0 = io_ptw_0_status_v; // @[Controller.scala:45:7]
wire io_ptw_0_status_mpv_0 = io_ptw_0_status_mpv; // @[Controller.scala:45:7]
wire io_ptw_0_status_gva_0 = io_ptw_0_status_gva; // @[Controller.scala:45:7]
wire io_ptw_0_status_tsr_0 = io_ptw_0_status_tsr; // @[Controller.scala:45:7]
wire io_ptw_0_status_tw_0 = io_ptw_0_status_tw; // @[Controller.scala:45:7]
wire io_ptw_0_status_tvm_0 = io_ptw_0_status_tvm; // @[Controller.scala:45:7]
wire io_ptw_0_status_mxr_0 = io_ptw_0_status_mxr; // @[Controller.scala:45:7]
wire io_ptw_0_status_sum_0 = io_ptw_0_status_sum; // @[Controller.scala:45:7]
wire io_ptw_0_status_mprv_0 = io_ptw_0_status_mprv; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_fs_0 = io_ptw_0_status_fs; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_mpp_0 = io_ptw_0_status_mpp; // @[Controller.scala:45:7]
wire io_ptw_0_status_spp_0 = io_ptw_0_status_spp; // @[Controller.scala:45:7]
wire io_ptw_0_status_mpie_0 = io_ptw_0_status_mpie; // @[Controller.scala:45:7]
wire io_ptw_0_status_spie_0 = io_ptw_0_status_spie; // @[Controller.scala:45:7]
wire io_ptw_0_status_mie_0 = io_ptw_0_status_mie; // @[Controller.scala:45:7]
wire io_ptw_0_status_sie_0 = io_ptw_0_status_sie; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_spvp_0 = io_ptw_0_hstatus_spvp; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_spv_0 = io_ptw_0_hstatus_spv; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_gva_0 = io_ptw_0_hstatus_gva; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_debug_0 = io_ptw_0_gstatus_debug; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_cease_0 = io_ptw_0_gstatus_cease; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_wfi_0 = io_ptw_0_gstatus_wfi; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_gstatus_isa_0 = io_ptw_0_gstatus_isa; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_dprv_0 = io_ptw_0_gstatus_dprv; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_dv_0 = io_ptw_0_gstatus_dv; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_prv_0 = io_ptw_0_gstatus_prv; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_v_0 = io_ptw_0_gstatus_v; // @[Controller.scala:45:7]
wire [22:0] io_ptw_0_gstatus_zero2_0 = io_ptw_0_gstatus_zero2; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_mpv_0 = io_ptw_0_gstatus_mpv; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_gva_0 = io_ptw_0_gstatus_gva; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_mbe_0 = io_ptw_0_gstatus_mbe; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_sbe_0 = io_ptw_0_gstatus_sbe; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_sxl_0 = io_ptw_0_gstatus_sxl; // @[Controller.scala:45:7]
wire [7:0] io_ptw_0_gstatus_zero1_0 = io_ptw_0_gstatus_zero1; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_tsr_0 = io_ptw_0_gstatus_tsr; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_tw_0 = io_ptw_0_gstatus_tw; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_tvm_0 = io_ptw_0_gstatus_tvm; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_mxr_0 = io_ptw_0_gstatus_mxr; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_sum_0 = io_ptw_0_gstatus_sum; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_mprv_0 = io_ptw_0_gstatus_mprv; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_fs_0 = io_ptw_0_gstatus_fs; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_mpp_0 = io_ptw_0_gstatus_mpp; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_vs_0 = io_ptw_0_gstatus_vs; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_spp_0 = io_ptw_0_gstatus_spp; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_mpie_0 = io_ptw_0_gstatus_mpie; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_ube_0 = io_ptw_0_gstatus_ube; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_spie_0 = io_ptw_0_gstatus_spie; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_upie_0 = io_ptw_0_gstatus_upie; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_mie_0 = io_ptw_0_gstatus_mie; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_hie_0 = io_ptw_0_gstatus_hie; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_sie_0 = io_ptw_0_gstatus_sie; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_uie_0 = io_ptw_0_gstatus_uie; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_0_cfg_l_0 = io_ptw_0_pmp_0_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_0_cfg_a_0 = io_ptw_0_pmp_0_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_0_cfg_x_0 = io_ptw_0_pmp_0_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_0_cfg_w_0 = io_ptw_0_pmp_0_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_0_cfg_r_0 = io_ptw_0_pmp_0_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_0_addr_0 = io_ptw_0_pmp_0_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_0_mask_0 = io_ptw_0_pmp_0_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_1_cfg_l_0 = io_ptw_0_pmp_1_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_1_cfg_a_0 = io_ptw_0_pmp_1_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_1_cfg_x_0 = io_ptw_0_pmp_1_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_1_cfg_w_0 = io_ptw_0_pmp_1_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_1_cfg_r_0 = io_ptw_0_pmp_1_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_1_addr_0 = io_ptw_0_pmp_1_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_1_mask_0 = io_ptw_0_pmp_1_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_2_cfg_l_0 = io_ptw_0_pmp_2_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_2_cfg_a_0 = io_ptw_0_pmp_2_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_2_cfg_x_0 = io_ptw_0_pmp_2_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_2_cfg_w_0 = io_ptw_0_pmp_2_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_2_cfg_r_0 = io_ptw_0_pmp_2_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_2_addr_0 = io_ptw_0_pmp_2_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_2_mask_0 = io_ptw_0_pmp_2_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_3_cfg_l_0 = io_ptw_0_pmp_3_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_3_cfg_a_0 = io_ptw_0_pmp_3_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_3_cfg_x_0 = io_ptw_0_pmp_3_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_3_cfg_w_0 = io_ptw_0_pmp_3_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_3_cfg_r_0 = io_ptw_0_pmp_3_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_3_addr_0 = io_ptw_0_pmp_3_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_3_mask_0 = io_ptw_0_pmp_3_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_4_cfg_l_0 = io_ptw_0_pmp_4_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_4_cfg_a_0 = io_ptw_0_pmp_4_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_4_cfg_x_0 = io_ptw_0_pmp_4_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_4_cfg_w_0 = io_ptw_0_pmp_4_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_4_cfg_r_0 = io_ptw_0_pmp_4_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_4_addr_0 = io_ptw_0_pmp_4_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_4_mask_0 = io_ptw_0_pmp_4_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_5_cfg_l_0 = io_ptw_0_pmp_5_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_5_cfg_a_0 = io_ptw_0_pmp_5_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_5_cfg_x_0 = io_ptw_0_pmp_5_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_5_cfg_w_0 = io_ptw_0_pmp_5_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_5_cfg_r_0 = io_ptw_0_pmp_5_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_5_addr_0 = io_ptw_0_pmp_5_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_5_mask_0 = io_ptw_0_pmp_5_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_6_cfg_l_0 = io_ptw_0_pmp_6_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_6_cfg_a_0 = io_ptw_0_pmp_6_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_6_cfg_x_0 = io_ptw_0_pmp_6_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_6_cfg_w_0 = io_ptw_0_pmp_6_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_6_cfg_r_0 = io_ptw_0_pmp_6_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_6_addr_0 = io_ptw_0_pmp_6_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_6_mask_0 = io_ptw_0_pmp_6_mask; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_7_cfg_l_0 = io_ptw_0_pmp_7_cfg_l; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_7_cfg_a_0 = io_ptw_0_pmp_7_cfg_a; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_7_cfg_x_0 = io_ptw_0_pmp_7_cfg_x; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_7_cfg_w_0 = io_ptw_0_pmp_7_cfg_w; // @[Controller.scala:45:7]
wire io_ptw_0_pmp_7_cfg_r_0 = io_ptw_0_pmp_7_cfg_r; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_pmp_7_addr_0 = io_ptw_0_pmp_7_addr; // @[Controller.scala:45:7]
wire [31:0] io_ptw_0_pmp_7_mask_0 = io_ptw_0_pmp_7_mask; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_0_ren_0 = io_ptw_0_customCSRs_csrs_0_ren; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_0_wen_0 = io_ptw_0_customCSRs_csrs_0_wen; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_0_wdata_0 = io_ptw_0_customCSRs_csrs_0_wdata; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_0_value_0 = io_ptw_0_customCSRs_csrs_0_value; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_1_ren_0 = io_ptw_0_customCSRs_csrs_1_ren; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_1_wen_0 = io_ptw_0_customCSRs_csrs_1_wen; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_1_wdata_0 = io_ptw_0_customCSRs_csrs_1_wdata; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_1_value_0 = io_ptw_0_customCSRs_csrs_1_value; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_2_ren_0 = io_ptw_0_customCSRs_csrs_2_ren; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_2_wen_0 = io_ptw_0_customCSRs_csrs_2_wen; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_2_wdata_0 = io_ptw_0_customCSRs_csrs_2_wdata; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_2_value_0 = io_ptw_0_customCSRs_csrs_2_value; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_3_ren_0 = io_ptw_0_customCSRs_csrs_3_ren; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_3_wen_0 = io_ptw_0_customCSRs_csrs_3_wen; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_3_wdata_0 = io_ptw_0_customCSRs_csrs_3_wdata; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_3_value_0 = io_ptw_0_customCSRs_csrs_3_value; // @[Controller.scala:45:7]
wire io_mem_req_valid = 1'h0; // @[Controller.scala:45:7]
wire io_mem_req_bits_signed = 1'h0; // @[Controller.scala:45:7]
wire io_mem_req_bits_dv = 1'h0; // @[Controller.scala:45:7]
wire io_mem_req_bits_phys = 1'h0; // @[Controller.scala:45:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[Controller.scala:45:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[Controller.scala:45:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s1_kill = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_nack = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_nack_cause_raw = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_kill = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_uncached = 1'h0; // @[Controller.scala:45:7]
wire io_mem_replay_next = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_ma_st = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_pf_st = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_xcpt_ae_st = 1'h0; // @[Controller.scala:45:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[Controller.scala:45:7]
wire io_mem_ordered = 1'h0; // @[Controller.scala:45:7]
wire io_mem_store_pending = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_acquire = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_release = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_grant = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_tlbMiss = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_blocked = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Controller.scala:45:7]
wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[Controller.scala:45:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[Controller.scala:45:7]
wire io_mem_clock_enabled = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_req_bits_bits_vstage1 = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_req_bits_bits_stage2 = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_resp_bits_fragmented_superpage = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_mbe = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_sbe = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_sd_rv32 = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_ube = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_upie = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_hie = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_status_uie = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_vtsr = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_vtw = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_vtvm = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_hu = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_hstatus_vsbe = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_sd_rv32 = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_0_stall = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_0_set = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_1_stall = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_1_set = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_2_stall = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_2_set = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_3_stall = 1'h0; // @[Controller.scala:45:7]
wire io_ptw_0_customCSRs_csrs_3_set = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_ready = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_valid = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_ldst = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_wen = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_ren1 = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_ren2 = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_ren3 = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_swap12 = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_swap23 = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_fromint = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_toint = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_fastpipe = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_fma = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_div = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_sqrt = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_wflags = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_req_bits_vec = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_resp_ready = 1'h0; // @[Controller.scala:45:7]
wire io_fpu_resp_valid = 1'h0; // @[Controller.scala:45:7]
wire [15:0] io_ptw_0_ptbr_asid = 16'h0; // @[Controller.scala:45:7]
wire [15:0] io_ptw_0_hgatp_asid = 16'h0; // @[Controller.scala:45:7]
wire [15:0] io_ptw_0_vsatp_asid = 16'h0; // @[Controller.scala:45:7]
wire [3:0] io_ptw_0_hgatp_mode = 4'h0; // @[Controller.scala:45:7]
wire [3:0] io_ptw_0_vsatp_mode = 4'h0; // @[Controller.scala:45:7]
wire [43:0] io_ptw_0_hgatp_ppn = 44'h0; // @[Controller.scala:45:7]
wire [43:0] io_ptw_0_vsatp_ppn = 44'h0; // @[Controller.scala:45:7]
wire io_ptw_0_req_bits_valid = 1'h1; // @[Controller.scala:45:7]
wire io_ptw_0_status_sd = 1'h1; // @[Controller.scala:45:7]
wire io_ptw_0_gstatus_sd = 1'h1; // @[Controller.scala:45:7]
wire [22:0] io_ptw_0_status_zero2 = 23'h0; // @[Controller.scala:45:7]
wire [7:0] io_mem_req_bits_tag = 8'h0; // @[Controller.scala:45:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[Controller.scala:45:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[Controller.scala:45:7]
wire [7:0] io_ptw_0_status_zero1 = 8'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_xs = 2'h3; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_xs = 2'h3; // @[Controller.scala:45:7]
wire [1:0] io_mem_req_bits_size = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_mem_req_bits_dprv = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_vs = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_hstatus_zero3 = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_hstatus_zero2 = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_0_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_1_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_2_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_3_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_4_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_5_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_6_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_pmp_7_cfg_res = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_fpu_req_bits_typeTagIn = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_fpu_req_bits_typeTagOut = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_fpu_req_bits_fmaCmd = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_fpu_req_bits_typ = 2'h0; // @[Controller.scala:45:7]
wire [1:0] io_fpu_req_bits_fmt = 2'h0; // @[Controller.scala:45:7]
wire [29:0] io_ptw_0_hstatus_zero6 = 30'h0; // @[Controller.scala:45:7]
wire [8:0] io_ptw_0_hstatus_zero5 = 9'h0; // @[Controller.scala:45:7]
wire [5:0] io_ptw_0_hstatus_vgein = 6'h0; // @[Controller.scala:45:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[Controller.scala:45:7]
wire [4:0] io_ptw_0_hstatus_zero1 = 5'h0; // @[Controller.scala:45:7]
wire [4:0] io_fpu_resp_bits_exc = 5'h0; // @[Controller.scala:45:7]
wire [39:0] io_mem_req_bits_addr = 40'h0; // @[Controller.scala:45:7]
wire [39:0] io_mem_s2_gpa = 40'h0; // @[Controller.scala:45:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[Controller.scala:45:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_0_sdata = 64'h0; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_1_sdata = 64'h0; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_2_sdata = 64'h0; // @[Controller.scala:45:7]
wire [63:0] io_ptw_0_customCSRs_csrs_3_sdata = 64'h0; // @[Controller.scala:45:7]
wire [31:0] io_mem_s2_paddr = 32'h0; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_sxl = 2'h2; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_status_uxl = 2'h2; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_hstatus_vsxl = 2'h2; // @[Controller.scala:45:7]
wire [1:0] io_ptw_0_gstatus_uxl = 2'h2; // @[Controller.scala:45:7]
wire [2:0] io_fpu_req_bits_rm = 3'h0; // @[Controller.scala:45:7]
wire [64:0] io_fpu_req_bits_in1 = 65'h0; // @[Controller.scala:45:7]
wire [64:0] io_fpu_req_bits_in2 = 65'h0; // @[Controller.scala:45:7]
wire [64:0] io_fpu_req_bits_in3 = 65'h0; // @[Controller.scala:45:7]
wire [64:0] io_fpu_resp_bits_data = 65'h0; // @[Controller.scala:45:7]
wire _io_busy_T_6; // @[Controller.scala:330:178]
wire [2:0] auto_spad_id_out_a_bits_opcode_0; // @[Controller.scala:45:7]
wire [2:0] auto_spad_id_out_a_bits_param_0; // @[Controller.scala:45:7]
wire [3:0] auto_spad_id_out_a_bits_size_0; // @[Controller.scala:45:7]
wire [4:0] auto_spad_id_out_a_bits_source_0; // @[Controller.scala:45:7]
wire [31:0] auto_spad_id_out_a_bits_address_0; // @[Controller.scala:45:7]
wire [15:0] auto_spad_id_out_a_bits_mask_0; // @[Controller.scala:45:7]
wire [127:0] auto_spad_id_out_a_bits_data_0; // @[Controller.scala:45:7]
wire auto_spad_id_out_a_bits_corrupt_0; // @[Controller.scala:45:7]
wire auto_spad_id_out_a_valid_0; // @[Controller.scala:45:7]
wire auto_spad_id_out_d_ready_0; // @[Controller.scala:45:7]
wire io_cmd_ready_0; // @[Controller.scala:45:7]
wire [4:0] io_resp_bits_rd_0; // @[Controller.scala:45:7]
wire [63:0] io_resp_bits_data_0; // @[Controller.scala:45:7]
wire io_resp_valid_0; // @[Controller.scala:45:7]
wire [26:0] io_ptw_0_req_bits_bits_addr_0; // @[Controller.scala:45:7]
wire io_ptw_0_req_bits_bits_need_gpa_0; // @[Controller.scala:45:7]
wire io_ptw_0_req_valid_0; // @[Controller.scala:45:7]
wire io_busy_0; // @[Controller.scala:45:7]
wire io_interrupt_0; // @[Controller.scala:45:7]
wire _spad_io_flush_T = tlb_io_exp_0_flush_retry | tlb_io_exp_0_flush_skip; // @[FrontendTLB.scala:25:49]
reg clock_en_reg; // @[Controller.scala:81:29]
wire _clock_en_reg_T = io_cmd_bits_rs1_0[0]; // @[Controller.scala:45:7, :128:36]
wire _io_busy_T = _raw_cmd_q_io_deq_valid | _mod_io_busy; // @[LoopConv.scala:1542:21]
wire _io_busy_T_1 = _io_busy_T | _mod_1_io_busy; // @[LoopMatmul.scala:1127:21]
wire _io_busy_T_2 = _io_busy_T_1 | _reservation_station_io_busy; // @[Controller.scala:124:61, :330:{55,84}]
wire _io_busy_T_3 = _io_busy_T_2 | _spad_io_busy; // @[Controller.scala:36:24, :330:{84,115}]
wire _io_busy_T_4 = _io_busy_T_3 | _unrolled_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire _io_busy_T_5 = _io_busy_T_4 | _mod_1_io_out_valid; // @[LoopMatmul.scala:1127:21]
assign _io_busy_T_6 = _io_busy_T_5 | _mod_io_out_valid; // @[LoopConv.scala:1542:21]
assign io_busy_0 = _io_busy_T_6; // @[Controller.scala:45:7, :330:178]
wire _incr_ld_cycles_T = ~_store_controller_io_busy; // @[Controller.scala:189:58, :337:51]
wire _incr_ld_cycles_T_1 = _load_controller_io_busy & _incr_ld_cycles_T; // @[Controller.scala:188:57, :337:{48,51}]
wire _incr_ld_cycles_T_2 = ~_ex_controller_io_busy; // @[Controller.scala:190:55, :337:80]
wire incr_ld_cycles = _incr_ld_cycles_T_1 & _incr_ld_cycles_T_2; // @[Controller.scala:337:{48,77,80}]
wire _incr_st_cycles_T = ~_load_controller_io_busy; // @[Controller.scala:188:57, :338:24]
wire _incr_st_cycles_T_1 = _incr_st_cycles_T & _store_controller_io_busy; // @[Controller.scala:189:58, :338:{24,49}]
wire _incr_st_cycles_T_2 = ~_ex_controller_io_busy; // @[Controller.scala:190:55, :337:80, :338:80]
wire incr_st_cycles = _incr_st_cycles_T_1 & _incr_st_cycles_T_2; // @[Controller.scala:338:{49,77,80}]
wire _incr_ex_cycles_T = ~_load_controller_io_busy; // @[Controller.scala:188:57, :338:24, :339:24]
wire _incr_ex_cycles_T_1 = ~_store_controller_io_busy; // @[Controller.scala:189:58, :337:51, :339:52]
wire _incr_ex_cycles_T_2 = _incr_ex_cycles_T & _incr_ex_cycles_T_1; // @[Controller.scala:339:{24,49,52}]
wire incr_ex_cycles = _incr_ex_cycles_T_2 & _ex_controller_io_busy; // @[Controller.scala:190:55, :339:{49,78}]
wire _GEN = _load_controller_io_busy & _store_controller_io_busy; // @[Controller.scala:188:57, :189:58, :341:51]
wire _incr_ld_st_cycles_T; // @[Controller.scala:341:51]
assign _incr_ld_st_cycles_T = _GEN; // @[Controller.scala:341:51]
wire _incr_ld_st_ex_cycles_T; // @[Controller.scala:345:54]
assign _incr_ld_st_ex_cycles_T = _GEN; // @[Controller.scala:341:51, :345:54]
wire _incr_ld_st_cycles_T_1 = ~_ex_controller_io_busy; // @[Controller.scala:190:55, :337:80, :341:82]
wire incr_ld_st_cycles = _incr_ld_st_cycles_T & _incr_ld_st_cycles_T_1; // @[Controller.scala:341:{51,79,82}]
wire _incr_ld_ex_cycles_T = ~_store_controller_io_busy; // @[Controller.scala:189:58, :337:51, :342:54]
wire _incr_ld_ex_cycles_T_1 = _load_controller_io_busy & _incr_ld_ex_cycles_T; // @[Controller.scala:188:57, :342:{51,54}]
wire incr_ld_ex_cycles = _incr_ld_ex_cycles_T_1 & _ex_controller_io_busy; // @[Controller.scala:190:55, :342:{51,80}]
wire _incr_st_ex_cycles_T = ~_load_controller_io_busy; // @[Controller.scala:188:57, :338:24, :343:27]
wire _incr_st_ex_cycles_T_1 = _incr_st_ex_cycles_T & _store_controller_io_busy; // @[Controller.scala:189:58, :343:{27,52}]
wire incr_st_ex_cycles = _incr_st_ex_cycles_T_1 & _ex_controller_io_busy; // @[Controller.scala:190:55, :343:{52,80}]
wire incr_ld_st_ex_cycles = _incr_ld_st_ex_cycles_T & _ex_controller_io_busy; // @[Controller.scala:190:55, :345:{54,82}]
wire is_flush = _unrolled_cmd_q_io_deq_bits_cmd_inst_funct == 7'h7; // @[Decoupled.scala:362:21]
wire is_counter_op = _unrolled_cmd_q_io_deq_bits_cmd_inst_funct == 7'h7E; // @[Decoupled.scala:362:21]
wire is_clock_gate_en = _unrolled_cmd_q_io_deq_bits_cmd_inst_funct == 7'h16; // @[Decoupled.scala:362:21]
wire skip = _unrolled_cmd_q_io_deq_bits_cmd_rs1[0]; // @[Decoupled.scala:362:21]
wire _GEN_0 = _unrolled_cmd_q_io_deq_valid & is_flush; // @[Decoupled.scala:362:21]
assign tlb_io_exp_0_flush_skip = _GEN_0 & skip; // @[Controller.scala:72:35, :358:29, :375:21, :376:43, :377:39]
wire _tlb_io_exp_0_flush_retry_T = ~skip; // @[Controller.scala:376:43, :378:43]
assign tlb_io_exp_0_flush_retry = _GEN_0 & _tlb_io_exp_0_flush_retry_T; // @[Controller.scala:72:35, :73:36, :358:29, :375:21, :377:39, :378:{40,43}]
wire reservation_station_io_alloc_valid = _unrolled_cmd_q_io_deq_valid & ~(is_flush | is_counter_op | is_clock_gate_en); // @[Decoupled.scala:362:21]
reg [31:0] pipeline_stall_counter; // @[Controller.scala:405:39]
wire [32:0] _pipeline_stall_counter_T = {1'h0, pipeline_stall_counter} + 33'h1; // @[Controller.scala:405:39, :409:54]
wire [31:0] _pipeline_stall_counter_T_1 = _pipeline_stall_counter_T[31:0]; // @[Controller.scala:409:54] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire _source_ok_T_76 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_1355 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1355; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1208 = _T_1282 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1208 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1208 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1208 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1208 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1208 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1254 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1223 = _T_1355 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1223 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1223 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1223 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1308 = _T_1355 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1308 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1308 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1308 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_26 = 1'h1; // @[Parameters.scala:54:32]
wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_28 = 1'h1; // @[Parameters.scala:54:67]
wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_30 = 1'h1; // @[Parameters.scala:56:48]
wire _legal_source_WIRE_5 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_91 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:56:32]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [5:0] io_in_b_bits_source = 6'h20; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_55 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_56 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_57 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_58 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_59 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_1 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_2 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_3 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_4 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_T_37 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_43 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_44 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_WIRE_1 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _uncommonBits_T_60 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_61 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_62 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_63 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_64 = 6'h20; // @[Parameters.scala:52:29]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34]
wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7]
wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_31 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_33 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _legal_source_T_34 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_59 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_4 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_64 = 2'h0; // @[Parameters.scala:52:56]
wire [4:0] _legal_source_T_32 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_39 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_40 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_35 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_1 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_7 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_13 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_19 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] _legal_source_T_25 = 4'h8; // @[Parameters.scala:54:10]
wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_37 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_38 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_44 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_50 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_56 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_62 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_39 = _source_ok_T_38 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = _source_ok_T_44 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = _source_ok_T_50 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_57 = _source_ok_T_56 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_63 = _source_ok_T_62 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_67 = _source_ok_T_65 & _source_ok_T_66; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire _source_ok_T_68 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire _source_ok_T_69 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_73 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_74 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_75 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_81 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_87 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_93 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_99 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_88 = _source_ok_T_87 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_92 = _source_ok_T_90; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_94 = _source_ok_T_93 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_98; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_100 = _source_ok_T_99 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_103 = source_ok_uncommonBits_14 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_104 = _source_ok_T_102 & _source_ok_T_103; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2_5 = _source_ok_T_104; // @[Parameters.scala:1138:31]
wire _source_ok_T_105 = io_in_c_bits_source_0 == 6'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_6 = _source_ok_T_105; // @[Parameters.scala:1138:31]
wire _source_ok_T_106 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_110 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_74 = _uncommonBits_T_74[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_84 = _uncommonBits_T_84[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31]
wire _T_2103 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2103; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2103; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2177 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2177; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2177; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2177; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2177; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [2:0] b_first_counter; // @[Edges.scala:229:27]
wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2174 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2174; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2174; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [36:0] inflight; // @[Monitor.scala:614:27]
reg [147:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [147:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [36:0] a_set; // @[Monitor.scala:626:34]
wire [36:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [147:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [147:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [147:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [147:0] _a_opcode_lookup_T_6 = {144'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [147:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[147:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [147:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [147:0] _a_size_lookup_T_6 = {144'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [147:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[147:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire _T_2029 = _T_2103 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2029 ? _a_set_T[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2029 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2029 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2029 ? _a_opcodes_set_T_1[147:0] : 148'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2029 ? _a_sizes_set_T_1[147:0] : 148'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [36:0] d_clr; // @[Monitor.scala:664:34]
wire [36:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [147:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [147:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2075 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2075 & ~d_release_ack ? _d_clr_wo_ready_T[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire _T_2044 = _T_2177 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2044 ? _d_clr_T[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2044 ? _d_opcodes_clr_T_5[147:0] : 148'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2044 ? _d_sizes_clr_T_5[147:0] : 148'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [36:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [36:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [36:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [147:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [147:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [147:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [147:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [147:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [147:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [36:0] inflight_1; // @[Monitor.scala:726:35]
reg [147:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [147:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [36:0] c_set; // @[Monitor.scala:738:34]
wire [36:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [147:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [147:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [147:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [147:0] _c_opcode_lookup_T_6 = {144'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [147:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[147:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [147:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [147:0] _c_size_lookup_T_6 = {144'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [147:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[147:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire _T_2116 = _T_2174 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2116 ? _c_set_T[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2116 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2116 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2116 ? _c_opcodes_set_T_1[147:0] : 148'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2116 ? _c_sizes_set_T_1[147:0] : 148'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [36:0] d_clr_1; // @[Monitor.scala:774:34]
wire [36:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [147:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [147:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2147 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2147 & d_release_ack_1 ? _d_clr_wo_ready_T_1[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire _T_2129 = _T_2177 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2129 ? _d_clr_T_1[36:0] : 37'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2129 ? _d_opcodes_clr_T_11[147:0] : 148'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2129 ? _d_sizes_clr_T_11[147:0] : 148'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [36:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [36:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [36:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [147:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [147:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [147:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [147:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [147:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [147:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [6:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [6:0] d_set; // @[Monitor.scala:833:25]
wire _T_2183 = _T_2177 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2183 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
wire [6:0] e_clr; // @[Monitor.scala:839:25]
wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_2( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_19 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
| module MulAddRecFNPipe_l2_e8_s24_4( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [32:0] io_a, // @[FPU.scala:638:16]
input [32:0] io_b, // @[FPU.scala:638:16]
input [32:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [32:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [32:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [32:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [32:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [32:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [9:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [26:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e8_s24_4 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e8_s24_4 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e8_s24_8 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IdIndexer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{log2Ceil, Cat}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.IdRange
import freechips.rocketchip.util.{ControlKey, SimpleBundleField}
case object AXI4ExtraId extends ControlKey[UInt]("extra_id")
case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(Output(UInt(width.W)), 0.U)
/** This adapter limits the set of FIFO domain ids used by outbound transactions.
*
* Extra AWID and ARID bits from upstream transactions are stored in a User Bits field called AXI4ExtraId,
* which values are expected to be echoed back to this adapter alongside any downstream response messages,
* and are then prepended to the RID and BID field to restore the original identifier.
*
* @param idBits is the desired number of A[W|R]ID bits to be used
*/
class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
{
require (idBits >= 0, s"AXI4IdIndexer: idBits must be > 0, not $idBits")
val node = AXI4AdapterNode(
masterFn = { mp =>
// Create one new "master" per ID
val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters(
name = "",
id = IdRange(i, i+1),
aligned = true,
maxFlight = Some(0))
}
// Accumulate the names of masters we squish
val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() }
// Squash the information from original masters into new ID masters
mp.masters.foreach { m =>
for (i <- m.id.start until m.id.end) {
val j = i % (1 << idBits)
val accumulated = masters(j)
names(j) += m.name
masters(j) = accumulated.copy(
aligned = accumulated.aligned && m.aligned,
maxFlight = accumulated.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } })
}
}
val finalNameStrings = names.map { n => if (n.isEmpty) "(unused)" else n.toList.mkString(", ") }
val bits = log2Ceil(mp.endId) - idBits
val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil
mp.copy(
echoFields = field ++ mp.echoFields,
masters = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) })
},
slaveFn = { sp => sp
})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Leave everything mostly untouched
Connectable.waiveUnmatched(out.ar, in.ar) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(out.aw, in.aw) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(out.w, in.w) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(in.b, out.b) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(in.r, out.r) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
val bits = log2Ceil(edgeIn.master.endId) - idBits
if (bits > 0) {
// (in.aX.bits.id >> idBits).width = bits > 0
out.ar.bits.echo(AXI4ExtraId) := in.ar.bits.id >> idBits
out.aw.bits.echo(AXI4ExtraId) := in.aw.bits.id >> idBits
// Special care is needed in case of 0 idBits, b/c .id has width 1 still
if (idBits == 0) {
out.ar.bits.id := 0.U
out.aw.bits.id := 0.U
in.r.bits.id := out.r.bits.echo(AXI4ExtraId)
in.b.bits.id := out.b.bits.echo(AXI4ExtraId)
} else {
in.r.bits.id := Cat(out.r.bits.echo(AXI4ExtraId), out.r.bits.id)
in.b.bits.id := Cat(out.b.bits.echo(AXI4ExtraId), out.b.bits.id)
}
}
}
}
}
object AXI4IdIndexer
{
def apply(idBits: Int)(implicit p: Parameters): AXI4Node =
{
val axi4index = LazyModule(new AXI4IdIndexer(idBits))
axi4index.node
}
}
File ToAXI4.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField}
import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp}
import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1}
import freechips.rocketchip.util.DataToAugmentedData
class AXI4TLStateBundle(val sourceBits: Int) extends Bundle {
val size = UInt(4.W)
val source = UInt((sourceBits max 1).W)
}
case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state")
case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLtoAXI4IdMap serves as a record for the translation performed between id spaces.
*
* Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy.
* Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module.
*/
class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry]
{
val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType)
private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size }
private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init
val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) =>
AXI4MasterParameters(
name = tl.name,
id = IdRange(start, start+size),
aligned = true,
maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1),
nodePath = tl.nodePath)
}
private val axi4IdEnd = axi4Masters.map(_.id.end).max
private val axiDigits = String.valueOf(axi4IdEnd-1).length()
private val tlDigits = String.valueOf(tlPort.endSourceId-1).length()
protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s"
val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) =>
TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo)
}
}
case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = axi4Id
val maxTransactionsInFlight = Some(tlId.size)
}
case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
dFn = { p =>
AXI4MasterPortParameters(
masters = (new TLtoAXI4IdMap(p)).axi4Masters,
requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]),
echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields,
responseKeys = p.responseKeys)
},
uFn = { p => TLSlavePortParameters.v1(
managers = p.slaves.map { case s =>
TLSlaveParameters.v1(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,
supportsGet = s.supportsRead,
supportsPutFull = s.supportsWrite,
supportsPutPartial = s.supportsWrite,
fifoId = Some(0),
mayDenyPut = true,
mayDenyGet = true)},
beatBytes = p.beatBytes,
minLatency = p.minLatency,
responseFields = p.responseFields,
requestKeys = AMBAProt +: p.requestKeys)
})
// wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys
class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4")
val node = TLToAXI4Node(wcorrupt)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val slaves = edgeOut.slave.slaves
// All pairs of slaves must promise that they will never interleave data
require (slaves(0).interleavedId.isDefined)
slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
// Construct the source=>ID mapping table
val map = new TLtoAXI4IdMap(edgeIn.client)
val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B))
val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id)))
val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B))
var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] }
map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) =>
for (i <- 0 until tlId.size) {
val id = axi4Id.start + (if (fifo) 0 else i)
sourceStall(tlId.start + i) := idStall(id)
sourceTable(tlId.start + i) := id.U
}
if (fifo) { idCount(axi4Id.start) = Some(tlId.size) }
}
adapterName.foreach { n =>
println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n")
ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""")
}
// We need to keep the following state from A => D: (size, source)
// All of those fields could potentially require 0 bits (argh. Chisel.)
// We will pack all of that extra information into the echo bits.
require (log2Ceil(edgeIn.maxLgSize+1) <= 4)
val a_address = edgeIn.address(in.a.bits)
val a_source = in.a.bits.source
val a_size = edgeIn.size(in.a.bits)
val a_isPut = edgeIn.hasData(in.a.bits)
val (a_first, a_last, _) = edgeIn.firstlast(in.a)
val r_state = out.r.bits.echo(AXI4TLState)
val r_source = r_state.source
val r_size = r_state.size
val b_state = out.b.bits.echo(AXI4TLState)
val b_source = b_state.source
val b_size = b_state.size
// We need these Queues because AXI4 queues are irrevocable
val depth = if (combinational) 1 else 2
val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
val out_w = Wire(chiselTypeOf(out.w))
out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational)
val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational)
// Fan out the ARW channel to AR and AW
out.ar.bits := queue_arw.bits
out.aw.bits := queue_arw.bits
out.ar.valid := queue_arw.valid && !queue_arw.bits.wen
out.aw.valid := queue_arw.valid && queue_arw.bits.wen
queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready)
val beatBytes = edgeIn.manager.beatBytes
val maxSize = log2Ceil(beatBytes).U
val doneAW = RegInit(false.B)
when (in.a.fire) { doneAW := !a_last }
val arw = out_arw.bits
arw.wen := a_isPut
arw.id := sourceTable(a_source)
arw.addr := a_address
arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes)
arw.size := Mux(a_size >= maxSize, maxSize, a_size)
arw.burst := AXI4Parameters.BURST_INCR
arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee)
arw.cache := 0.U // do not allow AXI to modify our transactions
arw.prot := AXI4Parameters.PROT_PRIVILEGED
arw.qos := 0.U // no QoS
Connectable.waiveUnmatched(arw.user, in.a.bits.user) match {
case (lhs, rhs) => lhs :<= rhs
}
Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = arw.echo(AXI4TLState)
a_extra.source := a_source
a_extra.size := a_size
in.a.bits.user.lift(AMBAProt).foreach { x =>
val prot = Wire(Vec(3, Bool()))
val cache = Wire(Vec(4, Bool()))
prot(0) := x.privileged
prot(1) := !x.secure
prot(2) := x.fetch
cache(0) := x.bufferable
cache(1) := x.modifiable
cache(2) := x.readalloc
cache(3) := x.writealloc
arw.prot := Cat(prot.reverse)
arw.cache := Cat(cache.reverse)
}
val stall = sourceStall(in.a.bits.source) && a_first
in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready)
out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B)
out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready)
out_w.bits.data := in.a.bits.data
out_w.bits.strb := in.a.bits.mask
out_w.bits.last := a_last
out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt }
// R and B => D arbitration
val r_holds_d = RegInit(false.B)
when (out.r.fire) { r_holds_d := !out.r.bits.last }
// Give R higher priority than B, unless B has been delayed for 8 cycles
val b_delay = Reg(UInt(3.W))
when (out.b.valid && !out.b.ready) {
b_delay := b_delay + 1.U
} .otherwise {
b_delay := 0.U
}
val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d
out.r.ready := in.d.ready && r_wins
out.b.ready := in.d.ready && !r_wins
in.d.valid := Mux(r_wins, out.r.valid, out.b.valid)
// If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied
// request. We must pulse extend this value as AXI is allowed to change the
// value of RRESP on every beat, and ChipLink may not.
val r_first = RegInit(true.B)
when (out.r.fire) { r_first := out.r.bits.last }
val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first
val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied)
val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied)
Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
in.d.bits := Mux(r_wins, r_d, b_d)
in.d.bits.data := out.r.bits.data // avoid a costly Mux
// We need to track if any reads or writes are inflight for a given ID.
// If the opposite type arrives, we must stall until it completes.
val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools
val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools
val d_last = Mux(r_wins, out.r.bits.last, true.B)
// If FIFO was requested, ensure that R+W ordering is preserved
(a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) =>
// AXI does not guarantee read vs. write ordering. In particular, if we
// are in the middle of receiving a read burst and then issue a write,
// the write might affect the read burst. This violates FIFO behaviour.
// To solve this, we must wait until the last beat of a burst, but this
// means that a TileLink master which performs early source reuse can
// have one more transaction inflight than we promised AXI; stall it too.
val maxCount = n.getOrElse(1)
val count = RegInit(0.U(log2Ceil(maxCount + 1).W))
val write = Reg(Bool())
val idle = count === 0.U
val inc = as && out_arw.fire
val dec = ds && d_last && in.d.fire
count := count + inc.asUInt - dec.asUInt
assert (!dec || count =/= 0.U) // underflow
assert (!inc || count =/= maxCount.U) // overflow
when (inc) { write := arw.wen }
// If only one transaction can be inflight, it can't mismatch
val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B }
s := (!idle && mismatch) || (count === maxCount.U)
}
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
}
object TLToAXI4
{
def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) =
{
val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt))
tl2axi4.node
}
def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = {
if ( a.supports.probe && !b.supports.probe) return false
if (!a.supports.probe && b.supports.probe) return true
if ( a.requestFifo && !b.requestFifo ) return false
if (!a.requestFifo && b.requestFifo ) return true
return false
}
}
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File UserYanker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Queue, QueueIO, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.BundleMap
/** This adapter prunes all user bit fields of the echo type from request messages,
* storing them in queues and echoing them back when matching response messages are received.
*
* It also optionally rate limits the number of transactions that can be in flight simultaneously
* per FIFO domain / A[W|R]ID.
*
* @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID.
*/
class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
{
val node = AXI4AdapterNode(
masterFn = { mp => mp.copy(
masters = mp.masters.map { m => m.copy(
maxFlight = (m.maxFlight, capMaxFlight) match {
case (Some(x), Some(y)) => Some(x min y)
case (Some(x), None) => Some(x)
case (None, Some(y)) => Some(y)
case (None, None) => None })},
echoFields = Nil)},
slaveFn = { sp => sp })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Which fields are we stripping?
val echoFields = edgeIn.master.echoFields
val need_bypass = edgeOut.slave.minLatency < 1
edgeOut.master.masters.foreach { m =>
require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID")
}
def queue(id: Int) = {
val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0)
if (depth == 0) {
Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value
} else {
Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io
}
}
val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val arid = in.ar.bits.id
val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid)
in .ar.ready := out.ar.ready && ar_ready
out.ar.valid := in .ar.valid && ar_ready
Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match {
case (lhs, rhs) => lhs :<= rhs
}
val rid = out.r.bits.id
val r_valid = VecInit(rqueues.map(_.deq.valid))(rid)
val r_bits = VecInit(rqueues.map(_.deq.bits))(rid)
assert (!out.r.valid || r_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.r, out.r) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.r.bits.echo :<= r_bits
val arsel = UIntToOH(arid, edgeIn.master.endId).asBools
val rsel = UIntToOH(rid, edgeIn.master.endId).asBools
(rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) =>
q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .ar.valid && out.ar.ready && ar
q.enq.ready := DontCare
q.enq.bits :<>= in.ar.bits.echo
q.count := DontCare
}
val awid = in.aw.bits.id
val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid)
in .aw.ready := out.aw.ready && aw_ready
out.aw.valid := in .aw.valid && aw_ready
Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match {
case (lhs, rhs) => lhs :<>= rhs
}
val bid = out.b.bits.id
val b_valid = VecInit(wqueues.map(_.deq.valid))(bid)
val b_bits = VecInit(wqueues.map(_.deq.bits))(bid)
assert (!out.b.valid || b_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.b, out.b) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.b.bits.echo :<>= b_bits
val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
val bsel = UIntToOH(bid, edgeIn.master.endId).asBools
(wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) =>
q.deq.ready := out.b .valid && in .b .ready && b
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .aw.valid && out.aw.ready && aw
q.enq.ready := DontCare
q.enq.bits :<>= in.aw.bits.echo
q.count := DontCare
}
out.w :<>= in.w
}
}
}
object AXI4UserYanker
{
def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
{
val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
axi4yank.node
}
}
| module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_2( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire _tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala:301:29]
wire [31:0] _tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_w_valid; // @[ToAXI4.scala:301:29]
wire [63:0] _tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_b_ready; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala:301:29]
wire [31:0] _tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_r_ready; // @[ToAXI4.scala:301:29]
wire _axi4index_auto_in_aw_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_w_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_b_valid; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_in_b_bits_id; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_b_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_in_b_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_ar_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_r_valid; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_in_r_bits_id; // @[IdIndexer.scala:108:31]
wire [63:0] _axi4index_auto_in_r_bits_data; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_r_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_in_r_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_r_bits_last; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_aw_valid; // @[IdIndexer.scala:108:31]
wire [6:0] _axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala:108:31]
wire [31:0] _axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_aw_bits_echo_extra_id; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_w_valid; // @[IdIndexer.scala:108:31]
wire [63:0] _axi4index_auto_out_w_bits_data; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_w_bits_last; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_b_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_ar_valid; // @[IdIndexer.scala:108:31]
wire [6:0] _axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala:108:31]
wire [31:0] _axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_ar_bits_echo_extra_id; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_r_ready; // @[IdIndexer.scala:108:31]
wire _axi4yank_auto_in_aw_ready; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_w_ready; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_b_valid; // @[UserYanker.scala:125:30]
wire [6:0] _axi4yank_auto_in_b_bits_id; // @[UserYanker.scala:125:30]
wire [1:0] _axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_b_bits_echo_tl_state_size; // @[UserYanker.scala:125:30]
wire [7:0] _axi4yank_auto_in_b_bits_echo_tl_state_source; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_b_bits_echo_extra_id; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_ar_ready; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_r_valid; // @[UserYanker.scala:125:30]
wire [6:0] _axi4yank_auto_in_r_bits_id; // @[UserYanker.scala:125:30]
wire [63:0] _axi4yank_auto_in_r_bits_data; // @[UserYanker.scala:125:30]
wire [1:0] _axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_r_bits_echo_tl_state_size; // @[UserYanker.scala:125:30]
wire [7:0] _axi4yank_auto_in_r_bits_echo_tl_state_source; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_r_bits_echo_extra_id; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_r_bits_last; // @[UserYanker.scala:125:30]
wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_aw_ready_0 = auto_axi4yank_out_aw_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_w_ready_0 = auto_axi4yank_out_w_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_b_valid_0 = auto_axi4yank_out_b_valid; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_axi4yank_out_b_bits_id_0 = auto_axi4yank_out_b_bits_id; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_b_bits_resp_0 = auto_axi4yank_out_b_bits_resp; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_ar_ready_0 = auto_axi4yank_out_ar_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_r_valid_0 = auto_axi4yank_out_r_valid; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_axi4yank_out_r_bits_id_0 = auto_axi4yank_out_r_bits_id; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_axi4yank_out_r_bits_data_0 = auto_axi4yank_out_r_bits_data; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_r_bits_resp_0 = auto_axi4yank_out_r_bits_resp; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_r_bits_last_0 = auto_axi4yank_out_r_bits_last; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_d_bits_source_0 = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire auto_tl_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire auto_tl_out_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_out_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_anonOut_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_anonIn_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire tlOut_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire tlIn_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] auto_widget_anon_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] auto_tl_out_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] widget_auto_anon_out_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] widget_anonOut_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] widget_anonIn_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_a_valid = auto_widget_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode = auto_widget_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param = auto_widget_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_size = auto_widget_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_a_bits_source = auto_widget_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address = auto_widget_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_a_bits_mask = auto_widget_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_a_bits_data = auto_widget_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_bits_corrupt = auto_widget_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready = auto_widget_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [31:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_d_bits_source = auto_tl_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_axi4yank_out_aw_bits_id_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_axi4yank_out_aw_bits_addr_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_axi4yank_out_aw_bits_len_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_aw_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_aw_bits_burst_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_aw_bits_lock_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_aw_bits_cache_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_aw_bits_prot_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_aw_bits_qos_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_aw_valid_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_axi4yank_out_w_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_axi4yank_out_w_bits_strb_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_w_bits_last_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_w_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_b_ready_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_axi4yank_out_ar_bits_id_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_axi4yank_out_ar_bits_addr_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_axi4yank_out_ar_bits_len_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_ar_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_ar_bits_burst_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_ar_bits_lock_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_ar_bits_cache_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_ar_bits_prot_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_ar_bits_qos_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_ar_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_r_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_a_ready_0 = widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_bits_corrupt = widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_valid_0 = widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_opcode_0 = widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_size_0 = widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_source_0 = widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_denied_0 = widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_data_0 = widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_corrupt_0 = widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_corrupt = widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_corrupt = widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_param_0 = tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_source_0 = tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
AXI4UserYanker_2 axi4yank ( // @[UserYanker.scala:125:30]
.clock (clock),
.reset (reset),
.auto_in_aw_ready (_axi4yank_auto_in_aw_ready),
.auto_in_aw_valid (_axi4index_auto_out_aw_valid), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_id (_axi4index_auto_out_aw_bits_id), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_addr (_axi4index_auto_out_aw_bits_addr), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_len (_axi4index_auto_out_aw_bits_len), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_size (_axi4index_auto_out_aw_bits_size), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_burst (_axi4index_auto_out_aw_bits_burst), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_lock (_axi4index_auto_out_aw_bits_lock), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_cache (_axi4index_auto_out_aw_bits_cache), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_prot (_axi4index_auto_out_aw_bits_prot), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_qos (_axi4index_auto_out_aw_bits_qos), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_echo_extra_id (_axi4index_auto_out_aw_bits_echo_extra_id), // @[IdIndexer.scala:108:31]
.auto_in_w_ready (_axi4yank_auto_in_w_ready),
.auto_in_w_valid (_axi4index_auto_out_w_valid), // @[IdIndexer.scala:108:31]
.auto_in_w_bits_data (_axi4index_auto_out_w_bits_data), // @[IdIndexer.scala:108:31]
.auto_in_w_bits_strb (_axi4index_auto_out_w_bits_strb), // @[IdIndexer.scala:108:31]
.auto_in_w_bits_last (_axi4index_auto_out_w_bits_last), // @[IdIndexer.scala:108:31]
.auto_in_b_ready (_axi4index_auto_out_b_ready), // @[IdIndexer.scala:108:31]
.auto_in_b_valid (_axi4yank_auto_in_b_valid),
.auto_in_b_bits_id (_axi4yank_auto_in_b_bits_id),
.auto_in_b_bits_resp (_axi4yank_auto_in_b_bits_resp),
.auto_in_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size),
.auto_in_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source),
.auto_in_b_bits_echo_extra_id (_axi4yank_auto_in_b_bits_echo_extra_id),
.auto_in_ar_ready (_axi4yank_auto_in_ar_ready),
.auto_in_ar_valid (_axi4index_auto_out_ar_valid), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_id (_axi4index_auto_out_ar_bits_id), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_addr (_axi4index_auto_out_ar_bits_addr), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_len (_axi4index_auto_out_ar_bits_len), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_size (_axi4index_auto_out_ar_bits_size), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_burst (_axi4index_auto_out_ar_bits_burst), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_lock (_axi4index_auto_out_ar_bits_lock), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_cache (_axi4index_auto_out_ar_bits_cache), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_prot (_axi4index_auto_out_ar_bits_prot), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_qos (_axi4index_auto_out_ar_bits_qos), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_echo_extra_id (_axi4index_auto_out_ar_bits_echo_extra_id), // @[IdIndexer.scala:108:31]
.auto_in_r_ready (_axi4index_auto_out_r_ready), // @[IdIndexer.scala:108:31]
.auto_in_r_valid (_axi4yank_auto_in_r_valid),
.auto_in_r_bits_id (_axi4yank_auto_in_r_bits_id),
.auto_in_r_bits_data (_axi4yank_auto_in_r_bits_data),
.auto_in_r_bits_resp (_axi4yank_auto_in_r_bits_resp),
.auto_in_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size),
.auto_in_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source),
.auto_in_r_bits_echo_extra_id (_axi4yank_auto_in_r_bits_echo_extra_id),
.auto_in_r_bits_last (_axi4yank_auto_in_r_bits_last),
.auto_out_aw_ready (auto_axi4yank_out_aw_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_out_aw_valid (auto_axi4yank_out_aw_valid_0),
.auto_out_aw_bits_id (auto_axi4yank_out_aw_bits_id_0),
.auto_out_aw_bits_addr (auto_axi4yank_out_aw_bits_addr_0),
.auto_out_aw_bits_len (auto_axi4yank_out_aw_bits_len_0),
.auto_out_aw_bits_size (auto_axi4yank_out_aw_bits_size_0),
.auto_out_aw_bits_burst (auto_axi4yank_out_aw_bits_burst_0),
.auto_out_aw_bits_lock (auto_axi4yank_out_aw_bits_lock_0),
.auto_out_aw_bits_cache (auto_axi4yank_out_aw_bits_cache_0),
.auto_out_aw_bits_prot (auto_axi4yank_out_aw_bits_prot_0),
.auto_out_aw_bits_qos (auto_axi4yank_out_aw_bits_qos_0),
.auto_out_w_ready (auto_axi4yank_out_w_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_out_w_valid (auto_axi4yank_out_w_valid_0),
.auto_out_w_bits_data (auto_axi4yank_out_w_bits_data_0),
.auto_out_w_bits_strb (auto_axi4yank_out_w_bits_strb_0),
.auto_out_w_bits_last (auto_axi4yank_out_w_bits_last_0),
.auto_out_b_ready (auto_axi4yank_out_b_ready_0),
.auto_out_b_valid (auto_axi4yank_out_b_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_out_b_bits_id (auto_axi4yank_out_b_bits_id_0), // @[LazyModuleImp.scala:138:7]
.auto_out_b_bits_resp (auto_axi4yank_out_b_bits_resp_0), // @[LazyModuleImp.scala:138:7]
.auto_out_ar_ready (auto_axi4yank_out_ar_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_out_ar_valid (auto_axi4yank_out_ar_valid_0),
.auto_out_ar_bits_id (auto_axi4yank_out_ar_bits_id_0),
.auto_out_ar_bits_addr (auto_axi4yank_out_ar_bits_addr_0),
.auto_out_ar_bits_len (auto_axi4yank_out_ar_bits_len_0),
.auto_out_ar_bits_size (auto_axi4yank_out_ar_bits_size_0),
.auto_out_ar_bits_burst (auto_axi4yank_out_ar_bits_burst_0),
.auto_out_ar_bits_lock (auto_axi4yank_out_ar_bits_lock_0),
.auto_out_ar_bits_cache (auto_axi4yank_out_ar_bits_cache_0),
.auto_out_ar_bits_prot (auto_axi4yank_out_ar_bits_prot_0),
.auto_out_ar_bits_qos (auto_axi4yank_out_ar_bits_qos_0),
.auto_out_r_ready (auto_axi4yank_out_r_ready_0),
.auto_out_r_valid (auto_axi4yank_out_r_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_id (auto_axi4yank_out_r_bits_id_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_data (auto_axi4yank_out_r_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_resp (auto_axi4yank_out_r_bits_resp_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_last (auto_axi4yank_out_r_bits_last_0) // @[LazyModuleImp.scala:138:7]
); // @[UserYanker.scala:125:30]
AXI4IdIndexer_2 axi4index ( // @[IdIndexer.scala:108:31]
.clock (clock),
.reset (reset),
.auto_in_aw_ready (_axi4index_auto_in_aw_ready),
.auto_in_aw_valid (_tl2axi4_auto_out_aw_valid), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29]
.auto_in_w_ready (_axi4index_auto_in_w_ready),
.auto_in_w_valid (_tl2axi4_auto_out_w_valid), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_data (_tl2axi4_auto_out_w_bits_data), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_last (_tl2axi4_auto_out_w_bits_last), // @[ToAXI4.scala:301:29]
.auto_in_b_ready (_tl2axi4_auto_out_b_ready), // @[ToAXI4.scala:301:29]
.auto_in_b_valid (_axi4index_auto_in_b_valid),
.auto_in_b_bits_id (_axi4index_auto_in_b_bits_id),
.auto_in_b_bits_resp (_axi4index_auto_in_b_bits_resp),
.auto_in_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size),
.auto_in_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source),
.auto_in_ar_ready (_axi4index_auto_in_ar_ready),
.auto_in_ar_valid (_tl2axi4_auto_out_ar_valid), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29]
.auto_in_r_ready (_tl2axi4_auto_out_r_ready), // @[ToAXI4.scala:301:29]
.auto_in_r_valid (_axi4index_auto_in_r_valid),
.auto_in_r_bits_id (_axi4index_auto_in_r_bits_id),
.auto_in_r_bits_data (_axi4index_auto_in_r_bits_data),
.auto_in_r_bits_resp (_axi4index_auto_in_r_bits_resp),
.auto_in_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size),
.auto_in_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source),
.auto_in_r_bits_last (_axi4index_auto_in_r_bits_last),
.auto_out_aw_ready (_axi4yank_auto_in_aw_ready), // @[UserYanker.scala:125:30]
.auto_out_aw_valid (_axi4index_auto_out_aw_valid),
.auto_out_aw_bits_id (_axi4index_auto_out_aw_bits_id),
.auto_out_aw_bits_addr (_axi4index_auto_out_aw_bits_addr),
.auto_out_aw_bits_len (_axi4index_auto_out_aw_bits_len),
.auto_out_aw_bits_size (_axi4index_auto_out_aw_bits_size),
.auto_out_aw_bits_burst (_axi4index_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock (_axi4index_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache (_axi4index_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot (_axi4index_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos (_axi4index_auto_out_aw_bits_qos),
.auto_out_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size),
.auto_out_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source),
.auto_out_aw_bits_echo_extra_id (_axi4index_auto_out_aw_bits_echo_extra_id),
.auto_out_w_ready (_axi4yank_auto_in_w_ready), // @[UserYanker.scala:125:30]
.auto_out_w_valid (_axi4index_auto_out_w_valid),
.auto_out_w_bits_data (_axi4index_auto_out_w_bits_data),
.auto_out_w_bits_strb (_axi4index_auto_out_w_bits_strb),
.auto_out_w_bits_last (_axi4index_auto_out_w_bits_last),
.auto_out_b_ready (_axi4index_auto_out_b_ready),
.auto_out_b_valid (_axi4yank_auto_in_b_valid), // @[UserYanker.scala:125:30]
.auto_out_b_bits_id (_axi4yank_auto_in_b_bits_id), // @[UserYanker.scala:125:30]
.auto_out_b_bits_resp (_axi4yank_auto_in_b_bits_resp), // @[UserYanker.scala:125:30]
.auto_out_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size), // @[UserYanker.scala:125:30]
.auto_out_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source), // @[UserYanker.scala:125:30]
.auto_out_b_bits_echo_extra_id (_axi4yank_auto_in_b_bits_echo_extra_id), // @[UserYanker.scala:125:30]
.auto_out_ar_ready (_axi4yank_auto_in_ar_ready), // @[UserYanker.scala:125:30]
.auto_out_ar_valid (_axi4index_auto_out_ar_valid),
.auto_out_ar_bits_id (_axi4index_auto_out_ar_bits_id),
.auto_out_ar_bits_addr (_axi4index_auto_out_ar_bits_addr),
.auto_out_ar_bits_len (_axi4index_auto_out_ar_bits_len),
.auto_out_ar_bits_size (_axi4index_auto_out_ar_bits_size),
.auto_out_ar_bits_burst (_axi4index_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock (_axi4index_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache (_axi4index_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot (_axi4index_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos (_axi4index_auto_out_ar_bits_qos),
.auto_out_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size),
.auto_out_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source),
.auto_out_ar_bits_echo_extra_id (_axi4index_auto_out_ar_bits_echo_extra_id),
.auto_out_r_ready (_axi4index_auto_out_r_ready),
.auto_out_r_valid (_axi4yank_auto_in_r_valid), // @[UserYanker.scala:125:30]
.auto_out_r_bits_id (_axi4yank_auto_in_r_bits_id), // @[UserYanker.scala:125:30]
.auto_out_r_bits_data (_axi4yank_auto_in_r_bits_data), // @[UserYanker.scala:125:30]
.auto_out_r_bits_resp (_axi4yank_auto_in_r_bits_resp), // @[UserYanker.scala:125:30]
.auto_out_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size), // @[UserYanker.scala:125:30]
.auto_out_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source), // @[UserYanker.scala:125:30]
.auto_out_r_bits_echo_extra_id (_axi4yank_auto_in_r_bits_echo_extra_id), // @[UserYanker.scala:125:30]
.auto_out_r_bits_last (_axi4yank_auto_in_r_bits_last) // @[UserYanker.scala:125:30]
); // @[IdIndexer.scala:108:31]
TLToAXI4_2 tl2axi4 ( // @[ToAXI4.scala:301:29]
.clock (clock),
.reset (reset),
.auto_in_a_ready (widget_auto_anon_out_a_ready),
.auto_in_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_corrupt (widget_auto_anon_out_a_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_in_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9]
.auto_in_d_valid (widget_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (widget_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_size (widget_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (widget_auto_anon_out_d_bits_source),
.auto_in_d_bits_denied (widget_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (widget_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt),
.auto_out_aw_ready (_axi4index_auto_in_aw_ready), // @[IdIndexer.scala:108:31]
.auto_out_aw_valid (_tl2axi4_auto_out_aw_valid),
.auto_out_aw_bits_id (_tl2axi4_auto_out_aw_bits_id),
.auto_out_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr),
.auto_out_aw_bits_len (_tl2axi4_auto_out_aw_bits_len),
.auto_out_aw_bits_size (_tl2axi4_auto_out_aw_bits_size),
.auto_out_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos),
.auto_out_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size),
.auto_out_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source),
.auto_out_w_ready (_axi4index_auto_in_w_ready), // @[IdIndexer.scala:108:31]
.auto_out_w_valid (_tl2axi4_auto_out_w_valid),
.auto_out_w_bits_data (_tl2axi4_auto_out_w_bits_data),
.auto_out_w_bits_strb (_tl2axi4_auto_out_w_bits_strb),
.auto_out_w_bits_last (_tl2axi4_auto_out_w_bits_last),
.auto_out_b_ready (_tl2axi4_auto_out_b_ready),
.auto_out_b_valid (_axi4index_auto_in_b_valid), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_id (_axi4index_auto_in_b_bits_id), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_resp (_axi4index_auto_in_b_bits_resp), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_out_ar_ready (_axi4index_auto_in_ar_ready), // @[IdIndexer.scala:108:31]
.auto_out_ar_valid (_tl2axi4_auto_out_ar_valid),
.auto_out_ar_bits_id (_tl2axi4_auto_out_ar_bits_id),
.auto_out_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr),
.auto_out_ar_bits_len (_tl2axi4_auto_out_ar_bits_len),
.auto_out_ar_bits_size (_tl2axi4_auto_out_ar_bits_size),
.auto_out_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos),
.auto_out_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size),
.auto_out_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source),
.auto_out_r_ready (_tl2axi4_auto_out_r_ready),
.auto_out_r_valid (_axi4index_auto_in_r_valid), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_id (_axi4index_auto_in_r_bits_id), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_data (_axi4index_auto_in_r_bits_data), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_resp (_axi4index_auto_in_r_bits_resp), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_last (_axi4index_auto_in_r_bits_last) // @[IdIndexer.scala:108:31]
); // @[ToAXI4.scala:301:29]
assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_valid = auto_axi4yank_out_aw_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_id = auto_axi4yank_out_aw_bits_id_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_addr = auto_axi4yank_out_aw_bits_addr_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_len = auto_axi4yank_out_aw_bits_len_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_size = auto_axi4yank_out_aw_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_burst = auto_axi4yank_out_aw_bits_burst_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_lock = auto_axi4yank_out_aw_bits_lock_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_cache = auto_axi4yank_out_aw_bits_cache_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_prot = auto_axi4yank_out_aw_bits_prot_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_qos = auto_axi4yank_out_aw_bits_qos_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_valid = auto_axi4yank_out_w_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_bits_data = auto_axi4yank_out_w_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_bits_strb = auto_axi4yank_out_w_bits_strb_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_bits_last = auto_axi4yank_out_w_bits_last_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_b_ready = auto_axi4yank_out_b_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_valid = auto_axi4yank_out_ar_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_id = auto_axi4yank_out_ar_bits_id_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_addr = auto_axi4yank_out_ar_bits_addr_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_len = auto_axi4yank_out_ar_bits_len_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_size = auto_axi4yank_out_ar_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_burst = auto_axi4yank_out_ar_bits_burst_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_lock = auto_axi4yank_out_ar_bits_lock_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_cache = auto_axi4yank_out_ar_bits_cache_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_prot = auto_axi4yank_out_ar_bits_prot_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_qos = auto_axi4yank_out_ar_bits_qos_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_r_ready = auto_axi4yank_out_r_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_param = auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_source = auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_280( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_24 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File issue-unit-age-ordered.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util.{log2Ceil, PopCount}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import FUConstants._
import boom.v3.common._
/**
* Specific type of issue unit
*
* @param params issue queue params
* @param numWakeupPorts number of wakeup ports for the issue queue
*/
class IssueUnitCollapsing(
params: IssueParams,
numWakeupPorts: Int)
(implicit p: Parameters)
extends IssueUnit(params.numEntries, params.issueWidth, numWakeupPorts, params.iqType, params.dispatchWidth)
{
//-------------------------------------------------------------
// Figure out how much to shift entries by
val maxShift = dispatchWidth
val vacants = issue_slots.map(s => !(s.valid)) ++ io.dis_uops.map(_.valid).map(!_.asBool)
val shamts_oh = Array.fill(numIssueSlots+dispatchWidth) {Wire(UInt(width=maxShift.W))}
// track how many to shift up this entry by by counting previous vacant spots
def SaturatingCounterOH(count_oh:UInt, inc: Bool, max: Int): UInt = {
val next = Wire(UInt(width=max.W))
next := count_oh
when (count_oh === 0.U && inc) {
next := 1.U
} .elsewhen (!count_oh(max-1) && inc) {
next := (count_oh << 1.U)
}
next
}
shamts_oh(0) := 0.U
for (i <- 1 until numIssueSlots + dispatchWidth) {
shamts_oh(i) := SaturatingCounterOH(shamts_oh(i-1), vacants(i-1), maxShift)
}
//-------------------------------------------------------------
// which entries' uops will still be next cycle? (not being issued and vacated)
val will_be_valid = (0 until numIssueSlots).map(i => issue_slots(i).will_be_valid) ++
(0 until dispatchWidth).map(i => io.dis_uops(i).valid &&
!dis_uops(i).exception &&
!dis_uops(i).is_fence &&
!dis_uops(i).is_fencei)
val uops = issue_slots.map(s=>s.out_uop) ++ dis_uops.map(s=>s)
for (i <- 0 until numIssueSlots) {
issue_slots(i).in_uop.valid := false.B
issue_slots(i).in_uop.bits := uops(i+1)
for (j <- 1 to maxShift by 1) {
when (shamts_oh(i+j) === (1 << (j-1)).U) {
issue_slots(i).in_uop.valid := will_be_valid(i+j)
issue_slots(i).in_uop.bits := uops(i+j)
}
}
issue_slots(i).clear := shamts_oh(i) =/= 0.U
}
//-------------------------------------------------------------
// Dispatch/Entry Logic
// did we find a spot to slide the new dispatched uops into?
val will_be_available = (0 until numIssueSlots).map(i =>
(!issue_slots(i).will_be_valid || issue_slots(i).clear) && !(issue_slots(i).in_uop.valid))
val num_available = PopCount(will_be_available)
for (w <- 0 until dispatchWidth) {
io.dis_uops(w).ready := RegNext(num_available > w.U)
}
//-------------------------------------------------------------
// Issue Select Logic
// set default
for (w <- 0 until issueWidth) {
io.iss_valids(w) := false.B
io.iss_uops(w) := NullMicroOp
// unsure if this is overkill
io.iss_uops(w).prs1 := 0.U
io.iss_uops(w).prs2 := 0.U
io.iss_uops(w).prs3 := 0.U
io.iss_uops(w).lrs1_rtype := RT_X
io.iss_uops(w).lrs2_rtype := RT_X
}
val requests = issue_slots.map(s => s.request)
val port_issued = Array.fill(issueWidth){Bool()}
for (w <- 0 until issueWidth) {
port_issued(w) = false.B
}
for (i <- 0 until numIssueSlots) {
issue_slots(i).grant := false.B
var uop_issued = false.B
for (w <- 0 until issueWidth) {
val can_allocate = (issue_slots(i).uop.fu_code & io.fu_types(w)) =/= 0.U
when (requests(i) && !uop_issued && can_allocate && !port_issued(w)) {
issue_slots(i).grant := true.B
io.iss_valids(w) := true.B
io.iss_uops(w) := issue_slots(i).uop
}
val was_port_issued_yet = port_issued(w)
port_issued(w) = (requests(i) && !uop_issued && can_allocate) | port_issued(w)
uop_issued = (requests(i) && can_allocate && !was_port_issued_yet) | uop_issued
}
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-unit.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.{Str}
import boom.v3.common._
import boom.v3.exu.FUConstants._
import boom.v3.util.{BoolToChar}
/**
* Class used for configurations
*
* @param issueWidth amount of things that can be issued
* @param numEntries size of issue queue
* @param iqType type of issue queue
*/
case class IssueParams(
dispatchWidth: Int = 1,
issueWidth: Int = 1,
numEntries: Int = 8,
iqType: BigInt
)
/**
* Constants for knowing about the status of a MicroOp
*/
trait IssueUnitConstants
{
// invalid : slot holds no valid uop.
// s_valid_1: slot holds a valid uop.
// s_valid_2: slot holds a store-like uop that may be broken into two micro-ops.
val s_invalid :: s_valid_1 :: s_valid_2 :: Nil = Enum(3)
}
/**
* What physical register is broadcasting its wakeup?
* Is the physical register poisoned (aka, was it woken up by a speculative issue)?
*
* @param pregSz size of physical destination register
*/
class IqWakeup(val pregSz: Int) extends Bundle
{
val pdst = UInt(width=pregSz.W)
val poisoned = Bool()
}
/**
* IO bundle to interact with the issue unit
*
* @param issueWidth amount of operations that can be issued at once
* @param numWakeupPorts number of wakeup ports for issue unit
*/
class IssueUnitIO(
val issueWidth: Int,
val numWakeupPorts: Int,
val dispatchWidth: Int)
(implicit p: Parameters) extends BoomBundle
{
val dis_uops = Vec(dispatchWidth, Flipped(Decoupled(new MicroOp)))
val iss_valids = Output(Vec(issueWidth, Bool()))
val iss_uops = Output(Vec(issueWidth, new MicroOp()))
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
// tell the issue unit what each execution pipeline has in terms of functional units
val fu_types = Input(Vec(issueWidth, Bits(width=FUC_SZ.W)))
val brupdate = Input(new BrUpdateInfo())
val flush_pipeline = Input(Bool())
val ld_miss = Input(Bool())
val event_empty = Output(Bool()) // used by HPM events; is the issue unit empty?
val tsc_reg = Input(UInt(width=xLen.W))
}
/**
* Abstract top level issue unit
*
* @param numIssueSlots depth of issue queue
* @param issueWidth amoutn of operations that can be issued at once
* @param numWakeupPorts number of wakeup ports for issue unit
* @param iqType type of issue queue (mem, int, fp)
*/
abstract class IssueUnit(
val numIssueSlots: Int,
val issueWidth: Int,
val numWakeupPorts: Int,
val iqType: BigInt,
val dispatchWidth: Int)
(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueUnitIO(issueWidth, numWakeupPorts, dispatchWidth))
//-------------------------------------------------------------
// Set up the dispatch uops
// special case "storing" 2 uops within one issue slot.
val dis_uops = Array.fill(dispatchWidth) {Wire(new MicroOp())}
for (w <- 0 until dispatchWidth) {
dis_uops(w) := io.dis_uops(w).bits
dis_uops(w).iw_p1_poisoned := false.B
dis_uops(w).iw_p2_poisoned := false.B
dis_uops(w).iw_state := s_valid_1
if (iqType == IQT_MEM.litValue || iqType == IQT_INT.litValue) {
// For StoreAddrGen for Int, or AMOAddrGen, we go to addr gen state
when ((io.dis_uops(w).bits.uopc === uopSTA && io.dis_uops(w).bits.lrs2_rtype === RT_FIX) ||
io.dis_uops(w).bits.uopc === uopAMO_AG) {
dis_uops(w).iw_state := s_valid_2
// For store addr gen for FP, rs2 is the FP register, and we don't wait for that here
} .elsewhen (io.dis_uops(w).bits.uopc === uopSTA && io.dis_uops(w).bits.lrs2_rtype =/= RT_FIX) {
dis_uops(w).lrs2_rtype := RT_X
dis_uops(w).prs2_busy := false.B
}
dis_uops(w).prs3_busy := false.B
} else if (iqType == IQT_FP.litValue) {
// FP "StoreAddrGen" is really storeDataGen, and rs1 is the integer address register
when (io.dis_uops(w).bits.uopc === uopSTA) {
dis_uops(w).lrs1_rtype := RT_X
dis_uops(w).prs1_busy := false.B
}
}
if (iqType != IQT_INT.litValue) {
assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))
dis_uops(w).ppred_busy := false.B
}
}
//-------------------------------------------------------------
// Issue Table
val slots = for (i <- 0 until numIssueSlots) yield { val slot = Module(new IssueSlot(numWakeupPorts)); slot }
val issue_slots = VecInit(slots.map(_.io))
for (i <- 0 until numIssueSlots) {
issue_slots(i).wakeup_ports := io.wakeup_ports
issue_slots(i).pred_wakeup_port := io.pred_wakeup_port
issue_slots(i).spec_ld_wakeup := io.spec_ld_wakeup
issue_slots(i).ldspec_miss := io.ld_miss
issue_slots(i).brupdate := io.brupdate
issue_slots(i).kill := io.flush_pipeline
}
io.event_empty := !(issue_slots.map(s => s.valid).reduce(_|_))
val count = PopCount(slots.map(_.io.valid))
dontTouch(count)
//-------------------------------------------------------------
assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, "[issue] window giving out too many grants.")
//-------------------------------------------------------------
def getType: String =
if (iqType == IQT_INT.litValue) "int"
else if (iqType == IQT_MEM.litValue) "mem"
else if (iqType == IQT_FP.litValue) " fp"
else "unknown"
}
| module IssueUnitCollapsing_1( // @[issue-unit-age-ordered.scala:29:7]
input clock, // @[issue-unit-age-ordered.scala:29:7]
input reset, // @[issue-unit-age-ordered.scala:29:7]
output io_dis_uops_0_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_0_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_0_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_0_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_0_bits_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_dis_uops_1_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_1_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_1_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_1_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_1_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_1_bits_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_dis_uops_2_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_2_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_2_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_2_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_2_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_2_bits_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_iss_valids_0, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_uopc, // @[issue-unit.scala:112:14]
output [31:0] io_iss_uops_0_inst, // @[issue-unit.scala:112:14]
output [31:0] io_iss_uops_0_debug_inst, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_rvc, // @[issue-unit.scala:112:14]
output [39:0] io_iss_uops_0_debug_pc, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_iq_type, // @[issue-unit.scala:112:14]
output [9:0] io_iss_uops_0_fu_code, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_ctrl_br_type, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_ctrl_op1_sel, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_op2_sel, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_imm_sel, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ctrl_op_fcn, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_load, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_sta, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_std, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_iw_state, // @[issue-unit.scala:112:14]
output io_iss_uops_0_iw_p1_poisoned, // @[issue-unit.scala:112:14]
output io_iss_uops_0_iw_p2_poisoned, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_br, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_jalr, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_jal, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_sfb, // @[issue-unit.scala:112:14]
output [15:0] io_iss_uops_0_br_mask, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_br_tag, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ftq_idx, // @[issue-unit.scala:112:14]
output io_iss_uops_0_edge_inst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_pc_lob, // @[issue-unit.scala:112:14]
output io_iss_uops_0_taken, // @[issue-unit.scala:112:14]
output [19:0] io_iss_uops_0_imm_packed, // @[issue-unit.scala:112:14]
output [11:0] io_iss_uops_0_csr_addr, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_rob_idx, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ldq_idx, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_stq_idx, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_rxq_idx, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_pdst, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_prs1, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_prs2, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_prs3, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ppred, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs1_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs2_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs3_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ppred_busy, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_stale_pdst, // @[issue-unit.scala:112:14]
output io_iss_uops_0_exception, // @[issue-unit.scala:112:14]
output [63:0] io_iss_uops_0_exc_cause, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bypassable, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_mem_cmd, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_mem_size, // @[issue-unit.scala:112:14]
output io_iss_uops_0_mem_signed, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_fence, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_fencei, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_amo, // @[issue-unit.scala:112:14]
output io_iss_uops_0_uses_ldq, // @[issue-unit.scala:112:14]
output io_iss_uops_0_uses_stq, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_sys_pc2epc, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_unique, // @[issue-unit.scala:112:14]
output io_iss_uops_0_flush_on_commit, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ldst_is_rs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_ldst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs2, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs3, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ldst_val, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_dst_rtype, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_lrs1_rtype, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_lrs2_rtype, // @[issue-unit.scala:112:14]
output io_iss_uops_0_frs3_en, // @[issue-unit.scala:112:14]
output io_iss_uops_0_fp_val, // @[issue-unit.scala:112:14]
output io_iss_uops_0_fp_single, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_pf_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_ae_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_ma_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bp_debug_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bp_xcpt_if, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_debug_fsrc, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_debug_tsrc, // @[issue-unit.scala:112:14]
input io_wakeup_ports_0_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_1_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_2_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_3_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_4_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_5_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_6_valid, // @[issue-unit.scala:112:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-unit.scala:112:14]
input io_spec_ld_wakeup_0_valid, // @[issue-unit.scala:112:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-unit.scala:112:14]
input [9:0] io_fu_types_0, // @[issue-unit.scala:112:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:112:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:112:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_br, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_jal, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:112:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_taken, // @[issue-unit.scala:112:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_exception, // @[issue-unit.scala:112:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_fp_single, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:112:14]
input io_brupdate_b2_valid, // @[issue-unit.scala:112:14]
input io_brupdate_b2_mispredict, // @[issue-unit.scala:112:14]
input io_brupdate_b2_taken, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:112:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:112:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:112:14]
input io_flush_pipeline, // @[issue-unit.scala:112:14]
input io_ld_miss, // @[issue-unit.scala:112:14]
input [63:0] io_tsc_reg // @[issue-unit.scala:112:14]
);
wire _slots_15_io_valid; // @[issue-unit.scala:153:73]
wire _slots_14_io_valid; // @[issue-unit.scala:153:73]
wire _slots_13_io_valid; // @[issue-unit.scala:153:73]
wire _slots_12_io_valid; // @[issue-unit.scala:153:73]
wire _slots_11_io_valid; // @[issue-unit.scala:153:73]
wire _slots_10_io_valid; // @[issue-unit.scala:153:73]
wire _slots_9_io_valid; // @[issue-unit.scala:153:73]
wire _slots_8_io_valid; // @[issue-unit.scala:153:73]
wire _slots_7_io_valid; // @[issue-unit.scala:153:73]
wire _slots_6_io_valid; // @[issue-unit.scala:153:73]
wire _slots_5_io_valid; // @[issue-unit.scala:153:73]
wire _slots_4_io_valid; // @[issue-unit.scala:153:73]
wire _slots_3_io_valid; // @[issue-unit.scala:153:73]
wire _slots_2_io_valid; // @[issue-unit.scala:153:73]
wire _slots_1_io_valid; // @[issue-unit.scala:153:73]
wire _slots_0_io_valid; // @[issue-unit.scala:153:73]
wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_uopc_0 = io_dis_uops_0_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_iq_type_0 = io_dis_uops_0_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_0_bits_fu_code_0 = io_dis_uops_0_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_0_bits_ctrl_br_type_0 = io_dis_uops_0_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_ctrl_op1_sel_0 = io_dis_uops_0_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_op2_sel_0 = io_dis_uops_0_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_imm_sel_0 = io_dis_uops_0_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ctrl_op_fcn_0 = io_dis_uops_0_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_fcn_dw_0 = io_dis_uops_0_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_csr_cmd_0 = io_dis_uops_0_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_load_0 = io_dis_uops_0_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_sta_0 = io_dis_uops_0_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_std_0 = io_dis_uops_0_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_iw_state_0 = io_dis_uops_0_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_iw_p1_poisoned_0 = io_dis_uops_0_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_iw_p2_poisoned_0 = io_dis_uops_0_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_br_0 = io_dis_uops_0_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_jalr_0 = io_dis_uops_0_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_jal_0 = io_dis_uops_0_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_0_bits_csr_addr_0 = io_dis_uops_0_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bypassable_0 = io_dis_uops_0_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ldst_val_0 = io_dis_uops_0_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_fp_single_0 = io_dis_uops_0_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_uopc_0 = io_dis_uops_1_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_iq_type_0 = io_dis_uops_1_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_1_bits_fu_code_0 = io_dis_uops_1_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_1_bits_ctrl_br_type_0 = io_dis_uops_1_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_ctrl_op1_sel_0 = io_dis_uops_1_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_ctrl_op2_sel_0 = io_dis_uops_1_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_ctrl_imm_sel_0 = io_dis_uops_1_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ctrl_op_fcn_0 = io_dis_uops_1_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_fcn_dw_0 = io_dis_uops_1_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_1_bits_ctrl_csr_cmd_0 = io_dis_uops_1_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_is_load_0 = io_dis_uops_1_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_is_sta_0 = io_dis_uops_1_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ctrl_is_std_0 = io_dis_uops_1_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_iw_state_0 = io_dis_uops_1_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_iw_p1_poisoned_0 = io_dis_uops_1_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_iw_p2_poisoned_0 = io_dis_uops_1_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_br_0 = io_dis_uops_1_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_jalr_0 = io_dis_uops_1_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_jal_0 = io_dis_uops_1_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_1_bits_csr_addr_0 = io_dis_uops_1_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_bypassable_0 = io_dis_uops_1_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ldst_val_0 = io_dis_uops_1_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_fp_single_0 = io_dis_uops_1_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_uopc_0 = io_dis_uops_2_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_iq_type_0 = io_dis_uops_2_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_2_bits_fu_code_0 = io_dis_uops_2_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_2_bits_ctrl_br_type_0 = io_dis_uops_2_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_ctrl_op1_sel_0 = io_dis_uops_2_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_ctrl_op2_sel_0 = io_dis_uops_2_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_ctrl_imm_sel_0 = io_dis_uops_2_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ctrl_op_fcn_0 = io_dis_uops_2_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_fcn_dw_0 = io_dis_uops_2_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_2_bits_ctrl_csr_cmd_0 = io_dis_uops_2_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_is_load_0 = io_dis_uops_2_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_is_sta_0 = io_dis_uops_2_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ctrl_is_std_0 = io_dis_uops_2_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_iw_state_0 = io_dis_uops_2_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_iw_p1_poisoned_0 = io_dis_uops_2_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_iw_p2_poisoned_0 = io_dis_uops_2_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_br_0 = io_dis_uops_2_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_jalr_0 = io_dis_uops_2_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_jal_0 = io_dis_uops_2_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_2_bits_csr_addr_0 = io_dis_uops_2_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_bypassable_0 = io_dis_uops_2_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ldst_val_0 = io_dis_uops_2_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_fp_single_0 = io_dis_uops_2_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_fu_types_0_0 = io_fu_types_0; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:29:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:29:7]
wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:29:7]
wire io_ld_miss_0 = io_ld_miss; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire issue_slots_0_clear = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_prs3_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_prs3_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ppred_busy = 1'h0; // @[issue-unit.scala:154:28]
wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:76:49]
wire io_iss_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_dis_uops_0_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_1_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_2_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ppred = 5'h0; // @[issue-unit.scala:154:28]
wire [4:0] io_iss_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] io_iss_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] _next_T = 4'h0; // @[issue-unit-age-ordered.scala:48:26]
wire [3:0] io_iss_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] io_iss_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] io_iss_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] io_iss_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] io_iss_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] io_iss_uops_0_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] io_iss_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] io_iss_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] io_iss_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] io_iss_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_8_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_9_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_10_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_11_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_12_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_13_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_14_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_15_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire _io_event_empty_T_15; // @[issue-unit.scala:165:21]
wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_valids_0_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_uopc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_iss_uops_0_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_iss_uops_0_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_iss_uops_0_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_iq_type_0; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_iss_uops_0_fu_code_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_iw_state_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_iw_p1_poisoned_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_iw_p2_poisoned_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_br_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_jal_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7]
wire [15:0] io_iss_uops_0_br_mask_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_br_tag_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_taken_0; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_iss_uops_0_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_iss_uops_0_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_pdst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_prs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_prs2_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_prs3_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ppred_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_exception_0; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_iss_uops_0_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bypassable_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_mem_size_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_fence_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_amo_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_unique_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_ldst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs2_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs3_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_fp_val_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_fp_single_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_event_empty; // @[issue-unit-age-ordered.scala:29:7]
wire _T_5 = io_dis_uops_0_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39]
wire _T_4 = _T_5 & io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_0_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39]
wire [1:0] _WIRE_iw_state = _T_4 ? 2'h2 : 2'h1; // @[issue-unit.scala:123:26, :127:96, :128:54, :129:30]
wire _GEN = _T_4 | ~(_T_5 & (|io_dis_uops_0_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}]
wire [1:0] _WIRE_lrs2_rtype = _GEN ? io_dis_uops_0_bits_lrs2_rtype_0 : 2'h2; // @[issue-unit.scala:120:17, :128:54, :131:102]
wire _WIRE_prs2_busy = _GEN & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit.scala:120:17, :128:54, :131:102]
wire _T_18 = io_dis_uops_1_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39]
wire _T_17 = _T_18 & io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_1_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39]
wire _GEN_0 = _T_17 | ~(_T_18 & (|io_dis_uops_1_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}]
wire [1:0] _WIRE_1_lrs2_rtype = _GEN_0 ? io_dis_uops_1_bits_lrs2_rtype_0 : 2'h2; // @[issue-unit.scala:120:17, :128:54, :131:102]
wire _WIRE_1_prs2_busy = _GEN_0 & io_dis_uops_1_bits_prs2_busy_0; // @[issue-unit.scala:120:17, :128:54, :131:102]
wire _T_31 = io_dis_uops_2_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39]
wire _T_30 = _T_31 & io_dis_uops_2_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_2_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39]
wire _GEN_1 = _T_30 | ~(_T_31 & (|io_dis_uops_2_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}]
wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [3:0] issue_slots_0_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_0_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_valid; // @[issue-unit.scala:154:28]
wire issue_slots_0_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_0_request; // @[issue-unit.scala:154:28]
wire issue_slots_0_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_0_grant; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_1_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_valid; // @[issue-unit.scala:154:28]
wire issue_slots_1_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_1_request; // @[issue-unit.scala:154:28]
wire issue_slots_1_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_1_grant; // @[issue-unit.scala:154:28]
wire issue_slots_1_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_2_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_valid; // @[issue-unit.scala:154:28]
wire issue_slots_2_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_2_request; // @[issue-unit.scala:154:28]
wire issue_slots_2_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_2_grant; // @[issue-unit.scala:154:28]
wire issue_slots_2_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_3_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_valid; // @[issue-unit.scala:154:28]
wire issue_slots_3_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_3_request; // @[issue-unit.scala:154:28]
wire issue_slots_3_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_3_grant; // @[issue-unit.scala:154:28]
wire issue_slots_3_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_4_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_valid; // @[issue-unit.scala:154:28]
wire issue_slots_4_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_4_request; // @[issue-unit.scala:154:28]
wire issue_slots_4_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_4_grant; // @[issue-unit.scala:154:28]
wire issue_slots_4_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_5_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_valid; // @[issue-unit.scala:154:28]
wire issue_slots_5_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_5_request; // @[issue-unit.scala:154:28]
wire issue_slots_5_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_5_grant; // @[issue-unit.scala:154:28]
wire issue_slots_5_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_6_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_valid; // @[issue-unit.scala:154:28]
wire issue_slots_6_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_6_request; // @[issue-unit.scala:154:28]
wire issue_slots_6_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_6_grant; // @[issue-unit.scala:154:28]
wire issue_slots_6_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_7_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_valid; // @[issue-unit.scala:154:28]
wire issue_slots_7_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_7_request; // @[issue-unit.scala:154:28]
wire issue_slots_7_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_7_grant; // @[issue-unit.scala:154:28]
wire issue_slots_7_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_8_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_8_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_8_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_8_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_8_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_8_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_8_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_8_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_8_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_8_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_8_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_8_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_8_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_8_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_8_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_8_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_8_valid; // @[issue-unit.scala:154:28]
wire issue_slots_8_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_8_request; // @[issue-unit.scala:154:28]
wire issue_slots_8_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_8_grant; // @[issue-unit.scala:154:28]
wire issue_slots_8_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_9_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_9_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_9_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_9_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_9_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_9_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_9_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_9_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_9_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_9_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_9_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_9_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_9_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_9_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_9_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_9_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_9_valid; // @[issue-unit.scala:154:28]
wire issue_slots_9_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_9_request; // @[issue-unit.scala:154:28]
wire issue_slots_9_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_9_grant; // @[issue-unit.scala:154:28]
wire issue_slots_9_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_10_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_10_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_10_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_10_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_10_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_10_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_10_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_10_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_10_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_10_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_10_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_10_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_10_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_10_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_10_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_10_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_10_valid; // @[issue-unit.scala:154:28]
wire issue_slots_10_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_10_request; // @[issue-unit.scala:154:28]
wire issue_slots_10_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_10_grant; // @[issue-unit.scala:154:28]
wire issue_slots_10_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_11_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_11_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_11_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_11_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_11_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_11_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_11_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_11_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_11_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_11_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_11_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_11_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_11_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_11_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_11_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_11_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_11_valid; // @[issue-unit.scala:154:28]
wire issue_slots_11_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_11_request; // @[issue-unit.scala:154:28]
wire issue_slots_11_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_11_grant; // @[issue-unit.scala:154:28]
wire issue_slots_11_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_12_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_12_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_12_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_12_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_12_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_12_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_12_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_12_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_12_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_12_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_12_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_12_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_12_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_12_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_12_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_12_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_12_valid; // @[issue-unit.scala:154:28]
wire issue_slots_12_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_12_request; // @[issue-unit.scala:154:28]
wire issue_slots_12_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_12_grant; // @[issue-unit.scala:154:28]
wire issue_slots_12_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_13_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_13_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_13_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_13_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_13_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_13_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_13_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_13_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_13_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_13_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_13_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_13_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_13_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_13_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_13_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_13_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_13_valid; // @[issue-unit.scala:154:28]
wire issue_slots_13_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_13_request; // @[issue-unit.scala:154:28]
wire issue_slots_13_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_13_grant; // @[issue-unit.scala:154:28]
wire issue_slots_13_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_14_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_14_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_14_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_14_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_14_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_14_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_14_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_14_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_14_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_prs3; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_14_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_14_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_14_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_14_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_14_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_14_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_14_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_14_valid; // @[issue-unit.scala:154:28]
wire issue_slots_14_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_14_request; // @[issue-unit.scala:154:28]
wire issue_slots_14_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_14_grant; // @[issue-unit.scala:154:28]
wire issue_slots_14_clear; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_in_uop_bits_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_in_uop_bits_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_15_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_15_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_15_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_15_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_15_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [15:0] issue_slots_15_uop_br_mask; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_15_uop_br_tag; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_15_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_15_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_pdst; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_prs1; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_prs2; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_15_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_15_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_15_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_15_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_15_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_15_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_15_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_15_valid; // @[issue-unit.scala:154:28]
wire issue_slots_15_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_15_request; // @[issue-unit.scala:154:28]
wire issue_slots_15_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_15_grant; // @[issue-unit.scala:154:28]
wire issue_slots_15_clear; // @[issue-unit.scala:154:28]
wire _io_event_empty_T = issue_slots_0_valid | issue_slots_1_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_1 = _io_event_empty_T | issue_slots_2_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_2 = _io_event_empty_T_1 | issue_slots_3_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_3 = _io_event_empty_T_2 | issue_slots_4_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_4 = _io_event_empty_T_3 | issue_slots_5_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_5 = _io_event_empty_T_4 | issue_slots_6_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_6 = _io_event_empty_T_5 | issue_slots_7_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_7 = _io_event_empty_T_6 | issue_slots_8_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_8 = _io_event_empty_T_7 | issue_slots_9_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_9 = _io_event_empty_T_8 | issue_slots_10_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_10 = _io_event_empty_T_9 | issue_slots_11_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_11 = _io_event_empty_T_10 | issue_slots_12_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_12 = _io_event_empty_T_11 | issue_slots_13_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_13 = _io_event_empty_T_12 | issue_slots_14_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_14 = _io_event_empty_T_13 | issue_slots_15_valid; // @[issue-unit.scala:154:28, :165:61]
assign _io_event_empty_T_15 = ~_io_event_empty_T_14; // @[issue-unit.scala:165:{21,61}]
assign io_event_empty = _io_event_empty_T_15; // @[issue-unit.scala:165:21]
wire [1:0] _count_T = {1'h0, _slots_0_io_valid} + {1'h0, _slots_1_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_1 = _count_T; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_2 = {1'h0, _slots_2_io_valid} + {1'h0, _slots_3_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_3 = _count_T_2; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_4 = {1'h0, _count_T_1} + {1'h0, _count_T_3}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_5 = _count_T_4; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_6 = {1'h0, _slots_4_io_valid} + {1'h0, _slots_5_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_7 = _count_T_6; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_8 = {1'h0, _slots_6_io_valid} + {1'h0, _slots_7_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_9 = _count_T_8; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_10 = {1'h0, _count_T_7} + {1'h0, _count_T_9}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_11 = _count_T_10; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_12 = {1'h0, _count_T_5} + {1'h0, _count_T_11}; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_13 = _count_T_12; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_14 = {1'h0, _slots_8_io_valid} + {1'h0, _slots_9_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_15 = _count_T_14; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_16 = {1'h0, _slots_10_io_valid} + {1'h0, _slots_11_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_17 = _count_T_16; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_18 = {1'h0, _count_T_15} + {1'h0, _count_T_17}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_19 = _count_T_18; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_20 = {1'h0, _slots_12_io_valid} + {1'h0, _slots_13_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_21 = _count_T_20; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_22 = {1'h0, _slots_14_io_valid} + {1'h0, _slots_15_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_23 = _count_T_22; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_24 = {1'h0, _count_T_21} + {1'h0, _count_T_23}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_25 = _count_T_24; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_26 = {1'h0, _count_T_19} + {1'h0, _count_T_25}; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_27 = _count_T_26; // @[issue-unit.scala:167:23]
wire [4:0] _count_T_28 = {1'h0, _count_T_13} + {1'h0, _count_T_27}; // @[issue-unit.scala:167:23]
wire [4:0] count = _count_T_28; // @[issue-unit.scala:167:23] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_185( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_195 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_27( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_283 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Parameters.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy.{BufferParams}
import saturn.exu._
object VectorParams {
// minParams:
// For a very small area-efficient vector unit with iterative
// and element-wise functional units
def minParams = VectorParams()
// refParams
// For a standard modestly capable small vector unit with
// SIMD functional units
def refParams = minParams.copy(
vlrobEntries = 4,
vlissqEntries = 3,
vsissqEntries = 3,
vxissqEntries = 3,
vatSz = 5,
useSegmentedIMul = true,
doubleBufferSegments = true,
useScalarFPFMA = false,
vrfBanking = 4,
)
// dspParams
// For a wide high-performance vector unit with multi-issue
def dspParams = refParams.copy(
issStructure = VectorIssueStructure.Shared
)
// genParams:
// For a vector unit that performs better on less-optimized
// code sequences
def genParams = dspParams.copy(
issStructure = VectorIssueStructure.Split,
vlifqEntries = 16,
vlrobEntries = 16
)
// multiFMAParams:
// Provides a second sequencer and set of functional units for FMA operations
def multiFMAParams = genParams.copy(
issStructure = VectorIssueStructure.MultiFMA
)
// multiMACParams:
// Provides a second sequencer and set of functional units for integer MAC operations
def multiMACParams = genParams.copy(
issStructure = VectorIssueStructure.MultiMAC
)
// dmaParams:
// For a vector unit that only does memcpys, and no arithmetic
def dmaParams = VectorParams(
vdqEntries = 2,
vliqEntries = 4,
vsiqEntries = 4,
vlifqEntries = 32,
vlrobEntries = 4,
vsifqEntries = 32,
vlissqEntries = 2,
vsissqEntries = 1,
vrfBanking = 1,
useIterativeIMul = true
)
// The parameters below are approximations
// hwaParams
// For a vector unit with limited sequencer slots akin to Hwacha
def hwaParams = genParams.copy(
vatSz = 3, // 8 mseq Entries
vdqEntries = 1,
vlissqEntries = 8,
vsissqEntries = 8,
vxissqEntries = 8,
vpissqEntries = 8,
hwachaLimiter = Some(8), // sequencer slots
)
// lgvParams
// For a vector unit with very long vector lengths
def lgvParams = VectorParams(
vatSz = 5,
vlifqEntries = 32,
vsifqEntries = 32,
vlrobEntries = 32,
vlissqEntries = 8,
vsissqEntries = 8,
vxissqEntries = 8,
vpissqEntries = 8,
useSegmentedIMul = true,
useScalarFPMisc = false,
useScalarFPFMA = false,
vrfBanking = 4,
issStructure = VectorIssueStructure.Split
)
}
case class VXSequencerParams(
name: String,
fus: Seq[FunctionalUnitFactory]
) {
def insns = fus.map(_.insns).flatten
}
case class VXIssuePathParams(
name: String,
depth: Int,
seqs: Seq[VXSequencerParams]
) {
def insns = seqs.map(_.insns).flatten
}
object VXFunctionalUnitGroups {
def integerFUs(idivDoesImul: Boolean = false) = Seq(
IntegerPipeFactory,
ShiftPipeFactory,
BitwisePipeFactory,
IntegerDivideFactory(idivDoesImul),
MaskUnitFactory,
PermuteUnitFactory
)
def integerMAC(pipeDepth: Int, useSegmented: Boolean) = Seq(
IntegerMultiplyFactory(pipeDepth, useSegmented)
)
def allIntegerFUs(idivDoesImul: Boolean, imaDepth: Int, useSegmentedImul: Boolean) = (
integerFUs(idivDoesImul) ++ integerMAC(imaDepth, useSegmentedImul)
)
def sharedFPFMA(pipeDepth: Int) = Seq(
FPFMAFactory(pipeDepth, true)
)
def sharedFPMisc = Seq(
SharedFPMiscFactory
)
def fpFMA(pipeDepth: Int) = Seq(
FPFMAFactory(pipeDepth, false)
)
def fpMisc = Seq(
FPDivSqrtFactory,
FPCmpFactory,
FPConvFactory
)
def allFPFUs(fmaPipeDepth: Int, useScalarFPFMA: Boolean, useScalarFPMisc: Boolean) = (
(if (useScalarFPFMA) sharedFPFMA(fmaPipeDepth) else fpFMA(fmaPipeDepth)) ++
(if (useScalarFPMisc) sharedFPMisc else fpMisc)
)
}
sealed trait VectorIssueStructure {
def generate(params: VectorParams): Seq[VXIssuePathParams]
}
object VectorIssueStructure {
import VXFunctionalUnitGroups._
case object Unified extends VectorIssueStructure {
def generate(params: VectorParams) = {
val fp_int_path = VXIssuePathParams(
name = "fp_int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp_int", (
allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul) ++
allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)
))
)
)
Seq(fp_int_path)
}
}
case object Shared extends VectorIssueStructure {
def generate(params: VectorParams) = {
val fp_int_path = VXIssuePathParams(
name = "fp_int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(fp_int_path)
}
}
case object Split extends VectorIssueStructure {
def generate(params: VectorParams) = {
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(int_path, fp_path)
}
}
case object MultiFMA extends VectorIssueStructure {
def generate(params: VectorParams) = {
require(!params.useScalarFPFMA)
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp0", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)),
VXSequencerParams("fp1", fpFMA(params.fmaPipeDepth))
)
)
Seq(int_path, fp_path)
}
}
case object MultiMAC extends VectorIssueStructure {
def generate(params: VectorParams) = {
require(!params.useIterativeIMul && params.useSegmentedIMul)
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int0", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
VXSequencerParams("int1", integerMAC(params.imaPipeDepth, params.useSegmentedIMul))
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(int_path, fp_path)
}
}
}
case class VectorParams(
// In-order dispatch Queue
vdqEntries: Int = 4,
// Load store instruction queues (in VLSU)
vliqEntries: Int = 4,
vsiqEntries: Int = 4,
// Load store in-flight queues (in VLSU)
vlifqEntries: Int = 8,
vsifqEntries: Int = 16,
vlrobEntries: Int = 2,
// Scatter-gather engine params
vsgPorts: Int = 8,
vsgifqEntries: Int = 4,
vsgBuffers: Int = 3,
// Load/store/execute/permute/maskindex issue queues
vlissqEntries: Int = 0,
vsissqEntries: Int = 0,
vxissqEntries: Int = 0,
vpissqEntries: Int = 0,
dLen: Int = 64,
vatSz: Int = 3,
useSegmentedIMul: Boolean = false,
useScalarFPFMA: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions
useScalarFPMisc: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions
useIterativeIMul: Boolean = false,
fmaPipeDepth: Int = 4,
imaPipeDepth: Int = 3,
// for comparisons only
hazardingMultiplier: Int = 0,
hwachaLimiter: Option[Int] = None,
enableChaining: Boolean = true,
latencyInject: Boolean = false,
enableDAE: Boolean = true,
enableOOO: Boolean = true,
enableScalarVectorAddrDisambiguation: Boolean = true,
doubleBufferSegments: Boolean = false,
vrfBanking: Int = 2,
vrfHiccupBuffer: Boolean = true,
issStructure: VectorIssueStructure = VectorIssueStructure.Unified,
tlBuffer: BufferParams = BufferParams.default,
) {
def supported_ex_insns = issStructure.generate(this).map(_.insns).flatten
}
case object VectorParamsKey extends Field[VectorParams]
trait HasVectorParams extends HasVectorConsts { this: HasCoreParameters =>
implicit val p: Parameters
def vParams: VectorParams = p(VectorParamsKey)
def dLen = vParams.dLen
def dLenB = dLen / 8
def dLenOffBits = log2Ceil(dLenB)
def dmemTagBits = log2Ceil(vParams.vlifqEntries.max(vParams.vsifqEntries))
def sgmemTagBits = log2Ceil(vParams.vsgifqEntries)
def egsPerVReg = vLen / dLen
def egsTotal = (vLen / dLen) * 32
def vrfBankBits = log2Ceil(vParams.vrfBanking)
def lsiqIdBits = log2Ceil(vParams.vliqEntries.max(vParams.vsiqEntries))
val debugIdSz = 16
val nRelease = vParams.issStructure match {
case VectorIssueStructure.Unified => 3
case VectorIssueStructure.Shared | VectorIssueStructure.Split => 4
case VectorIssueStructure.MultiFMA | VectorIssueStructure.MultiMAC => 5
}
def getEgId(vreg: UInt, eidx: UInt, eew: UInt, bitwise: Bool): UInt = {
val base = vreg << log2Ceil(egsPerVReg)
val off = eidx >> Mux(bitwise, log2Ceil(dLen).U, (log2Ceil(dLenB).U - eew))
base +& off
}
def getByteId(vreg: UInt, eidx: UInt, eew: UInt): UInt = {
Cat(getEgId(vreg, eidx, eew, false.B), (eidx << eew)(log2Ceil(dLenB)-1,0))
}
def eewByteMask(eew: UInt) = (0 until (1+log2Ceil(eLen/8))).map { e =>
Mux(e.U === eew, ((1 << (1 << e)) - 1).U, 0.U)
}.reduce(_|_)((eLen/8)-1,0)
def eewBitMask(eew: UInt) = FillInterleaved(8, eewByteMask(eew))
def cqOlder(i0: UInt, i1: UInt, tail: UInt) = (i0 < i1) ^ (i0 < tail) ^ (i1 < tail)
def dLenSplat(in: UInt, eew: UInt) = {
val v = Wire(UInt(64.W))
v := in
Mux1H(UIntToOH(eew), (0 until 4).map { i => Fill(dLenB >> i, v((8<<i)-1,0)) })
}
def sextElem(in: UInt, in_eew: UInt): UInt = VecInit.tabulate(4)( { eew =>
Cat(in((8 << eew)-1), in((8 << eew)-1,0)).asSInt
})(in_eew)(64,0)
def extractElem(in: UInt, in_eew: UInt, eidx: UInt): UInt = {
val bytes = in.asTypeOf(Vec(dLenB, UInt(8.W)))
VecInit.tabulate(4) { eew =>
val elem = if (dLen == 64 && eew == 3) {
in
} else {
VecInit(bytes.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq)(eidx(log2Ceil(dLenB)-1-eew,0))
}
elem((8 << eew)-1,0)
}(in_eew)
}
def maxPosUInt(sew: Int) = Cat(0.U, ~(0.U(((8 << sew)-1).W)))
def minNegUInt(sew: Int) = Cat(1.U, 0.U(((8 << sew)-1).W))
def maxPosSInt(sew: Int) = ((1 << ((8 << sew)-1))-1).S
def minNegSInt(sew: Int) = (-1 << ((8 << sew)-1)).S
def maxPosFPUInt(sew: Int) = {
val expBits = Seq(4, 5, 8, 11)(sew)
val fracBits = (8 << sew) - expBits - 1
Cat(0.U, ~(0.U(expBits.W)), 0.U(fracBits.W))
}
def minNegFPUInt(sew: Int) = {
val expBits = Seq(4, 5, 8, 11)(sew)
val fracBits = (8 << sew) - expBits - 1
Cat(1.U, ~(0.U(expBits.W)), 0.U(fracBits.W))
}
def get_arch_mask(reg: UInt, emul: UInt) = VecInit.tabulate(4)({ lmul =>
FillInterleaved(1 << lmul, UIntToOH(reg >> lmul)((32>>lmul)-1,0))
})(emul)
def log2_up(f: UInt, max: Int) = VecInit.tabulate(max)({nf => log2Ceil(nf+1).U})(f)
def hazardMultiply(mask: UInt): UInt = if (vParams.hazardingMultiplier == 0) { mask } else {
require((1 << vParams.hazardingMultiplier) <= egsTotal)
VecInit(mask.asBools.grouped(1 << vParams.hazardingMultiplier).map { g =>
Fill(1 << vParams.hazardingMultiplier, g.orR)
}.toSeq).asUInt
}
}
File PipeSequencer.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile.{CoreModule}
import saturn.common._
abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val dis = Flipped(Decoupled(new BackendIssueInst))
val dis_stall = Input(Bool()) // used to disable OOO
val seq_hazard = Output(Valid(new SequencerHazard))
val vat = Output(UInt(vParams.vatSz.W))
val vat_head = Input(UInt(vParams.vatSz.W))
val older_writes = Input(UInt(egsTotal.W))
val older_reads = Input(UInt(egsTotal.W))
val busy = Output(Bool())
val head = Output(Bool())
val rvs1 = new VectorReadIO
val rvs2 = new VectorReadIO
val rvd = new VectorReadIO
val rvm = new VectorReadIO
val perm = new Bundle {
val req = Decoupled(new CompactorReq(dLenB))
val data = Input(UInt(dLen.W))
}
val iss = Decoupled(issType)
val acc = Input(Valid(new VectorWrite(dLen)))
})
def accepts(inst: VectorIssueInst): Bool
def min(a: UInt, b: UInt) = Mux(a > b, b, a)
def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0)
def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0)
def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0))
def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = {
val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W)
val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0)
val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0)
Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) })
}
def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = {
val next = Wire(UInt((1+log2Ceil(maxVLMax)).W))
next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask,
eidx +& dLen.U,
(((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen))
))
min(vl, next)
}
def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = {
val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew)
(next_eidx >> offset) =/= (eidx >> offset)
}
io.rvs1.req.valid := false.B
io.rvs1.req.bits := DontCare
io.rvs2.req.valid := false.B
io.rvs2.req.bits := DontCare
io.rvd.req.valid := false.B
io.rvd.req.bits := DontCare
io.rvm.req.valid := false.B
io.rvm.req.bits := DontCare
io.perm.req.valid := false.B
io.perm.req.bits := DontCare
}
File ExecuteSequencer.scala:
package saturn.backend
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
import saturn.insns._
class ExecuteSequencer(supported_insns: Seq[VectorInstruction])(implicit p: Parameters) extends PipeSequencer(new ExecuteMicroOp)(p) {
def accepts(inst: VectorIssueInst) = !inst.vmu && new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, supported_insns, Nil).matched
val valid = RegInit(false.B)
val inst = Reg(new BackendIssueInst)
val head = Reg(Bool())
val reduction_head = Reg(Bool())
val wvd_mask = Reg(UInt(egsTotal.W))
val rvs1_mask = Reg(UInt(egsTotal.W))
val rvs2_mask = Reg(UInt(egsTotal.W))
val rvd_mask = Reg(UInt(egsTotal.W))
val rvm_mask = Reg(UInt(egsPerVReg.W))
val slide = Reg(Bool())
val slide_up = Reg(Bool())
val slide1 = Reg(Bool())
val slide_offset = Reg(UInt((1+log2Ceil(maxVLMax)).W))
val perm_head = Reg(UInt(dLenOffBits.W))
val perm_tail = Reg(UInt(dLenOffBits.W))
val acc = Reg(Vec(dLenB, UInt(8.W)))
val acc_ready = Reg(Bool())
val acc_tail = Reg(Bool())
val acc_tail_id = Reg(UInt(log2Ceil(dLenB).W))
val ctrl = new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, supported_insns,
Seq(SetsWMask, UsesPermuteSeq, FPAdd, FPComp, Elementwise, UsesNarrowingSext, ZextImm5))
val mvnrr = inst.funct3 === OPIVI && inst.opif6 === OPIFunct6.mvnrr
val rgatherei16 = inst.funct3 === OPIVV && inst.opif6 === OPIFunct6.rgatherei16
val compress = inst.opmf6 === OPMFunct6.compress
val vs1_eew = Mux(rgatherei16, 1.U, inst.vconfig.vtype.vsew)
val vs2_eew = inst.vconfig.vtype.vsew + inst.wide_vs2 - Mux(ctrl.bool(UsesNarrowingSext), ~inst.rs1(2,1) + 1.U, 0.U)
val vs3_eew = inst.vconfig.vtype.vsew + inst.wide_vd
val vd_eew = inst.vconfig.vtype.vsew + inst.wide_vd
val incr_eew = Seq(
Mux(inst.renv1, vs1_eew, 0.U),
Mux(inst.renv2, vs2_eew, 0.U),
Mux(inst.renvd, vs3_eew, 0.U),
vd_eew).foldLeft(0.U(2.W)) { case (b, a) => Mux(a > b, a, b) }
val acc_elementwise_opcodes = (Seq(OPFFunct6.fredosum, OPFFunct6.fwredosum) ++
(if (vParams.useScalarFPMisc) Seq(OPFFunct6.fredmax, OPFFunct6.fredmin) else Nil) ++
(if (vParams.useScalarFPFMA) Seq(OPFFunct6.fredusum, OPFFunct6.fwredusum) else Nil)
)
val acc_copy = (vd_eew === 3.U && (dLenB == 8).B) || inst.opff6.isOneOf(acc_elementwise_opcodes)
val acc_last = acc_tail_id + 1.U === log2Ceil(dLenB).U - vd_eew || acc_copy
val uscalar = Mux(inst.funct3(2), inst.rs1_data, inst.imm5)
val sscalar = Mux(inst.funct3(2), inst.rs1_data, inst.imm5_sext)
val rgather = inst.opif6 === OPIFunct6.rgather
val rgather_ix = rgather && inst.funct3.isOneOf(OPIVX, OPIVI)
val rgather_v = rgather && inst.funct3.isOneOf(OPIVV)
val renv1 = Mux(inst.reduction, reduction_head, inst.renv1)
val renv2 = Mux(rgather_ix, head, Mux(inst.reduction, !reduction_head && !acc_tail, inst.renv2))
val renvd = inst.renvd
val renvm = inst.renvm
val renacc = inst.reduction
val use_wmask = !inst.vm && ctrl.bool(SetsWMask)
val eidx = Reg(UInt(log2Ceil(maxVLMax).W))
val eff_vl = Mux(mvnrr, ((vLen/8).U >> vd_eew) << inst.emul, Mux(inst.scalar_to_vd0, 1.U, inst.vconfig.vl))
val increments_as_mask = (!inst.renv1 || inst.reads_vs1_mask) && (!inst.renv2 || inst.reads_vs2_mask) && (!inst.wvd || inst.writes_mask)
val next_eidx = get_next_eidx(eff_vl, eidx, incr_eew, 0.U, increments_as_mask, ctrl.bool(Elementwise))
val eidx_tail = next_eidx === eff_vl
val tail = Mux(inst.reduction, acc_tail && acc_last, eidx_tail)
io.dis.ready := (!valid || (tail && io.iss.fire)) && !io.dis_stall
when (io.dis.fire) {
val dis_inst = io.dis.bits
valid := true.B
inst := io.dis.bits
assert(dis_inst.vstart === 0.U)
eidx := 0.U
val vd_arch_mask = get_arch_mask(dis_inst.rd , dis_inst.emul +& dis_inst.wide_vd)
val vs1_arch_mask = get_arch_mask(dis_inst.rs1, Mux(dis_inst.reads_vs1_mask, 0.U, dis_inst.emul))
val vs2_arch_mask = get_arch_mask(dis_inst.rs2, Mux(dis_inst.reads_vs2_mask, 0.U, dis_inst.emul +& dis_inst.wide_vs2))
wvd_mask := Mux(dis_inst.wvd , FillInterleaved(egsPerVReg, vd_arch_mask), 0.U)
rvs1_mask := Mux(dis_inst.renv1, FillInterleaved(egsPerVReg, vs1_arch_mask), 0.U)
rvs2_mask := Mux(dis_inst.renv2, FillInterleaved(egsPerVReg, vs2_arch_mask), 0.U)
rvd_mask := Mux(dis_inst.renvd, FillInterleaved(egsPerVReg, vd_arch_mask), 0.U)
rvm_mask := Mux(dis_inst.renvm, ~(0.U(egsPerVReg.W)), 0.U)
head := true.B
reduction_head := true.B
acc_tail := false.B
acc_tail_id := 0.U
acc_ready := true.B
val dis_slide = (dis_inst.funct6.isOneOf(OPIFunct6.slideup.litValue.U, OPIFunct6.slidedown.litValue.U)
&& dis_inst.funct3 =/= OPIVV)
val dis_slide_up = !dis_inst.funct6(0)
val dis_vl = dis_inst.vconfig.vl
val dis_sew = dis_inst.vconfig.vtype.vsew
val dis_vlmax = dis_inst.vconfig.vtype.vlMax
val dis_next_eidx = get_next_eidx(dis_vl, 0.U, dis_sew, 0.U, false.B, false.B)
val dis_slide1 = !dis_inst.isOpi
val dis_uscalar = Mux(dis_inst.funct3(2), dis_inst.rs1_data, dis_inst.imm5)
val dis_slide_offset = Mux(!dis_slide1, get_max_offset(dis_uscalar), 1.U)
val dis_tail = dis_next_eidx === dis_vl
val dis_rgather_eew = Mux(dis_inst.opif6 === OPIFunct6.rgatherei16, 1.U, dis_sew)
slide := dis_slide
when (dis_slide) {
slide_up := dis_slide_up
slide1 := dis_slide1
slide_offset := dis_slide_offset
}
perm_head := Mux(dis_slide && dis_slide_up,
(dis_slide_offset << dis_sew)(dLenOffBits-1,0),
0.U)
perm_tail := Mux(dis_slide,
Mux(dis_slide_up,
Mux(dis_tail, dis_vl << dis_sew, 0.U),
(Mux(dis_next_eidx + dis_slide_offset <= dis_vlmax, dis_next_eidx, dis_vlmax - dis_slide_offset) << dis_sew)(dLenOffBits-1,0)
),
1.U << dis_rgather_eew)
} .elsewhen (io.iss.fire) {
valid := !tail
head := false.B
}
when (io.acc.valid) {
acc_ready := true.B
for (i <- 0 until dLenB) when (io.acc.bits.mask(i*8)) { acc(i) := io.acc.bits.data >> (i*8) }
}
io.vat := inst.vat
io.seq_hazard.valid := valid
io.seq_hazard.bits.rintent := hazardMultiply(rvs1_mask | rvs2_mask | rvd_mask | rvm_mask)
io.seq_hazard.bits.wintent := hazardMultiply(wvd_mask)
io.seq_hazard.bits.vat := inst.vat
val vs1_read_oh = Mux(renv1 , UIntToOH(io.rvs1.req.bits.eg), 0.U)
val vs2_read_oh = Mux(renv2 , UIntToOH(io.rvs2.req.bits.eg), 0.U)
val vd_read_oh = Mux(renvd , UIntToOH(io.rvd.req.bits.eg ), 0.U)
val vm_read_oh = Mux(renvm , UIntToOH(io.rvm.req.bits.eg ), 0.U)
val vd_write_oh = Mux(inst.wvd, UIntToOH(io.iss.bits.wvd_eg), 0.U)
val raw_hazard = ((vs1_read_oh | vs2_read_oh | vd_read_oh | vm_read_oh) & io.older_writes) =/= 0.U
val waw_hazard = (vd_write_oh & io.older_writes) =/= 0.U
val war_hazard = (vd_write_oh & io.older_reads) =/= 0.U
val data_hazard = raw_hazard || waw_hazard || war_hazard
val acc_insns = supported_insns.filter(_.props.contains(Reduction.Y))
val acc_ctrl = new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, acc_insns, Seq(AccInitZeros, AccInitOnes, AccInitPos, AccInitNeg))
val acc_init_fp_pos = inst.opff6 === OPFFunct6.fredmin
val acc_init_fp_neg = inst.opff6 === OPFFunct6.fredmax
val acc_init = Mux1H(Seq(
(acc_ctrl.bool(AccInitZeros) , 0.U(dLen.W)),
(acc_ctrl.bool(AccInitOnes) , ~(0.U(dLen.W))),
(acc_ctrl.bool(AccInitPos) , VecInit.tabulate(4)({sew => Fill(dLenB >> sew, maxPosUInt(sew))})(vd_eew)),
(acc_ctrl.bool(AccInitNeg) , VecInit.tabulate(4)({sew => Fill(dLenB >> sew, minNegUInt(sew))})(vd_eew)),
(acc_init_fp_pos, VecInit.tabulate(4)({sew => Fill(dLenB >> sew, maxPosFPUInt(sew))})(vd_eew)),
(acc_init_fp_neg, VecInit.tabulate(4)({sew => Fill(dLenB >> sew, minNegFPUInt(sew))})(vd_eew)),
))
val rgather_eidx = get_max_offset(Mux(rgather_ix && rgather, uscalar, io.perm.data & eewBitMask(vs1_eew)))
val rgather_zero = rgather_eidx >= inst.vconfig.vtype.vlMax
val rvs2_eidx = Mux(rgather || rgatherei16, rgather_eidx, eidx)
io.rvs1.req.bits.eg := getEgId(inst.rs1, eidx , vs1_eew, inst.reads_vs1_mask)
io.rvs2.req.bits.eg := getEgId(inst.rs2, rvs2_eidx, vs2_eew, inst.reads_vs2_mask)
io.rvd.req.bits.eg := getEgId(inst.rd , eidx , vs3_eew, false.B)
io.rvm.req.bits.eg := getEgId(0.U , eidx , 0.U , true.B)
io.rvs1.req.valid := valid && renv1
io.rvs2.req.valid := valid && renv2
io.rvd.req.valid := valid && renvd
io.rvm.req.valid := valid && renvm
val oldest = inst.vat === io.vat_head
io.rvs1.req.bits.oldest := oldest
io.rvs2.req.bits.oldest := oldest
io.rvd.req.bits.oldest := oldest
io.rvm.req.bits.oldest := oldest
val read_perm_buffer = ctrl.bool(UsesPermuteSeq) && (!slide || Mux(slide_up,
next_eidx > slide_offset,
eidx +& slide_offset < inst.vconfig.vtype.vlMax))
io.perm.req.bits.head := perm_head
io.perm.req.bits.tail := perm_tail
val slide_down_byte_mask = Mux(slide && !slide_up && next_eidx + slide_offset > inst.vconfig.vtype.vlMax,
Mux(eidx +& slide_offset >= inst.vconfig.vtype.vlMax,
0.U,
~(0.U(dLenB.W)) >> (0.U(dLenOffBits.W) - ((inst.vconfig.vtype.vlMax - slide_offset) << vs2_eew))(dLenOffBits-1,0)),
~(0.U(dLenB.W)))
val slide_down_bit_mask = FillInterleaved(8, slide_down_byte_mask)
val iss_valid = (valid &&
!data_hazard &&
!(renv1 && !io.rvs1.req.ready) &&
!(renv2 && !io.rvs2.req.ready) &&
!(renvd && !io.rvd.req.ready) &&
!(renvm && !io.rvm.req.ready) &&
!(read_perm_buffer && !io.perm.req.ready) &&
!(renacc && !acc_ready)
)
io.perm.req.valid := iss_valid && read_perm_buffer && io.iss.ready
io.iss.valid := iss_valid && !(inst.reduction && reduction_head)
io.iss.bits.rvs1_data := io.rvs1.resp
io.iss.bits.rvs2_data := io.rvs2.resp
io.iss.bits.rvd_data := io.rvd.resp
io.iss.bits.rvs1_elem := extractElem(io.rvs1.resp, vs1_eew, eidx)
io.iss.bits.rvs2_elem := extractElem(io.rvs2.resp, vs2_eew, eidx)
io.iss.bits.rvd_elem := extractElem(io.rvd.resp , vs3_eew, eidx)
io.iss.bits.rvs1_eew := vs1_eew
io.iss.bits.rvs2_eew := vs2_eew
io.iss.bits.rvd_eew := vs3_eew
io.iss.bits.vd_eew := vd_eew
io.iss.bits.eidx := eidx
io.iss.bits.vl := inst.vconfig.vl
io.iss.bits.wvd_eg := getEgId(inst.rd, Mux(inst.reduction, 0.U, eidx), vd_eew, inst.writes_mask)
io.iss.bits.rs1 := inst.rs1
io.iss.bits.rs2 := inst.rs2
io.iss.bits.rd := inst.rd
io.iss.bits.funct3 := inst.funct3
io.iss.bits.funct6 := inst.funct6
io.iss.bits.tail := tail
io.iss.bits.head := head
io.iss.bits.acc := inst.reduction
io.iss.bits.vat := inst.vat
io.iss.bits.vm := inst.vm
io.iss.bits.rm := inst.rm
val dlen_mask = ~(0.U(dLenB.W))
val head_mask = dlen_mask << (eidx << vd_eew)(dLenOffBits-1,0)
val tail_mask = dlen_mask >> (0.U(dLenOffBits.W) - (next_eidx << vd_eew)(dLenOffBits-1,0))
val slide1up_mask = Mux(head && !inst.isOpi, eewByteMask(vs2_eew), 0.U)
val slideup_mask = Mux(slide && slide_up && eidx < slide_offset,
Mux(next_eidx <= slide_offset, 0.U, dlen_mask << (slide_offset << vd_eew)(dLenOffBits-1,0)) | slide1up_mask,
dlen_mask)
val full_tail_mask = Mux(tail,
~(0.U(dLen.W)) >> (0.U(log2Ceil(dLen).W) - eff_vl(log2Ceil(dLen)-1,0)),
~(0.U(dLen.W))
)
val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W)
val vm_eidx = (eidx & ~(vm_off >> vd_eew))(log2Ceil(dLen)-1,0)
val vm_resp = (io.rvm.resp >> vm_eidx)(dLenB-1,0)
val vm_mask = Mux(use_wmask,
VecInit.tabulate(4)({ sew => FillInterleaved(1 << sew, vm_resp)(dLenB-1,0) })(vd_eew),
~(0.U(dLenB.W))
)
val acc_mask = Mux(acc_last,
eewByteMask(vd_eew),
VecInit.tabulate(log2Ceil(dLenB))(i => ~(0.U((dLen>>i).W)))(acc_tail_id))
io.iss.bits.wmask := Mux(inst.reduction && acc_tail,
acc_mask,
head_mask & tail_mask & vm_mask & slideup_mask)
io.iss.bits.rmask := Mux(inst.vm, ~(0.U(dLenB.W)), vm_resp)
io.iss.bits.rvm_data := Mux(inst.vm, ~(0.U(dLen.W)), io.rvm.resp)
io.iss.bits.full_tail_mask := full_tail_mask
when (inst.funct3.isOneOf(OPIVI, OPIVX, OPMVX, OPFVF)) {
io.iss.bits.rvs1_elem := sscalar
io.iss.bits.rvs1_data := dLenSplat(Mux(ctrl.bool(ZextImm5), uscalar, sscalar), vs1_eew)
}
when (inst.reduction) {
val acc_bits = acc.asUInt
val elementwise_acc = inst.opff6.isOneOf(OPFFunct6.fredosum, OPFFunct6.fwredosum) || (
vParams.useScalarFPMisc.B && ctrl.bool(FPComp) && inst.isOpf
) || (
vParams.useScalarFPFMA.B && ctrl.bool(FPAdd) && inst.isOpf
)
when (elementwise_acc && !acc_tail) {
io.iss.bits.rvs2_data := io.iss.bits.rvs2_elem
val mask_bit = Mux(use_wmask, (io.rvm.resp >> eidx(log2Ceil(dLen)-1,0))(0), true.B)
io.iss.bits.wmask := VecInit.tabulate(4)({sew => Fill(1 << sew, mask_bit)})(vd_eew)
}
when (acc_tail) {
val folded = VecInit.tabulate(log2Ceil(dLenB))(i => {
val start = dLen >> (1 + i)
acc_bits(2*start-1,start)
})(acc_tail_id)
io.iss.bits.rvs1_elem := Mux(acc_copy, acc_init, folded)
io.iss.bits.rvs1_data := Mux(acc_copy, acc_init, folded)
io.iss.bits.rvs1_eew := vd_eew
io.iss.bits.rvs2_elem := acc_bits
io.iss.bits.rvs2_data := acc_bits
io.iss.bits.rvs2_eew := vd_eew
} .otherwise {
io.iss.bits.rvs1_elem := acc_bits
io.iss.bits.rvs1_data := acc_bits
io.iss.bits.rvs1_eew := vd_eew
}
}
when (rgather_v || rgatherei16) {
io.iss.bits.rvs1_elem := rgather_eidx
io.iss.bits.rvs1_data := rgather_eidx
}
when (rgather_zero && (rgather || rgatherei16)) {
io.iss.bits.rvs2_elem := 0.U
io.iss.bits.rvs2_data := 0.U
}
when (slide) {
io.iss.bits.rvs2_elem := io.perm.data & slide_down_bit_mask
io.iss.bits.rvs2_data := io.perm.data & slide_down_bit_mask
}
when (iss_valid && inst.reduction && reduction_head) {
val v0_mask = eewBitMask(vd_eew)
acc := ((acc_init & ~v0_mask.pad(dLen)) | (io.rvs1.resp & v0_mask)).asTypeOf(Vec(dLenB, UInt(8.W)))
reduction_head := false.B
}
when (io.iss.fire && !tail) {
when (next_is_new_eg(eidx, next_eidx, vd_eew, inst.writes_mask) && !inst.reduction && !compress && vParams.enableChaining.B) {
val wvd_clr_mask = UIntToOH(io.iss.bits.wvd_eg)
wvd_mask := wvd_mask & ~wvd_clr_mask
}
when (next_is_new_eg(eidx, next_eidx, vs2_eew, inst.reads_vs2_mask) && !(inst.reduction && head) && !rgather_v && !rgatherei16 && vParams.enableChaining.B) {
rvs2_mask := rvs2_mask & ~UIntToOH(io.rvs2.req.bits.eg)
}
when (rgather_ix && vParams.enableChaining.B) {
rvs2_mask := 0.U
}
when (next_is_new_eg(eidx, next_eidx, vs1_eew, inst.reads_vs1_mask) && vParams.enableChaining.B) {
rvs1_mask := rvs1_mask & ~UIntToOH(io.rvs1.req.bits.eg)
}
when (next_is_new_eg(eidx, next_eidx, vs3_eew, false.B) && vParams.enableChaining.B) {
rvd_mask := rvd_mask & ~UIntToOH(io.rvd.req.bits.eg)
}
when (next_is_new_eg(eidx, next_eidx, 0.U , true.B) && vParams.enableChaining.B) {
rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg)
}
acc_ready := false.B
when (eidx_tail) { acc_tail := true.B }
when (acc_tail) { acc_tail_id := acc_tail_id + 1.U }
eidx := next_eidx
when (ctrl.bool(UsesPermuteSeq) && slide) {
val next_next_eidx = get_next_eidx(eff_vl, next_eidx, incr_eew, 0.U, increments_as_mask, ctrl.bool(Elementwise))
val next_tail = next_next_eidx === eff_vl
perm_head := Mux(slide_up,
Mux(next_eidx < slide_offset, (slide_offset << vs2_eew)(dLenOffBits-1,0), 0.U),
next_eidx << vs2_eew)
perm_tail := Mux(slide_up,
Mux(next_tail, eff_vl << vs2_eew, 0.U),
(Mux(next_next_eidx + slide_offset <= inst.vconfig.vtype.vlMax, next_next_eidx, inst.vconfig.vtype.vlMax - slide_offset) << vs2_eew)(dLenOffBits-1,0))
}
}
io.busy := valid
io.head := head
}
| module ExecuteSequencer( // @[ExecuteSequencer.scala:13:7]
input clock, // @[ExecuteSequencer.scala:13:7]
input reset, // @[ExecuteSequencer.scala:13:7]
output io_dis_ready, // @[PipeSequencer.scala:11:14]
input io_dis_valid, // @[PipeSequencer.scala:11:14]
input [31:0] io_dis_bits_bits, // @[PipeSequencer.scala:11:14]
input [6:0] io_dis_bits_vconfig_vl, // @[PipeSequencer.scala:11:14]
input [2:0] io_dis_bits_vconfig_vtype_vsew, // @[PipeSequencer.scala:11:14]
input io_dis_bits_vconfig_vtype_vlmul_sign, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_vconfig_vtype_vlmul_mag, // @[PipeSequencer.scala:11:14]
input [5:0] io_dis_bits_vstart, // @[PipeSequencer.scala:11:14]
input [63:0] io_dis_bits_rs1_data, // @[PipeSequencer.scala:11:14]
input [2:0] io_dis_bits_vat, // @[PipeSequencer.scala:11:14]
input [2:0] io_dis_bits_rm, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_emul, // @[PipeSequencer.scala:11:14]
input io_dis_bits_reduction, // @[PipeSequencer.scala:11:14]
input io_dis_bits_scalar_to_vd0, // @[PipeSequencer.scala:11:14]
input io_dis_bits_wide_vd, // @[PipeSequencer.scala:11:14]
input io_dis_bits_wide_vs2, // @[PipeSequencer.scala:11:14]
input io_dis_bits_writes_mask, // @[PipeSequencer.scala:11:14]
input io_dis_bits_reads_vs1_mask, // @[PipeSequencer.scala:11:14]
input io_dis_bits_reads_vs2_mask, // @[PipeSequencer.scala:11:14]
input io_dis_bits_renv1, // @[PipeSequencer.scala:11:14]
input io_dis_bits_renv2, // @[PipeSequencer.scala:11:14]
input io_dis_bits_renvd, // @[PipeSequencer.scala:11:14]
input io_dis_bits_renvm, // @[PipeSequencer.scala:11:14]
input io_dis_bits_wvd, // @[PipeSequencer.scala:11:14]
output io_seq_hazard_valid, // @[PipeSequencer.scala:11:14]
output [2:0] io_seq_hazard_bits_vat, // @[PipeSequencer.scala:11:14]
output [31:0] io_seq_hazard_bits_rintent, // @[PipeSequencer.scala:11:14]
output [31:0] io_seq_hazard_bits_wintent, // @[PipeSequencer.scala:11:14]
output [2:0] io_vat, // @[PipeSequencer.scala:11:14]
input [2:0] io_vat_head, // @[PipeSequencer.scala:11:14]
input [31:0] io_older_writes, // @[PipeSequencer.scala:11:14]
input [31:0] io_older_reads, // @[PipeSequencer.scala:11:14]
output io_busy, // @[PipeSequencer.scala:11:14]
input io_rvs1_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvs1_req_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_rvs1_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvs1_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [63:0] io_rvs1_resp, // @[PipeSequencer.scala:11:14]
input io_rvs2_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvs2_req_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_rvs2_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvs2_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [63:0] io_rvs2_resp, // @[PipeSequencer.scala:11:14]
input io_rvd_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvd_req_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_rvd_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvd_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [63:0] io_rvd_resp, // @[PipeSequencer.scala:11:14]
input io_rvm_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvm_req_valid, // @[PipeSequencer.scala:11:14]
output io_rvm_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [63:0] io_rvm_resp, // @[PipeSequencer.scala:11:14]
input io_perm_req_ready, // @[PipeSequencer.scala:11:14]
output io_perm_req_valid, // @[PipeSequencer.scala:11:14]
output [2:0] io_perm_req_bits_head, // @[PipeSequencer.scala:11:14]
output [2:0] io_perm_req_bits_tail, // @[PipeSequencer.scala:11:14]
input [63:0] io_perm_data, // @[PipeSequencer.scala:11:14]
input io_iss_ready, // @[PipeSequencer.scala:11:14]
output io_iss_valid, // @[PipeSequencer.scala:11:14]
output [5:0] io_iss_bits_eidx, // @[PipeSequencer.scala:11:14]
output [6:0] io_iss_bits_vl, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_rvs1_data, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_rvs2_data, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_rvm_data, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_rvs1_elem, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_rvs2_elem, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_rvd_elem, // @[PipeSequencer.scala:11:14]
output [1:0] io_iss_bits_rvs1_eew, // @[PipeSequencer.scala:11:14]
output [1:0] io_iss_bits_rvs2_eew, // @[PipeSequencer.scala:11:14]
output [1:0] io_iss_bits_rvd_eew, // @[PipeSequencer.scala:11:14]
output [1:0] io_iss_bits_vd_eew, // @[PipeSequencer.scala:11:14]
output [7:0] io_iss_bits_rmask, // @[PipeSequencer.scala:11:14]
output [7:0] io_iss_bits_wmask, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_full_tail_mask, // @[PipeSequencer.scala:11:14]
output [4:0] io_iss_bits_wvd_eg, // @[PipeSequencer.scala:11:14]
output [2:0] io_iss_bits_funct3, // @[PipeSequencer.scala:11:14]
output [5:0] io_iss_bits_funct6, // @[PipeSequencer.scala:11:14]
output [4:0] io_iss_bits_rs1, // @[PipeSequencer.scala:11:14]
output [4:0] io_iss_bits_rs2, // @[PipeSequencer.scala:11:14]
output [4:0] io_iss_bits_rd, // @[PipeSequencer.scala:11:14]
output io_iss_bits_vm, // @[PipeSequencer.scala:11:14]
output io_iss_bits_head, // @[PipeSequencer.scala:11:14]
output io_iss_bits_tail, // @[PipeSequencer.scala:11:14]
output [2:0] io_iss_bits_vat, // @[PipeSequencer.scala:11:14]
output io_iss_bits_acc, // @[PipeSequencer.scala:11:14]
output [2:0] io_iss_bits_rm, // @[PipeSequencer.scala:11:14]
input io_acc_valid, // @[PipeSequencer.scala:11:14]
input [63:0] io_acc_bits_data, // @[PipeSequencer.scala:11:14]
input [63:0] io_acc_bits_mask // @[PipeSequencer.scala:11:14]
);
wire [63:0] io_iss_bits_rvs2_elem_0; // @[ExecuteSequencer.scala:306:51, :310:16, :311:27]
wire [4:0] _io_iss_bits_wvd_eg_T_2; // @[Parameters.scala:344:10]
wire io_iss_valid_0; // @[ExecuteSequencer.scala:211:29]
wire [4:0] _io_rvd_req_bits_eg_T_1; // @[Parameters.scala:344:10]
wire [4:0] _io_rvs2_req_bits_eg_T_1; // @[Parameters.scala:344:10]
wire [4:0] _io_rvs1_req_bits_eg_T_1; // @[Parameters.scala:344:10]
wire [3:0][63:0] _GEN = '{64'hFFFFFFFFFFFFFFFF, 64'hFFFF, 64'hFFFFFFFF, 64'hFFFFFFFFFFFFFFFF};
wire [3:0][63:0] _GEN_0 = '{64'hFFF0000000000000, 64'hFF800000FF800000, 64'hFC00FC00FC00FC00, 64'hF8F8F8F8F8F8F8F8};
wire [3:0][63:0] _GEN_1 = '{64'h7FF0000000000000, 64'h7F8000007F800000, 64'h7C007C007C007C00, 64'h7878787878787878};
wire [3:0][63:0] _GEN_2 = '{64'h8000000000000000, 64'h8000000080000000, 64'h8000800080008000, 64'h8080808080808080};
wire [3:0][63:0] _GEN_3 = '{64'h7FFFFFFFFFFFFFFF, 64'h7FFFFFFF7FFFFFFF, 64'h7FFF7FFF7FFF7FFF, 64'h7F7F7F7F7F7F7F7F};
reg valid; // @[ExecuteSequencer.scala:16:22]
reg [31:0] inst_bits; // @[ExecuteSequencer.scala:17:18]
reg [6:0] inst_vconfig_vl; // @[ExecuteSequencer.scala:17:18]
reg [2:0] inst_vconfig_vtype_vsew; // @[ExecuteSequencer.scala:17:18]
reg inst_vconfig_vtype_vlmul_sign; // @[ExecuteSequencer.scala:17:18]
reg [1:0] inst_vconfig_vtype_vlmul_mag; // @[ExecuteSequencer.scala:17:18]
reg [63:0] inst_rs1_data; // @[ExecuteSequencer.scala:17:18]
reg [2:0] inst_vat; // @[ExecuteSequencer.scala:17:18]
reg [2:0] inst_rm; // @[ExecuteSequencer.scala:17:18]
reg [1:0] inst_emul; // @[ExecuteSequencer.scala:17:18]
reg inst_reduction; // @[ExecuteSequencer.scala:17:18]
reg inst_scalar_to_vd0; // @[ExecuteSequencer.scala:17:18]
reg inst_wide_vd; // @[ExecuteSequencer.scala:17:18]
reg inst_wide_vs2; // @[ExecuteSequencer.scala:17:18]
reg inst_writes_mask; // @[ExecuteSequencer.scala:17:18]
reg inst_reads_vs1_mask; // @[ExecuteSequencer.scala:17:18]
reg inst_reads_vs2_mask; // @[ExecuteSequencer.scala:17:18]
reg inst_renv1; // @[ExecuteSequencer.scala:17:18]
reg inst_renv2; // @[ExecuteSequencer.scala:17:18]
reg inst_renvd; // @[ExecuteSequencer.scala:17:18]
reg inst_renvm; // @[ExecuteSequencer.scala:17:18]
reg inst_wvd; // @[ExecuteSequencer.scala:17:18]
reg head; // @[ExecuteSequencer.scala:18:18]
reg reduction_head; // @[ExecuteSequencer.scala:19:27]
reg [31:0] wvd_mask; // @[ExecuteSequencer.scala:20:22]
reg [31:0] rvs1_mask; // @[ExecuteSequencer.scala:21:22]
reg [31:0] rvs2_mask; // @[ExecuteSequencer.scala:22:22]
reg [31:0] rvd_mask; // @[ExecuteSequencer.scala:23:22]
reg rvm_mask; // @[ExecuteSequencer.scala:24:22]
reg slide; // @[ExecuteSequencer.scala:25:22]
reg slide_up; // @[ExecuteSequencer.scala:26:22]
reg [6:0] slide_offset; // @[ExecuteSequencer.scala:28:25]
reg [2:0] perm_head; // @[ExecuteSequencer.scala:29:22]
reg [2:0] perm_tail; // @[ExecuteSequencer.scala:30:22]
reg [7:0] acc_0; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_1; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_2; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_3; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_4; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_5; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_6; // @[ExecuteSequencer.scala:32:22]
reg [7:0] acc_7; // @[ExecuteSequencer.scala:32:22]
reg acc_ready; // @[ExecuteSequencer.scala:33:22]
reg acc_tail; // @[ExecuteSequencer.scala:34:22]
reg [2:0] acc_tail_id; // @[ExecuteSequencer.scala:35:24]
wire [17:0] decode_invInputs = ~{inst_bits[18:15], inst_bits[24:20], inst_bits[14:12], inst_bits[31:26]}; // @[pla.scala:78:21]
wire [5:0] _decode_andMatrixOutputs_T_18 = {inst_bits[28], inst_bits[29], decode_invInputs[4], decode_invInputs[5], decode_invInputs[6], decode_invInputs[8]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [4:0] _decode_andMatrixOutputs_T_27 = {inst_bits[27], inst_bits[28], decode_invInputs[3], inst_bits[31], decode_invInputs[7]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [3:0] _decode_andMatrixOutputs_T_37 = {inst_bits[27], decode_invInputs[2], inst_bits[12], decode_invInputs[7]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [4:0] _decode_andMatrixOutputs_T_38 = {inst_bits[28], decode_invInputs[3], decode_invInputs[4], decode_invInputs[5], inst_bits[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [4:0] _decode_andMatrixOutputs_T_42 = {inst_bits[28], inst_bits[29], inst_bits[31], inst_bits[12], decode_invInputs[7]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [4:0] _decode_andMatrixOutputs_T_43 = {decode_invInputs[3], inst_bits[30], inst_bits[31], inst_bits[12], decode_invInputs[7]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [10:0] _decode_orMatrixOutputs_T_5 = {&_decode_andMatrixOutputs_T_18, &_decode_andMatrixOutputs_T_27, &{inst_bits[29], inst_bits[30], inst_bits[31]}, &{decode_invInputs[1], decode_invInputs[4], inst_bits[12], decode_invInputs[7]}, &_decode_andMatrixOutputs_T_37, &_decode_andMatrixOutputs_T_38, &{inst_bits[29], inst_bits[30], inst_bits[12], decode_invInputs[7]}, &_decode_andMatrixOutputs_T_42, &_decode_andMatrixOutputs_T_43, &{inst_bits[26], decode_invInputs[3], inst_bits[30], decode_invInputs[5], decode_invInputs[6], inst_bits[13]}, &{decode_invInputs[4], inst_bits[31], decode_invInputs[6], inst_bits[13]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19]
wire [1:0] _decode_orMatrixOutputs_T_10 = {&_decode_andMatrixOutputs_T_18, &{inst_bits[27], inst_bits[28], inst_bits[29], decode_invInputs[4], decode_invInputs[5]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19]
wire [6:0] _mvnrr_WIRE = {1'h0, inst_bits[31:26]}; // @[Bundles.scala:75:20, :84:35]
wire rgatherei16 = ~(|(inst_bits[14:12])) & (~(|(inst_bits[14:12])) | inst_bits[14:12] == 3'h3 | inst_bits[14:12] == 3'h4 ? _mvnrr_WIRE : 7'h40) == 7'hE; // @[Bundles.scala:72:20, :84:{18,35}]
wire [2:0] vs1_eew = rgatherei16 ? 3'h1 : inst_vconfig_vtype_vsew; // @[ExecuteSequencer.scala:17:18, :41:43, :43:21]
wire [3:0] _GEN_4 = {1'h0, inst_vconfig_vtype_vsew}; // @[ExecuteSequencer.scala:17:18, :44:42]
wire [2:0] _vs2_eew_T_9 = inst_vconfig_vtype_vsew + {2'h0, inst_wide_vs2} - {1'h0, (&{decode_invInputs[0], inst_bits[27], decode_invInputs[3], inst_bits[30], decode_invInputs[5], inst_bits[13], decode_invInputs[17]}) ? ~(inst_bits[17:16]) + 2'h1 : 2'h0}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
wire [2:0] _vd_eew_T = inst_vconfig_vtype_vsew + {2'h0, inst_wide_vd}; // @[ExecuteSequencer.scala:17:18, :45:42]
wire [2:0] _incr_eew_T_1 = inst_renv2 ? _vs2_eew_T_9 : 3'h0; // @[ExecuteSequencer.scala:17:18, :44:58, :49:8]
wire [2:0] _incr_eew_T_2 = inst_renvd ? _vd_eew_T : 3'h0; // @[ExecuteSequencer.scala:17:18, :45:42, :50:8]
wire [2:0] _incr_eew_T_4 = (|(inst_renv1 ? vs1_eew : 3'h0)) & inst_renv1 ? vs1_eew : 3'h0; // @[ExecuteSequencer.scala:17:18, :43:21, :48:8, :51:{52,55}]
wire [2:0] _incr_eew_T_6 = _incr_eew_T_1 > _incr_eew_T_4 ? _incr_eew_T_1 : _incr_eew_T_4; // @[ExecuteSequencer.scala:48:8, :49:8, :51:{52,55}]
wire [2:0] _incr_eew_T_8 = _incr_eew_T_2 > _incr_eew_T_6 ? _incr_eew_T_2 : _incr_eew_T_6; // @[ExecuteSequencer.scala:50:8, :51:{52,55}]
wire _v0_mask_T_6 = _vd_eew_T == 3'h3; // @[ExecuteSequencer.scala:45:42, :56:26]
wire [6:0] _acc_copy_T_7 = inst_bits[14:12] == 3'h1 | inst_bits[14:12] == 3'h5 ? _mvnrr_WIRE : 7'h40; // @[Bundles.scala:72:20, :84:35, :85:18]
wire _acc_copy_T_8 = _acc_copy_T_7 == 7'h3; // @[Bundles.scala:85:18]
wire _acc_copy_T_9 = _acc_copy_T_7 == 7'h33; // @[Bundles.scala:85:18]
wire _acc_copy_T_10 = _acc_copy_T_7 == 7'h7; // @[Bundles.scala:85:18]
wire _acc_copy_T_11 = _acc_copy_T_7 == 7'h5; // @[Bundles.scala:85:18]
wire _acc_copy_T_12 = _acc_copy_T_7 == 7'h1; // @[Bundles.scala:85:18]
wire _acc_copy_T_13 = _acc_copy_T_7 == 7'h31; // @[Bundles.scala:85:18]
wire [2:0] _acc_tail_id_T = acc_tail_id + 3'h1; // @[ExecuteSequencer.scala:35:24, :57:30]
wire [2:0] _offset_T = 3'h3 - _vd_eew_T; // @[ExecuteSequencer.scala:45:42, :57:58]
wire [7:0] _GEN_5 = {_acc_tail_id_T == _offset_T, _v0_mask_T_6, _acc_copy_T_13, _acc_copy_T_12, _acc_copy_T_11, _acc_copy_T_10, _acc_copy_T_9, _acc_copy_T_8}; // @[ExecuteSequencer.scala:56:{26,53,74}, :57:{30,36,58,67}]
wire [63:0] uscalar = inst_bits[14] ? inst_rs1_data : {59'h0, inst_bits[19:15]}; // @[Bundles.scala:68:17, :72:20]
wire [63:0] sscalar = inst_bits[14] ? inst_rs1_data : {{59{inst_bits[19]}}, inst_bits[19:15]}; // @[Bundles.scala:68:17, :72:20, :74:{22,27,36}]
wire rgather = (~(|(inst_bits[14:12])) | inst_bits[14:12] == 3'h3 | inst_bits[14:12] == 3'h4 ? _mvnrr_WIRE : 7'h40) == 7'hC; // @[Bundles.scala:72:20, :84:{18,35}]
wire rgather_ix = rgather & (inst_bits[14:12] == 3'h4 | inst_bits[14:12] == 3'h3); // @[Bundles.scala:72:20]
wire rgather_v = rgather & ~(|(inst_bits[14:12])); // @[Bundles.scala:72:20]
wire renv1 = inst_reduction ? reduction_head : inst_renv1; // @[ExecuteSequencer.scala:17:18, :19:27, :63:21]
wire renv2 = rgather_ix ? head : inst_reduction ? ~reduction_head & ~acc_tail : inst_renv2; // @[ExecuteSequencer.scala:17:18, :18:18, :19:27, :34:22, :61:28, :64:{21,43,60,76,79}]
wire use_wmask = ~(inst_bits[25]) & (|{decode_invInputs[4], &{decode_invInputs[1], inst_bits[28]}, inst_bits[29], inst_bits[31], &{decode_invInputs[0], inst_bits[12], decode_invInputs[7]}, &_decode_andMatrixOutputs_T_37, &{decode_invInputs[6], inst_bits[13]}}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
reg [5:0] eidx; // @[ExecuteSequencer.scala:70:22]
wire [6:0] eff_vl = inst_bits[14:12] == 3'h3 & (~(|(inst_bits[14:12])) | inst_bits[14:12] == 3'h3 | inst_bits[14:12] == 3'h4 ? _mvnrr_WIRE : 7'h40) == 7'h27 ? {3'h0, 4'h8 >> _vd_eew_T} << inst_emul : inst_scalar_to_vd0 ? 7'h1 : inst_vconfig_vl; // @[Bundles.scala:72:20, :84:{18,35}]
wire increments_as_mask = (~inst_renv1 | inst_reads_vs1_mask) & (~inst_renv2 | inst_reads_vs2_mask) & (~inst_wvd | inst_writes_mask); // @[ExecuteSequencer.scala:17:18, :72:{29,41,65,69,81,105,109,119}]
wire [6:0] _GEN_6 = {1'h0, eidx}; // @[PipeSequencer.scala:52:35]
wire [2:0] _next_next_eidx_next_T_8 = 3'h3 - (_vd_eew_T > _incr_eew_T_8 ? _vd_eew_T : _incr_eew_T_8); // @[PipeSequencer.scala:54:33]
wire [13:0] _next_eidx_next_T_12 = {7'h0, {1'h0, eidx >> _next_next_eidx_next_T_8} + 7'h1} << _next_next_eidx_next_T_8; // @[PipeSequencer.scala:54:{15,33,52,60}]
wire [6:0] _next_eidx_next_T_14 = (|_decode_orMatrixOutputs_T_5) ? _GEN_6 + 7'h1 : increments_as_mask ? _GEN_6 - 7'h40 : _next_eidx_next_T_12[6:0]; // @[pla.scala:114:{19,36}]
wire [6:0] next_eidx = eff_vl > _next_eidx_next_T_14 ? _next_eidx_next_T_14 : eff_vl; // @[PipeSequencer.scala:40:{34,37}, :52:16]
wire eidx_tail = next_eidx == eff_vl; // @[PipeSequencer.scala:40:34]
wire tail = inst_reduction ? acc_tail & (|_GEN_5) : eidx_tail; // @[ExecuteSequencer.scala:17:18, :34:22, :56:{53,74}, :57:67, :74:29, :75:{22,48}]
wire _io_dis_ready_T_1 = io_iss_ready & io_iss_valid_0; // @[Decoupled.scala:51:35]
wire io_dis_ready_0 = ~valid | tail & _io_dis_ready_T_1; // @[Decoupled.scala:51:35]
wire _GEN_7 = io_dis_ready_0 & io_dis_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_122( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_206 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_112( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Error.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resources.SimpleDevice
import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions}
/** Adds a /dev/null slave that generates TL error response messages */
class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters)
extends DevNullDevice(params,
minLatency = if (buffer) 1 else 0,
beatBytes, new SimpleDevice("error-device", Seq("sifive,error0")))
{
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
import TLMessages._
import TLPermissions._
val (in, edge) = node.in(0)
val a = if (buffer) {Queue(in.a, 1)} else in.a
val da = Wire(chiselTypeOf(in.d))
val idle = RegInit(true.B)
val a_last = edge.last(a)
val (da_first, da_last, _) = edge.firstlast(da)
assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below
a.ready := (da.ready && da_last && idle) || !a_last
da.valid := a.valid && a_last && idle
da.bits.opcode := TLMessages.adResponse(a.bits.opcode)
da.bits.param := 0.U // toT, but error grants must be handled transiently (ie: you don't keep permissions)
da.bits.size := a.bits.size
da.bits.source := a.bits.source
da.bits.sink := 0.U
da.bits.denied := true.B
da.bits.data := 0.U
da.bits.corrupt := edge.hasData(da.bits)
if (params.acquire) {
val c = if (buffer) {Queue(in.c, 1)} else in.c
val dc = Wire(chiselTypeOf(in.d))
val c_last = edge.last(c)
val dc_last = edge.last(dc)
// Only allow one Grant in-flight at a time
when (da.fire && da.bits.opcode === Grant) { idle := false.B }
when (in.e.fire) { idle := true.B }
c.ready := (dc.ready && dc_last) || !c_last
dc.valid := c.valid && c_last
// ReleaseAck is not allowed to report failure
dc.bits.opcode := ReleaseAck
dc.bits.param := VecInit(toB, toN, toN)(c.bits.param(1,0))
dc.bits.size := c.bits.size
dc.bits.source := c.bits.source
dc.bits.sink := 0.U
dc.bits.denied := false.B
dc.bits.data := 0.U
dc.bits.corrupt := false.B
// Combine response channels
TLArbiter.lowest(edge, in.d, dc, da)
} else {
in.d <> da
}
// We never probe or issue B requests
in.b.valid := false.B
// Sink GrantAcks
in.e.ready := true.B
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLError( // @[Error.scala:21:9]
input clock, // @[Error.scala:21:9]
input reset, // @[Error.scala:21:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9]
wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9]
wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9]
wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17]
wire da_bits_denied = 1'h1; // @[Error.scala:28:18]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18]
wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire da_bits_sink = 1'h0; // @[Error.scala:28:18]
wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9]
wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18]
wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9]
wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[Error.scala:21:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9]
wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9]
wire [4:0] auto_in_d_bits_source_0; // @[Error.scala:21:9]
wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9]
wire auto_in_d_valid_0; // @[Error.scala:21:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9]
wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18]
wire da_valid; // @[Error.scala:28:18]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9]
wire [2:0] da_bits_opcode; // @[Error.scala:28:18]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9]
wire [3:0] da_bits_size; // @[Error.scala:28:18]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9]
wire [4:0] da_bits_source; // @[Error.scala:28:18]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9]
wire da_bits_corrupt; // @[Error.scala:28:18]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9]
wire _da_valid_T_1; // @[Error.scala:36:35]
assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18]
assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18]
assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18]
assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18]
wire da_bits_corrupt_opdata; // @[Edges.scala:106:36]
assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18]
wire _q_io_deq_ready_T_3; // @[Error.scala:35:46]
wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21]
wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21]
wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_last_counter; // @[Edges.scala:229:27]
wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_last = _a_last_last_T | _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36]
assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire da_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire r_3 = da_last & _T; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33]
wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}]
wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33]
assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 | _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}]
wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21]
assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}]
assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35]
assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21]
assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36]
always @(posedge clock) begin // @[Error.scala:21:9]
if (reset) begin // @[Error.scala:21:9]
a_last_counter <= 9'h0; // @[Edges.scala:229:27]
r_counter <= 9'h0; // @[Edges.scala:229:27]
end
else begin // @[Error.scala:21:9]
if (_a_last_T) // @[Decoupled.scala:51:35]
a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
end
always @(posedge)
TLMonitor_5 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue1_TLBundleA_a14d64s5k1z4u a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46]
.io_deq_valid (_a_q_io_deq_valid),
.io_deq_bits_opcode (_a_q_io_deq_bits_opcode),
.io_deq_bits_size (_a_q_io_deq_bits_size),
.io_deq_bits_source (da_bits_source)
); // @[Decoupled.scala:362:21]
assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_66( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
| module TLBFromNoC_1( // @[TilelinkAdapters.scala:145:7]
input clock, // @[TilelinkAdapters.scala:145:7]
input reset, // @[TilelinkAdapters.scala:145:7]
input io_protocol_ready, // @[TilelinkAdapters.scala:56:14]
output io_protocol_valid, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14]
output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14]
output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14]
output [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14]
output [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14]
output [15:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:56:14]
output [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14]
output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14]
input [144:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
reg [47:0] const_reg; // @[TilelinkAdapters.scala:69:22]
wire [47:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[47:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:145:7]
if (reset) // @[TilelinkAdapters.scala:145:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :145:7]
else // @[TilelinkAdapters.scala:145:7]
is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35]
if (_GEN_0) // @[TilelinkAdapters.scala:84:22]
const_reg <= io_flit_bits_payload[47:0]; // @[TilelinkAdapters.scala:56:14, :69:22]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_10( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_10 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_10 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_20 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_222( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_74( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_57 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_111 = _source_ok_T_110 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_115 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1445 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1445; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1445; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1513 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1513; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1513; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1513; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1378 = _T_1445 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1378 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1378 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1378 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1378 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1378 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1424 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1424 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1393 = _T_1513 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1393 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1393 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1393 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1489 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1489 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1471 = _T_1513 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1471 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1471 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1471 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_37 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_38 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_40 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module lo_us_19( // @[tage.scala:90:27]
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [7:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_0_ext hi_us_0_ext ( // @[tage.scala:90:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1), // @[tage.scala:90:27]
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:90:27]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncQueueSource_TLBundleD_a29d64s7k1z3u( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_opcode, // @[AsyncQueue.scala:73:14]
input [1:0] io_enq_bits_param, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_size, // @[AsyncQueue.scala:73:14]
input [6:0] io_enq_bits_source, // @[AsyncQueue.scala:73:14]
input io_enq_bits_sink, // @[AsyncQueue.scala:73:14]
input io_enq_bits_denied, // @[AsyncQueue.scala:73:14]
input [63:0] io_enq_bits_data, // @[AsyncQueue.scala:73:14]
input io_enq_bits_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_0_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_0_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_1_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_1_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_1_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_1_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_1_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_2_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_2_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_2_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_2_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_2_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_3_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_3_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_3_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_3_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_3_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_4_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_4_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_4_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_4_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_4_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_5_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_5_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_5_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_5_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_5_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_6_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_6_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_6_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_6_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_6_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:73:14]
output [1:0] io_async_mem_7_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_size, // @[AsyncQueue.scala:73:14]
output [6:0] io_async_mem_7_source, // @[AsyncQueue.scala:73:14]
output io_async_mem_7_sink, // @[AsyncQueue.scala:73:14]
output io_async_mem_7_denied, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_7_corrupt, // @[AsyncQueue.scala:73:14]
input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[AsyncQueue.scala:70:7]
wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[AsyncQueue.scala:70:7]
wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_sink_0 = io_enq_bits_sink; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[AsyncQueue.scala:70:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_0_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_0_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_0_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_1_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_1_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_1_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_1_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_1_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_1_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_2_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_2_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_2_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_2_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_2_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_2_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_3_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_3_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_3_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_3_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_3_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_3_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_4_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_4_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_4_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_4_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_4_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_4_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_5_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_5_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_5_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_5_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_5_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_5_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_6_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_6_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_6_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_6_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_6_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_6_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_opcode_0; // @[AsyncQueue.scala:70:7]
wire [1:0] io_async_mem_7_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_size_0; // @[AsyncQueue.scala:70:7]
wire [6:0] io_async_mem_7_source_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_7_sink_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_7_denied_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_7_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_7_corrupt_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg [2:0] mem_0_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_opcode_0 = mem_0_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_0_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_param_0 = mem_0_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_0_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_size_0 = mem_0_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_0_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_source_0 = mem_0_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_sink_0 = mem_0_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_denied_0 = mem_0_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_0_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_data_0 = mem_0_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_corrupt_0 = mem_0_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_opcode_0 = mem_1_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_1_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_param_0 = mem_1_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_size_0 = mem_1_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_1_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_source_0 = mem_1_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_1_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_sink_0 = mem_1_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_1_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_denied_0 = mem_1_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_1_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_data_0 = mem_1_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_1_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_corrupt_0 = mem_1_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_opcode_0 = mem_2_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_2_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_param_0 = mem_2_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_size_0 = mem_2_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_2_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_source_0 = mem_2_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_2_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_sink_0 = mem_2_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_2_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_denied_0 = mem_2_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_2_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_data_0 = mem_2_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_2_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_corrupt_0 = mem_2_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_opcode_0 = mem_3_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_3_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_param_0 = mem_3_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_size_0 = mem_3_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_3_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_source_0 = mem_3_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_3_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_sink_0 = mem_3_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_3_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_denied_0 = mem_3_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_3_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_data_0 = mem_3_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_3_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_corrupt_0 = mem_3_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_opcode_0 = mem_4_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_4_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_param_0 = mem_4_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_size_0 = mem_4_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_4_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_source_0 = mem_4_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_4_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_sink_0 = mem_4_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_4_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_denied_0 = mem_4_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_4_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_data_0 = mem_4_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_4_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_corrupt_0 = mem_4_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_opcode_0 = mem_5_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_5_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_param_0 = mem_5_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_size_0 = mem_5_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_5_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_source_0 = mem_5_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_5_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_sink_0 = mem_5_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_5_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_denied_0 = mem_5_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_5_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_data_0 = mem_5_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_5_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_corrupt_0 = mem_5_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_opcode_0 = mem_6_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_6_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_param_0 = mem_6_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_size_0 = mem_6_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_6_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_source_0 = mem_6_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_6_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_sink_0 = mem_6_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_6_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_denied_0 = mem_6_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_6_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_data_0 = mem_6_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_6_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_corrupt_0 = mem_6_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_opcode_0 = mem_7_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [1:0] mem_7_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_param_0 = mem_7_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_size_0 = mem_7_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [6:0] mem_7_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_source_0 = mem_7_source; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_7_sink; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_sink_0 = mem_7_sink; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_7_denied; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_denied_0 = mem_7_denied; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_7_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_data_0 = mem_7_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_7_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_corrupt_0 = mem_7_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] ridx; // @[ShiftReg.scala:48:24]
wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52]
wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1 & index == 3'h0) begin // @[Decoupled.scala:51:35]
mem_0_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h1) begin // @[Decoupled.scala:51:35]
mem_1_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h2) begin // @[Decoupled.scala:51:35]
mem_2_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h3) begin // @[Decoupled.scala:51:35]
mem_3_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h4) begin // @[Decoupled.scala:51:35]
mem_4_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h5) begin // @[Decoupled.scala:51:35]
mem_5_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h6) begin // @[Decoupled.scala:51:35]
mem_6_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & (&index)) begin // @[Decoupled.scala:51:35]
mem_7_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_sink <= io_enq_bits_sink_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_denied <= io_enq_bits_denied_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File SinkC.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class SinkCResponse(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val last = Bool()
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val source = UInt(params.inner.bundle.sourceBits.W)
val param = UInt(3.W)
val data = Bool()
}
class PutBufferCEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val data = UInt(params.inner.bundle.dataBits.W)
val corrupt = Bool()
}
class SinkC(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Decoupled(new FullRequest(params)) // Release
val resp = Valid(new SinkCResponse(params)) // ProbeAck
val c = Flipped(Decoupled(new TLBundleC(params.inner.bundle)))
// Find 'way' via MSHR CAM lookup
val set = UInt(params.setBits.W)
val way = Flipped(UInt(params.wayBits.W))
// ProbeAck write-back
val bs_adr = Decoupled(new BankedStoreInnerAddress(params))
val bs_dat = new BankedStoreInnerPoison(params)
// SourceD sideband
val rel_pop = Flipped(Decoupled(new PutBufferPop(params)))
val rel_beat = new PutBufferCEntry(params)
})
if (params.firstLevel) {
// Tie off unused ports
io.req.valid := false.B
io.req.bits := DontCare
io.resp.valid := false.B
io.resp.bits := DontCare
io.c.ready := true.B
io.set := 0.U
io.bs_adr.valid := false.B
io.bs_adr.bits := DontCare
io.bs_dat := DontCare
io.rel_pop.ready := true.B
io.rel_beat := DontCare
} else {
// No restrictions on the type of buffer
val c = params.micro.innerBuf.c(io.c)
val (tag, set, offset) = params.parseAddress(c.bits.address)
val (first, last, _, beat) = params.inner.count(c)
val hasData = params.inner.hasData(c.bits)
val raw_resp = c.bits.opcode === TLMessages.ProbeAck || c.bits.opcode === TLMessages.ProbeAckData
val resp = Mux(c.valid, raw_resp, RegEnable(raw_resp, c.valid))
// Handling of C is broken into two cases:
// ProbeAck
// if hasData, must be written to BankedStore
// if last beat, trigger resp
// Release
// if first beat, trigger req
// if hasData, go to putBuffer
// if hasData && first beat, must claim a list
assert (!(c.valid && c.bits.corrupt), "Data poisoning unavailable")
io.set := Mux(c.valid, set, RegEnable(set, c.valid)) // finds us the way
// Cut path from inner C to the BankedStore SRAM setup
// ... this makes it easier to layout the L2 data banks far away
val bs_adr = Wire(chiselTypeOf(io.bs_adr))
io.bs_adr <> Queue(bs_adr, 1, pipe=true)
io.bs_dat.data := RegEnable(c.bits.data, bs_adr.fire)
bs_adr.valid := resp && (!first || (c.valid && hasData))
bs_adr.bits.noop := !c.valid
bs_adr.bits.way := io.way
bs_adr.bits.set := io.set
bs_adr.bits.beat := Mux(c.valid, beat, RegEnable(beat + bs_adr.ready.asUInt, c.valid))
bs_adr.bits.mask := ~0.U(params.innerMaskBits.W)
params.ccover(bs_adr.valid && !bs_adr.ready, "SINKC_SRAM_STALL", "Data SRAM busy")
io.resp.valid := resp && c.valid && (first || last) && (!hasData || bs_adr.ready)
io.resp.bits.last := last
io.resp.bits.set := set
io.resp.bits.tag := tag
io.resp.bits.source := c.bits.source
io.resp.bits.param := c.bits.param
io.resp.bits.data := hasData
val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferCEntry(params), params.relLists, params.relBeats, false)))
val lists = RegInit(0.U(params.relLists.W))
val lists_set = WireInit(init = 0.U(params.relLists.W))
val lists_clr = WireInit(init = 0.U(params.relLists.W))
lists := (lists | lists_set) & ~lists_clr
val free = !lists.andR
val freeOH = ~(leftOR(~lists) << 1) & ~lists
val freeIdx = OHToUInt(freeOH)
val req_block = first && !io.req.ready
val buf_block = hasData && !putbuffer.io.push.ready
val set_block = hasData && first && !free
params.ccover(c.valid && !raw_resp && req_block, "SINKC_REQ_STALL", "No MSHR available to sink request")
params.ccover(c.valid && !raw_resp && buf_block, "SINKC_BUF_STALL", "No space in putbuffer for beat")
params.ccover(c.valid && !raw_resp && set_block, "SINKC_SET_STALL", "No space in putbuffer for request")
c.ready := Mux(raw_resp, !hasData || bs_adr.ready, !req_block && !buf_block && !set_block)
io.req.valid := !resp && c.valid && first && !buf_block && !set_block
putbuffer.io.push.valid := !resp && c.valid && hasData && !req_block && !set_block
when (!resp && c.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH }
val put = Mux(first, freeIdx, RegEnable(freeIdx, first))
io.req.bits.prio := VecInit(4.U(3.W).asBools)
io.req.bits.control:= false.B
io.req.bits.opcode := c.bits.opcode
io.req.bits.param := c.bits.param
io.req.bits.size := c.bits.size
io.req.bits.source := c.bits.source
io.req.bits.offset := offset
io.req.bits.set := set
io.req.bits.tag := tag
io.req.bits.put := put
putbuffer.io.push.bits.index := put
putbuffer.io.push.bits.data.data := c.bits.data
putbuffer.io.push.bits.data.corrupt := c.bits.corrupt
// Grant access to pop the data
putbuffer.io.pop.bits := io.rel_pop.bits.index
putbuffer.io.pop.valid := io.rel_pop.fire
io.rel_pop.ready := putbuffer.io.valid(io.rel_pop.bits.index(log2Ceil(params.relLists)-1,0))
io.rel_beat := putbuffer.io.data
when (io.rel_pop.fire && io.rel_pop.bits.last) {
lists_clr := UIntToOH(io.rel_pop.bits.index, params.relLists)
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module SinkC_3( // @[SinkC.scala:41:7]
input clock, // @[SinkC.scala:41:7]
input reset, // @[SinkC.scala:41:7]
input io_req_ready, // @[SinkC.scala:43:14]
output io_req_valid, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_param, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_size, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_source, // @[SinkC.scala:43:14]
output [8:0] io_req_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_put, // @[SinkC.scala:43:14]
output [10:0] io_req_bits_set, // @[SinkC.scala:43:14]
output io_resp_valid, // @[SinkC.scala:43:14]
output io_resp_bits_last, // @[SinkC.scala:43:14]
output [10:0] io_resp_bits_set, // @[SinkC.scala:43:14]
output [8:0] io_resp_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_resp_bits_source, // @[SinkC.scala:43:14]
output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14]
output io_resp_bits_data, // @[SinkC.scala:43:14]
output io_c_ready, // @[SinkC.scala:43:14]
input io_c_valid, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_param, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_size, // @[SinkC.scala:43:14]
input [5:0] io_c_bits_source, // @[SinkC.scala:43:14]
input [31:0] io_c_bits_address, // @[SinkC.scala:43:14]
input [127:0] io_c_bits_data, // @[SinkC.scala:43:14]
input io_c_bits_corrupt, // @[SinkC.scala:43:14]
output [10:0] io_set, // @[SinkC.scala:43:14]
input [3:0] io_way, // @[SinkC.scala:43:14]
input io_bs_adr_ready, // @[SinkC.scala:43:14]
output io_bs_adr_valid, // @[SinkC.scala:43:14]
output io_bs_adr_bits_noop, // @[SinkC.scala:43:14]
output [3:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14]
output [10:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14]
output [1:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14]
output [1:0] io_bs_adr_bits_mask, // @[SinkC.scala:43:14]
output [127:0] io_bs_dat_data, // @[SinkC.scala:43:14]
output io_rel_pop_ready, // @[SinkC.scala:43:14]
input io_rel_pop_valid, // @[SinkC.scala:43:14]
input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14]
input io_rel_pop_bits_last, // @[SinkC.scala:43:14]
output [127:0] io_rel_beat_data, // @[SinkC.scala:43:14]
output io_rel_beat_corrupt // @[SinkC.scala:43:14]
);
wire [10:0] io_set_0; // @[SinkC.scala:41:7]
wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27]
wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27]
wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [127:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7]
wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7]
wire [5:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7]
wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7]
wire [127:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7]
wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7]
wire [3:0] io_way_0 = io_way; // @[SinkC.scala:41:7]
wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7]
wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7]
wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7]
wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7]
wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7]
wire [1:0] bs_adr_bits_mask = 2'h3; // @[SinkC.scala:96:22]
wire [1:0] _bs_adr_bits_mask_T = 2'h3; // @[SinkC.scala:104:25]
wire _io_req_valid_T_6; // @[SinkC.scala:136:61]
wire [8:0] tag_1; // @[Parameters.scala:217:9]
wire [5:0] offset_1; // @[Parameters.scala:217:50]
wire [10:0] set_1; // @[Parameters.scala:217:28]
wire _io_resp_valid_T_5; // @[SinkC.scala:107:57]
wire last; // @[Edges.scala:232:33]
wire hasData; // @[Edges.scala:102:36]
wire [10:0] _io_set_T; // @[SinkC.scala:92:18]
wire [10:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22]
wire [3:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22]
wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43]
wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7]
wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7]
wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_source_0; // @[SinkC.scala:41:7]
wire [8:0] io_req_bits_tag_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7]
wire [10:0] io_req_bits_set_0; // @[SinkC.scala:41:7]
wire io_req_valid_0; // @[SinkC.scala:41:7]
wire io_resp_bits_last_0; // @[SinkC.scala:41:7]
wire [10:0] io_resp_bits_set_0; // @[SinkC.scala:41:7]
wire [8:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7]
wire [5:0] io_resp_bits_source_0; // @[SinkC.scala:41:7]
wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7]
wire io_resp_bits_data_0; // @[SinkC.scala:41:7]
wire io_resp_valid_0; // @[SinkC.scala:41:7]
wire io_c_ready_0; // @[SinkC.scala:41:7]
wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7]
wire [3:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7]
wire [10:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7]
wire [1:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7]
wire [1:0] io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7]
wire io_bs_adr_valid_0; // @[SinkC.scala:41:7]
wire [127:0] io_bs_dat_data_0; // @[SinkC.scala:41:7]
wire io_rel_pop_ready_0; // @[SinkC.scala:41:7]
wire [127:0] io_rel_beat_data_0; // @[SinkC.scala:41:7]
wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7]
wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21]
wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21]
wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21]
wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21]
wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21]
wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21]
wire _offset_T_6 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21]
wire _offset_T_7 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21]
wire _offset_T_8 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21]
wire _offset_T_9 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21]
wire _offset_T_10 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21]
wire _offset_T_11 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21]
wire _offset_T_12 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21]
wire _offset_T_13 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21]
wire _offset_T_14 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21]
wire _offset_T_15 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21]
wire _offset_T_16 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21]
wire _offset_T_17 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21]
wire _offset_T_18 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21]
wire _offset_T_19 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21]
wire _offset_T_20 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21]
wire _offset_T_21 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21]
wire _offset_T_22 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21]
wire _offset_T_23 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21]
wire _offset_T_24 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21]
wire _offset_T_25 = _c_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21]
wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_lo_hi_hi = {_offset_T_5, _offset_T_4}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, _offset_T_3}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_lo_hi_lo_hi = {_offset_T_8, _offset_T_7}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_6}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_lo = {_offset_T_10, _offset_T_9}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_hi = {_offset_T_12, _offset_T_11}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_lo_lo_hi = {_offset_T_15, _offset_T_14}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_13}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_lo_hi_hi = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, _offset_T_16}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_hi_lo_hi = {_offset_T_21, _offset_T_20}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_19}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_lo = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_hi = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21]
wire [25:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21]
wire [19:0] set = offset[25:6]; // @[Parameters.scala:214:21, :215:22]
wire [8:0] tag = set[19:11]; // @[Parameters.scala:215:22, :216:19]
assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9]
assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7]
assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7]
assign set_1 = set[10:0]; // @[Parameters.scala:215:22, :217:28]
assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7]
assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7]
assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50]
assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7]
wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19]
wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21]
wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] r_beats1_decode = _r_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
wire [1:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] r_counter; // @[Edges.scala:229:27]
wire [2:0] _r_counter1_T = {1'h0, r_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] r_counter1 = _r_counter1_T[1:0]; // @[Edges.scala:230:28]
wire first = r_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33]
wire r_3 = last & _T; // @[Decoupled.scala:51:35]
wire [1:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36]
wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21]
wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21]
wire raw_resp = _raw_resp_T | _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}]
reg resp_r; // @[SinkC.scala:79:48]
wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module IntSyncCrossingSource_n1x1_28( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9]
wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
AsyncResetRegVec_w1_i0_28 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset)
); // @[AsyncResetReg.scala:86:21]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module cc_banks_6_2( // @[DescribedSRAM.scala:17:26]
input [14:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_396( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_140 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_2( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_51 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_52 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_53 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_54 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_62( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
| module BranchKillableQueue_7( // @[util.scala:448:7]
input clock, // @[util.scala:448:7]
input reset, // @[util.scala:448:7]
output io_enq_ready, // @[util.scala:453:14]
input io_enq_valid, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:453:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_is_br, // @[util.scala:453:14]
input io_enq_bits_uop_is_jalr, // @[util.scala:453:14]
input io_enq_bits_uop_is_jal, // @[util.scala:453:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14]
input io_enq_bits_uop_taken, // @[util.scala:453:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14]
input io_enq_bits_uop_exception, // @[util.scala:453:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14]
input io_enq_bits_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:453:14]
input io_enq_bits_uop_is_fence, // @[util.scala:453:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:453:14]
input io_enq_bits_uop_is_amo, // @[util.scala:453:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:453:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_enq_bits_uop_is_unique, // @[util.scala:453:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:453:14]
input io_enq_bits_uop_fp_val, // @[util.scala:453:14]
input io_enq_bits_uop_fp_single, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14]
input [33:0] io_enq_bits_addr, // @[util.scala:453:14]
input [63:0] io_enq_bits_data, // @[util.scala:453:14]
input io_enq_bits_is_hella, // @[util.scala:453:14]
input io_enq_bits_tag_match, // @[util.scala:453:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:453:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14]
input io_deq_ready, // @[util.scala:453:14]
output io_deq_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:453:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [33:0] io_deq_bits_addr, // @[util.scala:453:14]
output [63:0] io_deq_bits_data, // @[util.scala:453:14]
output io_deq_bits_is_hella, // @[util.scala:453:14]
output io_deq_bits_tag_match, // @[util.scala:453:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14]
output io_empty // @[util.scala:453:14]
);
wire [3:0] out_uop_br_mask; // @[util.scala:506:17]
wire [130:0] _ram_ext_R0_data; // @[util.scala:464:20]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7]
wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7]
wire _valids_0_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_0_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_1_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_1_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_2_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_2_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_3_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_3_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_4_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_4_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_5_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_5_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_6_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_6_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_7_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_7_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_8_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_8_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_9_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_9_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_10_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_10_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_11_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_11_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_12_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_12_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_13_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_13_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_14_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_14_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_15_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_15_T_5 = 1'h1; // @[util.scala:481:72]
wire _io_deq_valid_T_4 = 1'h1; // @[util.scala:509:68]
wire _io_deq_valid_T_7 = 1'h1; // @[util.scala:509:111]
wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_15_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _io_deq_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[util.scala:448:7, :453:14]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:448:7, :453:14]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:448:7, :453:14]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_valid = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:448:7]
wire io_flush = 1'h0; // @[util.scala:448:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32]
wire _valids_0_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_0_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_1_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_1_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_2_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_2_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_3_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_3_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_4_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_4_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_5_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_5_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_6_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_6_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_7_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_7_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_8_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_8_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_9_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_9_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_10_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_10_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_11_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_11_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_12_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_12_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_13_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_13_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_14_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_14_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_15_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_15_T_4 = 1'h0; // @[util.scala:481:83]
wire _io_deq_valid_T_3 = 1'h0; // @[util.scala:118:59]
wire _io_deq_valid_T_6 = 1'h0; // @[util.scala:509:122]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:448:7]
wire [3:0] _valids_0_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_1_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_2_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_3_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_4_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_5_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_6_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_7_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_8_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_9_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_10_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_11_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_12_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_13_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_14_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_15_T = 4'h0; // @[util.scala:118:51]
wire _io_enq_ready_T; // @[util.scala:504:19]
wire [3:0] _io_deq_valid_T_2 = 4'h0; // @[util.scala:118:51]
wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:85:25, :448:7]
wire _io_deq_valid_T_8; // @[util.scala:509:108]
wire [6:0] out_uop_uopc; // @[util.scala:506:17]
wire [31:0] out_uop_inst; // @[util.scala:506:17]
wire [31:0] out_uop_debug_inst; // @[util.scala:506:17]
wire out_uop_is_rvc; // @[util.scala:506:17]
wire [33:0] out_uop_debug_pc; // @[util.scala:506:17]
wire [2:0] out_uop_iq_type; // @[util.scala:506:17]
wire [9:0] out_uop_fu_code; // @[util.scala:506:17]
wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17]
wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17]
wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17]
wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17]
wire out_uop_ctrl_is_load; // @[util.scala:506:17]
wire out_uop_ctrl_is_sta; // @[util.scala:506:17]
wire out_uop_ctrl_is_std; // @[util.scala:506:17]
wire [1:0] out_uop_iw_state; // @[util.scala:506:17]
wire out_uop_iw_p1_poisoned; // @[util.scala:506:17]
wire out_uop_iw_p2_poisoned; // @[util.scala:506:17]
wire out_uop_is_br; // @[util.scala:506:17]
wire out_uop_is_jalr; // @[util.scala:506:17]
wire out_uop_is_jal; // @[util.scala:506:17]
wire out_uop_is_sfb; // @[util.scala:506:17]
wire [3:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [1:0] out_uop_br_tag; // @[util.scala:506:17]
wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17]
wire out_uop_edge_inst; // @[util.scala:506:17]
wire [5:0] out_uop_pc_lob; // @[util.scala:506:17]
wire out_uop_taken; // @[util.scala:506:17]
wire [19:0] out_uop_imm_packed; // @[util.scala:506:17]
wire [11:0] out_uop_csr_addr; // @[util.scala:506:17]
wire [5:0] out_uop_rob_idx; // @[util.scala:506:17]
wire [3:0] out_uop_ldq_idx; // @[util.scala:506:17]
wire [3:0] out_uop_stq_idx; // @[util.scala:506:17]
wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17]
wire [6:0] out_uop_pdst; // @[util.scala:506:17]
wire [6:0] out_uop_prs1; // @[util.scala:506:17]
wire [6:0] out_uop_prs2; // @[util.scala:506:17]
wire [6:0] out_uop_prs3; // @[util.scala:506:17]
wire [3:0] out_uop_ppred; // @[util.scala:506:17]
wire out_uop_prs1_busy; // @[util.scala:506:17]
wire out_uop_prs2_busy; // @[util.scala:506:17]
wire out_uop_prs3_busy; // @[util.scala:506:17]
wire out_uop_ppred_busy; // @[util.scala:506:17]
wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17]
wire out_uop_exception; // @[util.scala:506:17]
wire [63:0] out_uop_exc_cause; // @[util.scala:506:17]
wire out_uop_bypassable; // @[util.scala:506:17]
wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17]
wire [1:0] out_uop_mem_size; // @[util.scala:506:17]
wire out_uop_mem_signed; // @[util.scala:506:17]
wire out_uop_is_fence; // @[util.scala:506:17]
wire out_uop_is_fencei; // @[util.scala:506:17]
wire out_uop_is_amo; // @[util.scala:506:17]
wire out_uop_uses_ldq; // @[util.scala:506:17]
wire out_uop_uses_stq; // @[util.scala:506:17]
wire out_uop_is_sys_pc2epc; // @[util.scala:506:17]
wire out_uop_is_unique; // @[util.scala:506:17]
wire out_uop_flush_on_commit; // @[util.scala:506:17]
wire out_uop_ldst_is_rs1; // @[util.scala:506:17]
wire [5:0] out_uop_ldst; // @[util.scala:506:17]
wire [5:0] out_uop_lrs1; // @[util.scala:506:17]
wire [5:0] out_uop_lrs2; // @[util.scala:506:17]
wire [5:0] out_uop_lrs3; // @[util.scala:506:17]
wire out_uop_ldst_val; // @[util.scala:506:17]
wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17]
wire out_uop_frs3_en; // @[util.scala:506:17]
wire out_uop_fp_val; // @[util.scala:506:17]
wire out_uop_fp_single; // @[util.scala:506:17]
wire out_uop_xcpt_pf_if; // @[util.scala:506:17]
wire out_uop_xcpt_ae_if; // @[util.scala:506:17]
wire out_uop_xcpt_ma_if; // @[util.scala:506:17]
wire out_uop_bp_debug_if; // @[util.scala:506:17]
wire out_uop_bp_xcpt_if; // @[util.scala:506:17]
wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17]
wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17]
wire [33:0] out_addr; // @[util.scala:506:17]
wire [63:0] out_data; // @[util.scala:506:17]
wire out_is_hella; // @[util.scala:506:17]
wire out_tag_match; // @[util.scala:506:17]
wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17]
wire [21:0] out_old_meta_tag; // @[util.scala:506:17]
wire [1:0] out_way_en; // @[util.scala:506:17]
wire [4:0] out_sdq_id; // @[util.scala:506:17]
wire _io_empty_T_1; // @[util.scala:473:25]
wire io_enq_ready_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7]
wire io_deq_bits_is_hella_0; // @[util.scala:448:7]
wire io_deq_bits_tag_match_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7]
wire io_deq_valid_0; // @[util.scala:448:7]
wire io_empty_0; // @[util.scala:448:7]
wire [3:0] io_count; // @[util.scala:448:7]
assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:464:20, :506:17]
assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:464:20, :506:17]
assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:464:20, :506:17]
assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:464:20, :506:17]
assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:464:20, :506:17]
assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:464:20, :506:17]
assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:464:20, :506:17]
assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:464:20, :506:17]
reg valids_0; // @[util.scala:465:24]
wire _valids_0_T_3 = valids_0; // @[util.scala:465:24, :481:29]
reg valids_1; // @[util.scala:465:24]
wire _valids_1_T_3 = valids_1; // @[util.scala:465:24, :481:29]
reg valids_2; // @[util.scala:465:24]
wire _valids_2_T_3 = valids_2; // @[util.scala:465:24, :481:29]
reg valids_3; // @[util.scala:465:24]
wire _valids_3_T_3 = valids_3; // @[util.scala:465:24, :481:29]
reg valids_4; // @[util.scala:465:24]
wire _valids_4_T_3 = valids_4; // @[util.scala:465:24, :481:29]
reg valids_5; // @[util.scala:465:24]
wire _valids_5_T_3 = valids_5; // @[util.scala:465:24, :481:29]
reg valids_6; // @[util.scala:465:24]
wire _valids_6_T_3 = valids_6; // @[util.scala:465:24, :481:29]
reg valids_7; // @[util.scala:465:24]
wire _valids_7_T_3 = valids_7; // @[util.scala:465:24, :481:29]
reg valids_8; // @[util.scala:465:24]
wire _valids_8_T_3 = valids_8; // @[util.scala:465:24, :481:29]
reg valids_9; // @[util.scala:465:24]
wire _valids_9_T_3 = valids_9; // @[util.scala:465:24, :481:29]
reg valids_10; // @[util.scala:465:24]
wire _valids_10_T_3 = valids_10; // @[util.scala:465:24, :481:29]
reg valids_11; // @[util.scala:465:24]
wire _valids_11_T_3 = valids_11; // @[util.scala:465:24, :481:29]
reg valids_12; // @[util.scala:465:24]
wire _valids_12_T_3 = valids_12; // @[util.scala:465:24, :481:29]
reg valids_13; // @[util.scala:465:24]
wire _valids_13_T_3 = valids_13; // @[util.scala:465:24, :481:29]
reg valids_14; // @[util.scala:465:24]
wire _valids_14_T_3 = valids_14; // @[util.scala:465:24, :481:29]
reg valids_15; // @[util.scala:465:24]
wire _valids_15_T_3 = valids_15; // @[util.scala:465:24, :481:29]
reg [6:0] uops_0_uopc; // @[util.scala:466:20]
reg [31:0] uops_0_inst; // @[util.scala:466:20]
reg [31:0] uops_0_debug_inst; // @[util.scala:466:20]
reg uops_0_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_0_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_0_iq_type; // @[util.scala:466:20]
reg [9:0] uops_0_fu_code; // @[util.scala:466:20]
reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_0_ctrl_is_load; // @[util.scala:466:20]
reg uops_0_ctrl_is_sta; // @[util.scala:466:20]
reg uops_0_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_0_iw_state; // @[util.scala:466:20]
reg uops_0_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_0_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_0_is_br; // @[util.scala:466:20]
reg uops_0_is_jalr; // @[util.scala:466:20]
reg uops_0_is_jal; // @[util.scala:466:20]
reg uops_0_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_0_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_0_br_tag; // @[util.scala:466:20]
reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20]
reg uops_0_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_0_pc_lob; // @[util.scala:466:20]
reg uops_0_taken; // @[util.scala:466:20]
reg [19:0] uops_0_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_0_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_0_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_0_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_0_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_0_pdst; // @[util.scala:466:20]
reg [6:0] uops_0_prs1; // @[util.scala:466:20]
reg [6:0] uops_0_prs2; // @[util.scala:466:20]
reg [6:0] uops_0_prs3; // @[util.scala:466:20]
reg [3:0] uops_0_ppred; // @[util.scala:466:20]
reg uops_0_prs1_busy; // @[util.scala:466:20]
reg uops_0_prs2_busy; // @[util.scala:466:20]
reg uops_0_prs3_busy; // @[util.scala:466:20]
reg uops_0_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20]
reg uops_0_exception; // @[util.scala:466:20]
reg [63:0] uops_0_exc_cause; // @[util.scala:466:20]
reg uops_0_bypassable; // @[util.scala:466:20]
reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_0_mem_size; // @[util.scala:466:20]
reg uops_0_mem_signed; // @[util.scala:466:20]
reg uops_0_is_fence; // @[util.scala:466:20]
reg uops_0_is_fencei; // @[util.scala:466:20]
reg uops_0_is_amo; // @[util.scala:466:20]
reg uops_0_uses_ldq; // @[util.scala:466:20]
reg uops_0_uses_stq; // @[util.scala:466:20]
reg uops_0_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_0_is_unique; // @[util.scala:466:20]
reg uops_0_flush_on_commit; // @[util.scala:466:20]
reg uops_0_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_0_ldst; // @[util.scala:466:20]
reg [5:0] uops_0_lrs1; // @[util.scala:466:20]
reg [5:0] uops_0_lrs2; // @[util.scala:466:20]
reg [5:0] uops_0_lrs3; // @[util.scala:466:20]
reg uops_0_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20]
reg uops_0_frs3_en; // @[util.scala:466:20]
reg uops_0_fp_val; // @[util.scala:466:20]
reg uops_0_fp_single; // @[util.scala:466:20]
reg uops_0_xcpt_pf_if; // @[util.scala:466:20]
reg uops_0_xcpt_ae_if; // @[util.scala:466:20]
reg uops_0_xcpt_ma_if; // @[util.scala:466:20]
reg uops_0_bp_debug_if; // @[util.scala:466:20]
reg uops_0_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_1_uopc; // @[util.scala:466:20]
reg [31:0] uops_1_inst; // @[util.scala:466:20]
reg [31:0] uops_1_debug_inst; // @[util.scala:466:20]
reg uops_1_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_1_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_1_iq_type; // @[util.scala:466:20]
reg [9:0] uops_1_fu_code; // @[util.scala:466:20]
reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_1_ctrl_is_load; // @[util.scala:466:20]
reg uops_1_ctrl_is_sta; // @[util.scala:466:20]
reg uops_1_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_1_iw_state; // @[util.scala:466:20]
reg uops_1_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_1_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_1_is_br; // @[util.scala:466:20]
reg uops_1_is_jalr; // @[util.scala:466:20]
reg uops_1_is_jal; // @[util.scala:466:20]
reg uops_1_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_1_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_1_br_tag; // @[util.scala:466:20]
reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20]
reg uops_1_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_1_pc_lob; // @[util.scala:466:20]
reg uops_1_taken; // @[util.scala:466:20]
reg [19:0] uops_1_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_1_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_1_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_1_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_1_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_1_pdst; // @[util.scala:466:20]
reg [6:0] uops_1_prs1; // @[util.scala:466:20]
reg [6:0] uops_1_prs2; // @[util.scala:466:20]
reg [6:0] uops_1_prs3; // @[util.scala:466:20]
reg [3:0] uops_1_ppred; // @[util.scala:466:20]
reg uops_1_prs1_busy; // @[util.scala:466:20]
reg uops_1_prs2_busy; // @[util.scala:466:20]
reg uops_1_prs3_busy; // @[util.scala:466:20]
reg uops_1_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20]
reg uops_1_exception; // @[util.scala:466:20]
reg [63:0] uops_1_exc_cause; // @[util.scala:466:20]
reg uops_1_bypassable; // @[util.scala:466:20]
reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_1_mem_size; // @[util.scala:466:20]
reg uops_1_mem_signed; // @[util.scala:466:20]
reg uops_1_is_fence; // @[util.scala:466:20]
reg uops_1_is_fencei; // @[util.scala:466:20]
reg uops_1_is_amo; // @[util.scala:466:20]
reg uops_1_uses_ldq; // @[util.scala:466:20]
reg uops_1_uses_stq; // @[util.scala:466:20]
reg uops_1_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_1_is_unique; // @[util.scala:466:20]
reg uops_1_flush_on_commit; // @[util.scala:466:20]
reg uops_1_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_1_ldst; // @[util.scala:466:20]
reg [5:0] uops_1_lrs1; // @[util.scala:466:20]
reg [5:0] uops_1_lrs2; // @[util.scala:466:20]
reg [5:0] uops_1_lrs3; // @[util.scala:466:20]
reg uops_1_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20]
reg uops_1_frs3_en; // @[util.scala:466:20]
reg uops_1_fp_val; // @[util.scala:466:20]
reg uops_1_fp_single; // @[util.scala:466:20]
reg uops_1_xcpt_pf_if; // @[util.scala:466:20]
reg uops_1_xcpt_ae_if; // @[util.scala:466:20]
reg uops_1_xcpt_ma_if; // @[util.scala:466:20]
reg uops_1_bp_debug_if; // @[util.scala:466:20]
reg uops_1_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_2_uopc; // @[util.scala:466:20]
reg [31:0] uops_2_inst; // @[util.scala:466:20]
reg [31:0] uops_2_debug_inst; // @[util.scala:466:20]
reg uops_2_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_2_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_2_iq_type; // @[util.scala:466:20]
reg [9:0] uops_2_fu_code; // @[util.scala:466:20]
reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_2_ctrl_is_load; // @[util.scala:466:20]
reg uops_2_ctrl_is_sta; // @[util.scala:466:20]
reg uops_2_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_2_iw_state; // @[util.scala:466:20]
reg uops_2_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_2_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_2_is_br; // @[util.scala:466:20]
reg uops_2_is_jalr; // @[util.scala:466:20]
reg uops_2_is_jal; // @[util.scala:466:20]
reg uops_2_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_2_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_2_br_tag; // @[util.scala:466:20]
reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20]
reg uops_2_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_2_pc_lob; // @[util.scala:466:20]
reg uops_2_taken; // @[util.scala:466:20]
reg [19:0] uops_2_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_2_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_2_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_2_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_2_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_2_pdst; // @[util.scala:466:20]
reg [6:0] uops_2_prs1; // @[util.scala:466:20]
reg [6:0] uops_2_prs2; // @[util.scala:466:20]
reg [6:0] uops_2_prs3; // @[util.scala:466:20]
reg [3:0] uops_2_ppred; // @[util.scala:466:20]
reg uops_2_prs1_busy; // @[util.scala:466:20]
reg uops_2_prs2_busy; // @[util.scala:466:20]
reg uops_2_prs3_busy; // @[util.scala:466:20]
reg uops_2_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20]
reg uops_2_exception; // @[util.scala:466:20]
reg [63:0] uops_2_exc_cause; // @[util.scala:466:20]
reg uops_2_bypassable; // @[util.scala:466:20]
reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_2_mem_size; // @[util.scala:466:20]
reg uops_2_mem_signed; // @[util.scala:466:20]
reg uops_2_is_fence; // @[util.scala:466:20]
reg uops_2_is_fencei; // @[util.scala:466:20]
reg uops_2_is_amo; // @[util.scala:466:20]
reg uops_2_uses_ldq; // @[util.scala:466:20]
reg uops_2_uses_stq; // @[util.scala:466:20]
reg uops_2_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_2_is_unique; // @[util.scala:466:20]
reg uops_2_flush_on_commit; // @[util.scala:466:20]
reg uops_2_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_2_ldst; // @[util.scala:466:20]
reg [5:0] uops_2_lrs1; // @[util.scala:466:20]
reg [5:0] uops_2_lrs2; // @[util.scala:466:20]
reg [5:0] uops_2_lrs3; // @[util.scala:466:20]
reg uops_2_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20]
reg uops_2_frs3_en; // @[util.scala:466:20]
reg uops_2_fp_val; // @[util.scala:466:20]
reg uops_2_fp_single; // @[util.scala:466:20]
reg uops_2_xcpt_pf_if; // @[util.scala:466:20]
reg uops_2_xcpt_ae_if; // @[util.scala:466:20]
reg uops_2_xcpt_ma_if; // @[util.scala:466:20]
reg uops_2_bp_debug_if; // @[util.scala:466:20]
reg uops_2_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_3_uopc; // @[util.scala:466:20]
reg [31:0] uops_3_inst; // @[util.scala:466:20]
reg [31:0] uops_3_debug_inst; // @[util.scala:466:20]
reg uops_3_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_3_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_3_iq_type; // @[util.scala:466:20]
reg [9:0] uops_3_fu_code; // @[util.scala:466:20]
reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_3_ctrl_is_load; // @[util.scala:466:20]
reg uops_3_ctrl_is_sta; // @[util.scala:466:20]
reg uops_3_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_3_iw_state; // @[util.scala:466:20]
reg uops_3_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_3_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_3_is_br; // @[util.scala:466:20]
reg uops_3_is_jalr; // @[util.scala:466:20]
reg uops_3_is_jal; // @[util.scala:466:20]
reg uops_3_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_3_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_3_br_tag; // @[util.scala:466:20]
reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20]
reg uops_3_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_3_pc_lob; // @[util.scala:466:20]
reg uops_3_taken; // @[util.scala:466:20]
reg [19:0] uops_3_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_3_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_3_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_3_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_3_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_3_pdst; // @[util.scala:466:20]
reg [6:0] uops_3_prs1; // @[util.scala:466:20]
reg [6:0] uops_3_prs2; // @[util.scala:466:20]
reg [6:0] uops_3_prs3; // @[util.scala:466:20]
reg [3:0] uops_3_ppred; // @[util.scala:466:20]
reg uops_3_prs1_busy; // @[util.scala:466:20]
reg uops_3_prs2_busy; // @[util.scala:466:20]
reg uops_3_prs3_busy; // @[util.scala:466:20]
reg uops_3_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20]
reg uops_3_exception; // @[util.scala:466:20]
reg [63:0] uops_3_exc_cause; // @[util.scala:466:20]
reg uops_3_bypassable; // @[util.scala:466:20]
reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_3_mem_size; // @[util.scala:466:20]
reg uops_3_mem_signed; // @[util.scala:466:20]
reg uops_3_is_fence; // @[util.scala:466:20]
reg uops_3_is_fencei; // @[util.scala:466:20]
reg uops_3_is_amo; // @[util.scala:466:20]
reg uops_3_uses_ldq; // @[util.scala:466:20]
reg uops_3_uses_stq; // @[util.scala:466:20]
reg uops_3_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_3_is_unique; // @[util.scala:466:20]
reg uops_3_flush_on_commit; // @[util.scala:466:20]
reg uops_3_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_3_ldst; // @[util.scala:466:20]
reg [5:0] uops_3_lrs1; // @[util.scala:466:20]
reg [5:0] uops_3_lrs2; // @[util.scala:466:20]
reg [5:0] uops_3_lrs3; // @[util.scala:466:20]
reg uops_3_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20]
reg uops_3_frs3_en; // @[util.scala:466:20]
reg uops_3_fp_val; // @[util.scala:466:20]
reg uops_3_fp_single; // @[util.scala:466:20]
reg uops_3_xcpt_pf_if; // @[util.scala:466:20]
reg uops_3_xcpt_ae_if; // @[util.scala:466:20]
reg uops_3_xcpt_ma_if; // @[util.scala:466:20]
reg uops_3_bp_debug_if; // @[util.scala:466:20]
reg uops_3_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_4_uopc; // @[util.scala:466:20]
reg [31:0] uops_4_inst; // @[util.scala:466:20]
reg [31:0] uops_4_debug_inst; // @[util.scala:466:20]
reg uops_4_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_4_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_4_iq_type; // @[util.scala:466:20]
reg [9:0] uops_4_fu_code; // @[util.scala:466:20]
reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_4_ctrl_is_load; // @[util.scala:466:20]
reg uops_4_ctrl_is_sta; // @[util.scala:466:20]
reg uops_4_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_4_iw_state; // @[util.scala:466:20]
reg uops_4_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_4_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_4_is_br; // @[util.scala:466:20]
reg uops_4_is_jalr; // @[util.scala:466:20]
reg uops_4_is_jal; // @[util.scala:466:20]
reg uops_4_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_4_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_4_br_tag; // @[util.scala:466:20]
reg [3:0] uops_4_ftq_idx; // @[util.scala:466:20]
reg uops_4_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_4_pc_lob; // @[util.scala:466:20]
reg uops_4_taken; // @[util.scala:466:20]
reg [19:0] uops_4_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_4_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_4_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_4_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_4_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_4_pdst; // @[util.scala:466:20]
reg [6:0] uops_4_prs1; // @[util.scala:466:20]
reg [6:0] uops_4_prs2; // @[util.scala:466:20]
reg [6:0] uops_4_prs3; // @[util.scala:466:20]
reg [3:0] uops_4_ppred; // @[util.scala:466:20]
reg uops_4_prs1_busy; // @[util.scala:466:20]
reg uops_4_prs2_busy; // @[util.scala:466:20]
reg uops_4_prs3_busy; // @[util.scala:466:20]
reg uops_4_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20]
reg uops_4_exception; // @[util.scala:466:20]
reg [63:0] uops_4_exc_cause; // @[util.scala:466:20]
reg uops_4_bypassable; // @[util.scala:466:20]
reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_4_mem_size; // @[util.scala:466:20]
reg uops_4_mem_signed; // @[util.scala:466:20]
reg uops_4_is_fence; // @[util.scala:466:20]
reg uops_4_is_fencei; // @[util.scala:466:20]
reg uops_4_is_amo; // @[util.scala:466:20]
reg uops_4_uses_ldq; // @[util.scala:466:20]
reg uops_4_uses_stq; // @[util.scala:466:20]
reg uops_4_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_4_is_unique; // @[util.scala:466:20]
reg uops_4_flush_on_commit; // @[util.scala:466:20]
reg uops_4_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_4_ldst; // @[util.scala:466:20]
reg [5:0] uops_4_lrs1; // @[util.scala:466:20]
reg [5:0] uops_4_lrs2; // @[util.scala:466:20]
reg [5:0] uops_4_lrs3; // @[util.scala:466:20]
reg uops_4_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20]
reg uops_4_frs3_en; // @[util.scala:466:20]
reg uops_4_fp_val; // @[util.scala:466:20]
reg uops_4_fp_single; // @[util.scala:466:20]
reg uops_4_xcpt_pf_if; // @[util.scala:466:20]
reg uops_4_xcpt_ae_if; // @[util.scala:466:20]
reg uops_4_xcpt_ma_if; // @[util.scala:466:20]
reg uops_4_bp_debug_if; // @[util.scala:466:20]
reg uops_4_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_5_uopc; // @[util.scala:466:20]
reg [31:0] uops_5_inst; // @[util.scala:466:20]
reg [31:0] uops_5_debug_inst; // @[util.scala:466:20]
reg uops_5_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_5_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_5_iq_type; // @[util.scala:466:20]
reg [9:0] uops_5_fu_code; // @[util.scala:466:20]
reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_5_ctrl_is_load; // @[util.scala:466:20]
reg uops_5_ctrl_is_sta; // @[util.scala:466:20]
reg uops_5_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_5_iw_state; // @[util.scala:466:20]
reg uops_5_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_5_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_5_is_br; // @[util.scala:466:20]
reg uops_5_is_jalr; // @[util.scala:466:20]
reg uops_5_is_jal; // @[util.scala:466:20]
reg uops_5_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_5_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_5_br_tag; // @[util.scala:466:20]
reg [3:0] uops_5_ftq_idx; // @[util.scala:466:20]
reg uops_5_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_5_pc_lob; // @[util.scala:466:20]
reg uops_5_taken; // @[util.scala:466:20]
reg [19:0] uops_5_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_5_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_5_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_5_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_5_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_5_pdst; // @[util.scala:466:20]
reg [6:0] uops_5_prs1; // @[util.scala:466:20]
reg [6:0] uops_5_prs2; // @[util.scala:466:20]
reg [6:0] uops_5_prs3; // @[util.scala:466:20]
reg [3:0] uops_5_ppred; // @[util.scala:466:20]
reg uops_5_prs1_busy; // @[util.scala:466:20]
reg uops_5_prs2_busy; // @[util.scala:466:20]
reg uops_5_prs3_busy; // @[util.scala:466:20]
reg uops_5_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20]
reg uops_5_exception; // @[util.scala:466:20]
reg [63:0] uops_5_exc_cause; // @[util.scala:466:20]
reg uops_5_bypassable; // @[util.scala:466:20]
reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_5_mem_size; // @[util.scala:466:20]
reg uops_5_mem_signed; // @[util.scala:466:20]
reg uops_5_is_fence; // @[util.scala:466:20]
reg uops_5_is_fencei; // @[util.scala:466:20]
reg uops_5_is_amo; // @[util.scala:466:20]
reg uops_5_uses_ldq; // @[util.scala:466:20]
reg uops_5_uses_stq; // @[util.scala:466:20]
reg uops_5_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_5_is_unique; // @[util.scala:466:20]
reg uops_5_flush_on_commit; // @[util.scala:466:20]
reg uops_5_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_5_ldst; // @[util.scala:466:20]
reg [5:0] uops_5_lrs1; // @[util.scala:466:20]
reg [5:0] uops_5_lrs2; // @[util.scala:466:20]
reg [5:0] uops_5_lrs3; // @[util.scala:466:20]
reg uops_5_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20]
reg uops_5_frs3_en; // @[util.scala:466:20]
reg uops_5_fp_val; // @[util.scala:466:20]
reg uops_5_fp_single; // @[util.scala:466:20]
reg uops_5_xcpt_pf_if; // @[util.scala:466:20]
reg uops_5_xcpt_ae_if; // @[util.scala:466:20]
reg uops_5_xcpt_ma_if; // @[util.scala:466:20]
reg uops_5_bp_debug_if; // @[util.scala:466:20]
reg uops_5_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_6_uopc; // @[util.scala:466:20]
reg [31:0] uops_6_inst; // @[util.scala:466:20]
reg [31:0] uops_6_debug_inst; // @[util.scala:466:20]
reg uops_6_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_6_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_6_iq_type; // @[util.scala:466:20]
reg [9:0] uops_6_fu_code; // @[util.scala:466:20]
reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_6_ctrl_is_load; // @[util.scala:466:20]
reg uops_6_ctrl_is_sta; // @[util.scala:466:20]
reg uops_6_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_6_iw_state; // @[util.scala:466:20]
reg uops_6_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_6_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_6_is_br; // @[util.scala:466:20]
reg uops_6_is_jalr; // @[util.scala:466:20]
reg uops_6_is_jal; // @[util.scala:466:20]
reg uops_6_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_6_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_6_br_tag; // @[util.scala:466:20]
reg [3:0] uops_6_ftq_idx; // @[util.scala:466:20]
reg uops_6_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_6_pc_lob; // @[util.scala:466:20]
reg uops_6_taken; // @[util.scala:466:20]
reg [19:0] uops_6_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_6_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_6_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_6_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_6_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_6_pdst; // @[util.scala:466:20]
reg [6:0] uops_6_prs1; // @[util.scala:466:20]
reg [6:0] uops_6_prs2; // @[util.scala:466:20]
reg [6:0] uops_6_prs3; // @[util.scala:466:20]
reg [3:0] uops_6_ppred; // @[util.scala:466:20]
reg uops_6_prs1_busy; // @[util.scala:466:20]
reg uops_6_prs2_busy; // @[util.scala:466:20]
reg uops_6_prs3_busy; // @[util.scala:466:20]
reg uops_6_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20]
reg uops_6_exception; // @[util.scala:466:20]
reg [63:0] uops_6_exc_cause; // @[util.scala:466:20]
reg uops_6_bypassable; // @[util.scala:466:20]
reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_6_mem_size; // @[util.scala:466:20]
reg uops_6_mem_signed; // @[util.scala:466:20]
reg uops_6_is_fence; // @[util.scala:466:20]
reg uops_6_is_fencei; // @[util.scala:466:20]
reg uops_6_is_amo; // @[util.scala:466:20]
reg uops_6_uses_ldq; // @[util.scala:466:20]
reg uops_6_uses_stq; // @[util.scala:466:20]
reg uops_6_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_6_is_unique; // @[util.scala:466:20]
reg uops_6_flush_on_commit; // @[util.scala:466:20]
reg uops_6_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_6_ldst; // @[util.scala:466:20]
reg [5:0] uops_6_lrs1; // @[util.scala:466:20]
reg [5:0] uops_6_lrs2; // @[util.scala:466:20]
reg [5:0] uops_6_lrs3; // @[util.scala:466:20]
reg uops_6_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20]
reg uops_6_frs3_en; // @[util.scala:466:20]
reg uops_6_fp_val; // @[util.scala:466:20]
reg uops_6_fp_single; // @[util.scala:466:20]
reg uops_6_xcpt_pf_if; // @[util.scala:466:20]
reg uops_6_xcpt_ae_if; // @[util.scala:466:20]
reg uops_6_xcpt_ma_if; // @[util.scala:466:20]
reg uops_6_bp_debug_if; // @[util.scala:466:20]
reg uops_6_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_7_uopc; // @[util.scala:466:20]
reg [31:0] uops_7_inst; // @[util.scala:466:20]
reg [31:0] uops_7_debug_inst; // @[util.scala:466:20]
reg uops_7_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_7_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_7_iq_type; // @[util.scala:466:20]
reg [9:0] uops_7_fu_code; // @[util.scala:466:20]
reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_7_ctrl_is_load; // @[util.scala:466:20]
reg uops_7_ctrl_is_sta; // @[util.scala:466:20]
reg uops_7_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_7_iw_state; // @[util.scala:466:20]
reg uops_7_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_7_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_7_is_br; // @[util.scala:466:20]
reg uops_7_is_jalr; // @[util.scala:466:20]
reg uops_7_is_jal; // @[util.scala:466:20]
reg uops_7_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_7_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_7_br_tag; // @[util.scala:466:20]
reg [3:0] uops_7_ftq_idx; // @[util.scala:466:20]
reg uops_7_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_7_pc_lob; // @[util.scala:466:20]
reg uops_7_taken; // @[util.scala:466:20]
reg [19:0] uops_7_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_7_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_7_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_7_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_7_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_7_pdst; // @[util.scala:466:20]
reg [6:0] uops_7_prs1; // @[util.scala:466:20]
reg [6:0] uops_7_prs2; // @[util.scala:466:20]
reg [6:0] uops_7_prs3; // @[util.scala:466:20]
reg [3:0] uops_7_ppred; // @[util.scala:466:20]
reg uops_7_prs1_busy; // @[util.scala:466:20]
reg uops_7_prs2_busy; // @[util.scala:466:20]
reg uops_7_prs3_busy; // @[util.scala:466:20]
reg uops_7_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20]
reg uops_7_exception; // @[util.scala:466:20]
reg [63:0] uops_7_exc_cause; // @[util.scala:466:20]
reg uops_7_bypassable; // @[util.scala:466:20]
reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_7_mem_size; // @[util.scala:466:20]
reg uops_7_mem_signed; // @[util.scala:466:20]
reg uops_7_is_fence; // @[util.scala:466:20]
reg uops_7_is_fencei; // @[util.scala:466:20]
reg uops_7_is_amo; // @[util.scala:466:20]
reg uops_7_uses_ldq; // @[util.scala:466:20]
reg uops_7_uses_stq; // @[util.scala:466:20]
reg uops_7_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_7_is_unique; // @[util.scala:466:20]
reg uops_7_flush_on_commit; // @[util.scala:466:20]
reg uops_7_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_7_ldst; // @[util.scala:466:20]
reg [5:0] uops_7_lrs1; // @[util.scala:466:20]
reg [5:0] uops_7_lrs2; // @[util.scala:466:20]
reg [5:0] uops_7_lrs3; // @[util.scala:466:20]
reg uops_7_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20]
reg uops_7_frs3_en; // @[util.scala:466:20]
reg uops_7_fp_val; // @[util.scala:466:20]
reg uops_7_fp_single; // @[util.scala:466:20]
reg uops_7_xcpt_pf_if; // @[util.scala:466:20]
reg uops_7_xcpt_ae_if; // @[util.scala:466:20]
reg uops_7_xcpt_ma_if; // @[util.scala:466:20]
reg uops_7_bp_debug_if; // @[util.scala:466:20]
reg uops_7_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_8_uopc; // @[util.scala:466:20]
reg [31:0] uops_8_inst; // @[util.scala:466:20]
reg [31:0] uops_8_debug_inst; // @[util.scala:466:20]
reg uops_8_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_8_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_8_iq_type; // @[util.scala:466:20]
reg [9:0] uops_8_fu_code; // @[util.scala:466:20]
reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_8_ctrl_is_load; // @[util.scala:466:20]
reg uops_8_ctrl_is_sta; // @[util.scala:466:20]
reg uops_8_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_8_iw_state; // @[util.scala:466:20]
reg uops_8_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_8_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_8_is_br; // @[util.scala:466:20]
reg uops_8_is_jalr; // @[util.scala:466:20]
reg uops_8_is_jal; // @[util.scala:466:20]
reg uops_8_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_8_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_8_br_tag; // @[util.scala:466:20]
reg [3:0] uops_8_ftq_idx; // @[util.scala:466:20]
reg uops_8_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_8_pc_lob; // @[util.scala:466:20]
reg uops_8_taken; // @[util.scala:466:20]
reg [19:0] uops_8_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_8_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_8_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_8_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_8_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_8_pdst; // @[util.scala:466:20]
reg [6:0] uops_8_prs1; // @[util.scala:466:20]
reg [6:0] uops_8_prs2; // @[util.scala:466:20]
reg [6:0] uops_8_prs3; // @[util.scala:466:20]
reg [3:0] uops_8_ppred; // @[util.scala:466:20]
reg uops_8_prs1_busy; // @[util.scala:466:20]
reg uops_8_prs2_busy; // @[util.scala:466:20]
reg uops_8_prs3_busy; // @[util.scala:466:20]
reg uops_8_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20]
reg uops_8_exception; // @[util.scala:466:20]
reg [63:0] uops_8_exc_cause; // @[util.scala:466:20]
reg uops_8_bypassable; // @[util.scala:466:20]
reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_8_mem_size; // @[util.scala:466:20]
reg uops_8_mem_signed; // @[util.scala:466:20]
reg uops_8_is_fence; // @[util.scala:466:20]
reg uops_8_is_fencei; // @[util.scala:466:20]
reg uops_8_is_amo; // @[util.scala:466:20]
reg uops_8_uses_ldq; // @[util.scala:466:20]
reg uops_8_uses_stq; // @[util.scala:466:20]
reg uops_8_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_8_is_unique; // @[util.scala:466:20]
reg uops_8_flush_on_commit; // @[util.scala:466:20]
reg uops_8_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_8_ldst; // @[util.scala:466:20]
reg [5:0] uops_8_lrs1; // @[util.scala:466:20]
reg [5:0] uops_8_lrs2; // @[util.scala:466:20]
reg [5:0] uops_8_lrs3; // @[util.scala:466:20]
reg uops_8_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20]
reg uops_8_frs3_en; // @[util.scala:466:20]
reg uops_8_fp_val; // @[util.scala:466:20]
reg uops_8_fp_single; // @[util.scala:466:20]
reg uops_8_xcpt_pf_if; // @[util.scala:466:20]
reg uops_8_xcpt_ae_if; // @[util.scala:466:20]
reg uops_8_xcpt_ma_if; // @[util.scala:466:20]
reg uops_8_bp_debug_if; // @[util.scala:466:20]
reg uops_8_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_9_uopc; // @[util.scala:466:20]
reg [31:0] uops_9_inst; // @[util.scala:466:20]
reg [31:0] uops_9_debug_inst; // @[util.scala:466:20]
reg uops_9_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_9_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_9_iq_type; // @[util.scala:466:20]
reg [9:0] uops_9_fu_code; // @[util.scala:466:20]
reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_9_ctrl_is_load; // @[util.scala:466:20]
reg uops_9_ctrl_is_sta; // @[util.scala:466:20]
reg uops_9_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_9_iw_state; // @[util.scala:466:20]
reg uops_9_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_9_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_9_is_br; // @[util.scala:466:20]
reg uops_9_is_jalr; // @[util.scala:466:20]
reg uops_9_is_jal; // @[util.scala:466:20]
reg uops_9_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_9_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_9_br_tag; // @[util.scala:466:20]
reg [3:0] uops_9_ftq_idx; // @[util.scala:466:20]
reg uops_9_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_9_pc_lob; // @[util.scala:466:20]
reg uops_9_taken; // @[util.scala:466:20]
reg [19:0] uops_9_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_9_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_9_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_9_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_9_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_9_pdst; // @[util.scala:466:20]
reg [6:0] uops_9_prs1; // @[util.scala:466:20]
reg [6:0] uops_9_prs2; // @[util.scala:466:20]
reg [6:0] uops_9_prs3; // @[util.scala:466:20]
reg [3:0] uops_9_ppred; // @[util.scala:466:20]
reg uops_9_prs1_busy; // @[util.scala:466:20]
reg uops_9_prs2_busy; // @[util.scala:466:20]
reg uops_9_prs3_busy; // @[util.scala:466:20]
reg uops_9_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20]
reg uops_9_exception; // @[util.scala:466:20]
reg [63:0] uops_9_exc_cause; // @[util.scala:466:20]
reg uops_9_bypassable; // @[util.scala:466:20]
reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_9_mem_size; // @[util.scala:466:20]
reg uops_9_mem_signed; // @[util.scala:466:20]
reg uops_9_is_fence; // @[util.scala:466:20]
reg uops_9_is_fencei; // @[util.scala:466:20]
reg uops_9_is_amo; // @[util.scala:466:20]
reg uops_9_uses_ldq; // @[util.scala:466:20]
reg uops_9_uses_stq; // @[util.scala:466:20]
reg uops_9_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_9_is_unique; // @[util.scala:466:20]
reg uops_9_flush_on_commit; // @[util.scala:466:20]
reg uops_9_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_9_ldst; // @[util.scala:466:20]
reg [5:0] uops_9_lrs1; // @[util.scala:466:20]
reg [5:0] uops_9_lrs2; // @[util.scala:466:20]
reg [5:0] uops_9_lrs3; // @[util.scala:466:20]
reg uops_9_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20]
reg uops_9_frs3_en; // @[util.scala:466:20]
reg uops_9_fp_val; // @[util.scala:466:20]
reg uops_9_fp_single; // @[util.scala:466:20]
reg uops_9_xcpt_pf_if; // @[util.scala:466:20]
reg uops_9_xcpt_ae_if; // @[util.scala:466:20]
reg uops_9_xcpt_ma_if; // @[util.scala:466:20]
reg uops_9_bp_debug_if; // @[util.scala:466:20]
reg uops_9_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_10_uopc; // @[util.scala:466:20]
reg [31:0] uops_10_inst; // @[util.scala:466:20]
reg [31:0] uops_10_debug_inst; // @[util.scala:466:20]
reg uops_10_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_10_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_10_iq_type; // @[util.scala:466:20]
reg [9:0] uops_10_fu_code; // @[util.scala:466:20]
reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_10_ctrl_is_load; // @[util.scala:466:20]
reg uops_10_ctrl_is_sta; // @[util.scala:466:20]
reg uops_10_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_10_iw_state; // @[util.scala:466:20]
reg uops_10_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_10_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_10_is_br; // @[util.scala:466:20]
reg uops_10_is_jalr; // @[util.scala:466:20]
reg uops_10_is_jal; // @[util.scala:466:20]
reg uops_10_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_10_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_10_br_tag; // @[util.scala:466:20]
reg [3:0] uops_10_ftq_idx; // @[util.scala:466:20]
reg uops_10_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_10_pc_lob; // @[util.scala:466:20]
reg uops_10_taken; // @[util.scala:466:20]
reg [19:0] uops_10_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_10_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_10_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_10_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_10_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_10_pdst; // @[util.scala:466:20]
reg [6:0] uops_10_prs1; // @[util.scala:466:20]
reg [6:0] uops_10_prs2; // @[util.scala:466:20]
reg [6:0] uops_10_prs3; // @[util.scala:466:20]
reg [3:0] uops_10_ppred; // @[util.scala:466:20]
reg uops_10_prs1_busy; // @[util.scala:466:20]
reg uops_10_prs2_busy; // @[util.scala:466:20]
reg uops_10_prs3_busy; // @[util.scala:466:20]
reg uops_10_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20]
reg uops_10_exception; // @[util.scala:466:20]
reg [63:0] uops_10_exc_cause; // @[util.scala:466:20]
reg uops_10_bypassable; // @[util.scala:466:20]
reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_10_mem_size; // @[util.scala:466:20]
reg uops_10_mem_signed; // @[util.scala:466:20]
reg uops_10_is_fence; // @[util.scala:466:20]
reg uops_10_is_fencei; // @[util.scala:466:20]
reg uops_10_is_amo; // @[util.scala:466:20]
reg uops_10_uses_ldq; // @[util.scala:466:20]
reg uops_10_uses_stq; // @[util.scala:466:20]
reg uops_10_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_10_is_unique; // @[util.scala:466:20]
reg uops_10_flush_on_commit; // @[util.scala:466:20]
reg uops_10_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_10_ldst; // @[util.scala:466:20]
reg [5:0] uops_10_lrs1; // @[util.scala:466:20]
reg [5:0] uops_10_lrs2; // @[util.scala:466:20]
reg [5:0] uops_10_lrs3; // @[util.scala:466:20]
reg uops_10_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20]
reg uops_10_frs3_en; // @[util.scala:466:20]
reg uops_10_fp_val; // @[util.scala:466:20]
reg uops_10_fp_single; // @[util.scala:466:20]
reg uops_10_xcpt_pf_if; // @[util.scala:466:20]
reg uops_10_xcpt_ae_if; // @[util.scala:466:20]
reg uops_10_xcpt_ma_if; // @[util.scala:466:20]
reg uops_10_bp_debug_if; // @[util.scala:466:20]
reg uops_10_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_11_uopc; // @[util.scala:466:20]
reg [31:0] uops_11_inst; // @[util.scala:466:20]
reg [31:0] uops_11_debug_inst; // @[util.scala:466:20]
reg uops_11_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_11_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_11_iq_type; // @[util.scala:466:20]
reg [9:0] uops_11_fu_code; // @[util.scala:466:20]
reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_11_ctrl_is_load; // @[util.scala:466:20]
reg uops_11_ctrl_is_sta; // @[util.scala:466:20]
reg uops_11_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_11_iw_state; // @[util.scala:466:20]
reg uops_11_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_11_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_11_is_br; // @[util.scala:466:20]
reg uops_11_is_jalr; // @[util.scala:466:20]
reg uops_11_is_jal; // @[util.scala:466:20]
reg uops_11_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_11_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_11_br_tag; // @[util.scala:466:20]
reg [3:0] uops_11_ftq_idx; // @[util.scala:466:20]
reg uops_11_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_11_pc_lob; // @[util.scala:466:20]
reg uops_11_taken; // @[util.scala:466:20]
reg [19:0] uops_11_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_11_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_11_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_11_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_11_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_11_pdst; // @[util.scala:466:20]
reg [6:0] uops_11_prs1; // @[util.scala:466:20]
reg [6:0] uops_11_prs2; // @[util.scala:466:20]
reg [6:0] uops_11_prs3; // @[util.scala:466:20]
reg [3:0] uops_11_ppred; // @[util.scala:466:20]
reg uops_11_prs1_busy; // @[util.scala:466:20]
reg uops_11_prs2_busy; // @[util.scala:466:20]
reg uops_11_prs3_busy; // @[util.scala:466:20]
reg uops_11_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20]
reg uops_11_exception; // @[util.scala:466:20]
reg [63:0] uops_11_exc_cause; // @[util.scala:466:20]
reg uops_11_bypassable; // @[util.scala:466:20]
reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_11_mem_size; // @[util.scala:466:20]
reg uops_11_mem_signed; // @[util.scala:466:20]
reg uops_11_is_fence; // @[util.scala:466:20]
reg uops_11_is_fencei; // @[util.scala:466:20]
reg uops_11_is_amo; // @[util.scala:466:20]
reg uops_11_uses_ldq; // @[util.scala:466:20]
reg uops_11_uses_stq; // @[util.scala:466:20]
reg uops_11_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_11_is_unique; // @[util.scala:466:20]
reg uops_11_flush_on_commit; // @[util.scala:466:20]
reg uops_11_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_11_ldst; // @[util.scala:466:20]
reg [5:0] uops_11_lrs1; // @[util.scala:466:20]
reg [5:0] uops_11_lrs2; // @[util.scala:466:20]
reg [5:0] uops_11_lrs3; // @[util.scala:466:20]
reg uops_11_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20]
reg uops_11_frs3_en; // @[util.scala:466:20]
reg uops_11_fp_val; // @[util.scala:466:20]
reg uops_11_fp_single; // @[util.scala:466:20]
reg uops_11_xcpt_pf_if; // @[util.scala:466:20]
reg uops_11_xcpt_ae_if; // @[util.scala:466:20]
reg uops_11_xcpt_ma_if; // @[util.scala:466:20]
reg uops_11_bp_debug_if; // @[util.scala:466:20]
reg uops_11_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_12_uopc; // @[util.scala:466:20]
reg [31:0] uops_12_inst; // @[util.scala:466:20]
reg [31:0] uops_12_debug_inst; // @[util.scala:466:20]
reg uops_12_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_12_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_12_iq_type; // @[util.scala:466:20]
reg [9:0] uops_12_fu_code; // @[util.scala:466:20]
reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_12_ctrl_is_load; // @[util.scala:466:20]
reg uops_12_ctrl_is_sta; // @[util.scala:466:20]
reg uops_12_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_12_iw_state; // @[util.scala:466:20]
reg uops_12_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_12_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_12_is_br; // @[util.scala:466:20]
reg uops_12_is_jalr; // @[util.scala:466:20]
reg uops_12_is_jal; // @[util.scala:466:20]
reg uops_12_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_12_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_12_br_tag; // @[util.scala:466:20]
reg [3:0] uops_12_ftq_idx; // @[util.scala:466:20]
reg uops_12_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_12_pc_lob; // @[util.scala:466:20]
reg uops_12_taken; // @[util.scala:466:20]
reg [19:0] uops_12_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_12_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_12_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_12_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_12_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_12_pdst; // @[util.scala:466:20]
reg [6:0] uops_12_prs1; // @[util.scala:466:20]
reg [6:0] uops_12_prs2; // @[util.scala:466:20]
reg [6:0] uops_12_prs3; // @[util.scala:466:20]
reg [3:0] uops_12_ppred; // @[util.scala:466:20]
reg uops_12_prs1_busy; // @[util.scala:466:20]
reg uops_12_prs2_busy; // @[util.scala:466:20]
reg uops_12_prs3_busy; // @[util.scala:466:20]
reg uops_12_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20]
reg uops_12_exception; // @[util.scala:466:20]
reg [63:0] uops_12_exc_cause; // @[util.scala:466:20]
reg uops_12_bypassable; // @[util.scala:466:20]
reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_12_mem_size; // @[util.scala:466:20]
reg uops_12_mem_signed; // @[util.scala:466:20]
reg uops_12_is_fence; // @[util.scala:466:20]
reg uops_12_is_fencei; // @[util.scala:466:20]
reg uops_12_is_amo; // @[util.scala:466:20]
reg uops_12_uses_ldq; // @[util.scala:466:20]
reg uops_12_uses_stq; // @[util.scala:466:20]
reg uops_12_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_12_is_unique; // @[util.scala:466:20]
reg uops_12_flush_on_commit; // @[util.scala:466:20]
reg uops_12_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_12_ldst; // @[util.scala:466:20]
reg [5:0] uops_12_lrs1; // @[util.scala:466:20]
reg [5:0] uops_12_lrs2; // @[util.scala:466:20]
reg [5:0] uops_12_lrs3; // @[util.scala:466:20]
reg uops_12_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20]
reg uops_12_frs3_en; // @[util.scala:466:20]
reg uops_12_fp_val; // @[util.scala:466:20]
reg uops_12_fp_single; // @[util.scala:466:20]
reg uops_12_xcpt_pf_if; // @[util.scala:466:20]
reg uops_12_xcpt_ae_if; // @[util.scala:466:20]
reg uops_12_xcpt_ma_if; // @[util.scala:466:20]
reg uops_12_bp_debug_if; // @[util.scala:466:20]
reg uops_12_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_13_uopc; // @[util.scala:466:20]
reg [31:0] uops_13_inst; // @[util.scala:466:20]
reg [31:0] uops_13_debug_inst; // @[util.scala:466:20]
reg uops_13_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_13_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_13_iq_type; // @[util.scala:466:20]
reg [9:0] uops_13_fu_code; // @[util.scala:466:20]
reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_13_ctrl_is_load; // @[util.scala:466:20]
reg uops_13_ctrl_is_sta; // @[util.scala:466:20]
reg uops_13_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_13_iw_state; // @[util.scala:466:20]
reg uops_13_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_13_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_13_is_br; // @[util.scala:466:20]
reg uops_13_is_jalr; // @[util.scala:466:20]
reg uops_13_is_jal; // @[util.scala:466:20]
reg uops_13_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_13_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_13_br_tag; // @[util.scala:466:20]
reg [3:0] uops_13_ftq_idx; // @[util.scala:466:20]
reg uops_13_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_13_pc_lob; // @[util.scala:466:20]
reg uops_13_taken; // @[util.scala:466:20]
reg [19:0] uops_13_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_13_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_13_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_13_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_13_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_13_pdst; // @[util.scala:466:20]
reg [6:0] uops_13_prs1; // @[util.scala:466:20]
reg [6:0] uops_13_prs2; // @[util.scala:466:20]
reg [6:0] uops_13_prs3; // @[util.scala:466:20]
reg [3:0] uops_13_ppred; // @[util.scala:466:20]
reg uops_13_prs1_busy; // @[util.scala:466:20]
reg uops_13_prs2_busy; // @[util.scala:466:20]
reg uops_13_prs3_busy; // @[util.scala:466:20]
reg uops_13_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20]
reg uops_13_exception; // @[util.scala:466:20]
reg [63:0] uops_13_exc_cause; // @[util.scala:466:20]
reg uops_13_bypassable; // @[util.scala:466:20]
reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_13_mem_size; // @[util.scala:466:20]
reg uops_13_mem_signed; // @[util.scala:466:20]
reg uops_13_is_fence; // @[util.scala:466:20]
reg uops_13_is_fencei; // @[util.scala:466:20]
reg uops_13_is_amo; // @[util.scala:466:20]
reg uops_13_uses_ldq; // @[util.scala:466:20]
reg uops_13_uses_stq; // @[util.scala:466:20]
reg uops_13_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_13_is_unique; // @[util.scala:466:20]
reg uops_13_flush_on_commit; // @[util.scala:466:20]
reg uops_13_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_13_ldst; // @[util.scala:466:20]
reg [5:0] uops_13_lrs1; // @[util.scala:466:20]
reg [5:0] uops_13_lrs2; // @[util.scala:466:20]
reg [5:0] uops_13_lrs3; // @[util.scala:466:20]
reg uops_13_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20]
reg uops_13_frs3_en; // @[util.scala:466:20]
reg uops_13_fp_val; // @[util.scala:466:20]
reg uops_13_fp_single; // @[util.scala:466:20]
reg uops_13_xcpt_pf_if; // @[util.scala:466:20]
reg uops_13_xcpt_ae_if; // @[util.scala:466:20]
reg uops_13_xcpt_ma_if; // @[util.scala:466:20]
reg uops_13_bp_debug_if; // @[util.scala:466:20]
reg uops_13_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_14_uopc; // @[util.scala:466:20]
reg [31:0] uops_14_inst; // @[util.scala:466:20]
reg [31:0] uops_14_debug_inst; // @[util.scala:466:20]
reg uops_14_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_14_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_14_iq_type; // @[util.scala:466:20]
reg [9:0] uops_14_fu_code; // @[util.scala:466:20]
reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_14_ctrl_is_load; // @[util.scala:466:20]
reg uops_14_ctrl_is_sta; // @[util.scala:466:20]
reg uops_14_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_14_iw_state; // @[util.scala:466:20]
reg uops_14_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_14_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_14_is_br; // @[util.scala:466:20]
reg uops_14_is_jalr; // @[util.scala:466:20]
reg uops_14_is_jal; // @[util.scala:466:20]
reg uops_14_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_14_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_14_br_tag; // @[util.scala:466:20]
reg [3:0] uops_14_ftq_idx; // @[util.scala:466:20]
reg uops_14_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_14_pc_lob; // @[util.scala:466:20]
reg uops_14_taken; // @[util.scala:466:20]
reg [19:0] uops_14_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_14_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_14_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_14_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_14_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_14_pdst; // @[util.scala:466:20]
reg [6:0] uops_14_prs1; // @[util.scala:466:20]
reg [6:0] uops_14_prs2; // @[util.scala:466:20]
reg [6:0] uops_14_prs3; // @[util.scala:466:20]
reg [3:0] uops_14_ppred; // @[util.scala:466:20]
reg uops_14_prs1_busy; // @[util.scala:466:20]
reg uops_14_prs2_busy; // @[util.scala:466:20]
reg uops_14_prs3_busy; // @[util.scala:466:20]
reg uops_14_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20]
reg uops_14_exception; // @[util.scala:466:20]
reg [63:0] uops_14_exc_cause; // @[util.scala:466:20]
reg uops_14_bypassable; // @[util.scala:466:20]
reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_14_mem_size; // @[util.scala:466:20]
reg uops_14_mem_signed; // @[util.scala:466:20]
reg uops_14_is_fence; // @[util.scala:466:20]
reg uops_14_is_fencei; // @[util.scala:466:20]
reg uops_14_is_amo; // @[util.scala:466:20]
reg uops_14_uses_ldq; // @[util.scala:466:20]
reg uops_14_uses_stq; // @[util.scala:466:20]
reg uops_14_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_14_is_unique; // @[util.scala:466:20]
reg uops_14_flush_on_commit; // @[util.scala:466:20]
reg uops_14_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_14_ldst; // @[util.scala:466:20]
reg [5:0] uops_14_lrs1; // @[util.scala:466:20]
reg [5:0] uops_14_lrs2; // @[util.scala:466:20]
reg [5:0] uops_14_lrs3; // @[util.scala:466:20]
reg uops_14_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20]
reg uops_14_frs3_en; // @[util.scala:466:20]
reg uops_14_fp_val; // @[util.scala:466:20]
reg uops_14_fp_single; // @[util.scala:466:20]
reg uops_14_xcpt_pf_if; // @[util.scala:466:20]
reg uops_14_xcpt_ae_if; // @[util.scala:466:20]
reg uops_14_xcpt_ma_if; // @[util.scala:466:20]
reg uops_14_bp_debug_if; // @[util.scala:466:20]
reg uops_14_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_15_uopc; // @[util.scala:466:20]
reg [31:0] uops_15_inst; // @[util.scala:466:20]
reg [31:0] uops_15_debug_inst; // @[util.scala:466:20]
reg uops_15_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_15_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_15_iq_type; // @[util.scala:466:20]
reg [9:0] uops_15_fu_code; // @[util.scala:466:20]
reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_15_ctrl_is_load; // @[util.scala:466:20]
reg uops_15_ctrl_is_sta; // @[util.scala:466:20]
reg uops_15_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_15_iw_state; // @[util.scala:466:20]
reg uops_15_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_15_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_15_is_br; // @[util.scala:466:20]
reg uops_15_is_jalr; // @[util.scala:466:20]
reg uops_15_is_jal; // @[util.scala:466:20]
reg uops_15_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_15_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_15_br_mask_T_1 = uops_15_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_15_br_tag; // @[util.scala:466:20]
reg [3:0] uops_15_ftq_idx; // @[util.scala:466:20]
reg uops_15_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_15_pc_lob; // @[util.scala:466:20]
reg uops_15_taken; // @[util.scala:466:20]
reg [19:0] uops_15_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_15_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_15_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_15_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_15_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_15_pdst; // @[util.scala:466:20]
reg [6:0] uops_15_prs1; // @[util.scala:466:20]
reg [6:0] uops_15_prs2; // @[util.scala:466:20]
reg [6:0] uops_15_prs3; // @[util.scala:466:20]
reg [3:0] uops_15_ppred; // @[util.scala:466:20]
reg uops_15_prs1_busy; // @[util.scala:466:20]
reg uops_15_prs2_busy; // @[util.scala:466:20]
reg uops_15_prs3_busy; // @[util.scala:466:20]
reg uops_15_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20]
reg uops_15_exception; // @[util.scala:466:20]
reg [63:0] uops_15_exc_cause; // @[util.scala:466:20]
reg uops_15_bypassable; // @[util.scala:466:20]
reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_15_mem_size; // @[util.scala:466:20]
reg uops_15_mem_signed; // @[util.scala:466:20]
reg uops_15_is_fence; // @[util.scala:466:20]
reg uops_15_is_fencei; // @[util.scala:466:20]
reg uops_15_is_amo; // @[util.scala:466:20]
reg uops_15_uses_ldq; // @[util.scala:466:20]
reg uops_15_uses_stq; // @[util.scala:466:20]
reg uops_15_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_15_is_unique; // @[util.scala:466:20]
reg uops_15_flush_on_commit; // @[util.scala:466:20]
reg uops_15_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_15_ldst; // @[util.scala:466:20]
reg [5:0] uops_15_lrs1; // @[util.scala:466:20]
reg [5:0] uops_15_lrs2; // @[util.scala:466:20]
reg [5:0] uops_15_lrs3; // @[util.scala:466:20]
reg uops_15_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20]
reg uops_15_frs3_en; // @[util.scala:466:20]
reg uops_15_fp_val; // @[util.scala:466:20]
reg uops_15_fp_single; // @[util.scala:466:20]
reg uops_15_xcpt_pf_if; // @[util.scala:466:20]
reg uops_15_xcpt_ae_if; // @[util.scala:466:20]
reg uops_15_xcpt_ma_if; // @[util.scala:466:20]
reg uops_15_bp_debug_if; // @[util.scala:466:20]
reg uops_15_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:470:27]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25]
wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24]
wire full; // @[util.scala:474:24]
assign full = _GEN; // @[util.scala:474:24]
wire _io_count_T; // @[util.scala:526:32]
assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35]
wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}]
wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}]
wire _valids_0_T_6 = _valids_0_T_3; // @[util.scala:481:{29,69}]
wire _valids_1_T_6 = _valids_1_T_3; // @[util.scala:481:{29,69}]
wire _valids_2_T_6 = _valids_2_T_3; // @[util.scala:481:{29,69}]
wire _valids_3_T_6 = _valids_3_T_3; // @[util.scala:481:{29,69}]
wire _valids_4_T_6 = _valids_4_T_3; // @[util.scala:481:{29,69}]
wire _valids_5_T_6 = _valids_5_T_3; // @[util.scala:481:{29,69}]
wire _valids_6_T_6 = _valids_6_T_3; // @[util.scala:481:{29,69}]
wire _valids_7_T_6 = _valids_7_T_3; // @[util.scala:481:{29,69}]
wire _valids_8_T_6 = _valids_8_T_3; // @[util.scala:481:{29,69}]
wire _valids_9_T_6 = _valids_9_T_3; // @[util.scala:481:{29,69}]
wire _valids_10_T_6 = _valids_10_T_3; // @[util.scala:481:{29,69}]
wire _valids_11_T_6 = _valids_11_T_3; // @[util.scala:481:{29,69}]
wire _valids_12_T_6 = _valids_12_T_3; // @[util.scala:481:{29,69}]
wire _valids_13_T_6 = _valids_13_T_3; // @[util.scala:481:{29,69}]
wire _valids_14_T_6 = _valids_14_T_3; // @[util.scala:481:{29,69}]
wire _valids_15_T_6 = _valids_15_T_3; // @[util.scala:481:{29,69}]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19]
assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17]
assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask; // @[util.scala:85:25, :506:17]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17]
assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17]
wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19]
assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][33:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19]
assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19]
assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19]
assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19]
assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19]
assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19]
assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19]
assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19]
assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19]
assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19]
assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30]
wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}]
wire _io_deq_valid_T_5 = _io_deq_valid_T_1; // @[util.scala:509:{40,65}]
assign _io_deq_valid_T_8 = _io_deq_valid_T_5; // @[util.scala:509:{65,108}]
assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108]
assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7]
wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40]
wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}]
assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}]
wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40]
wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40]
wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40]
wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40]
wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40]
wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40]
wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:448:7]
if (reset) begin // @[util.scala:448:7]
valids_0 <= 1'h0; // @[util.scala:465:24]
valids_1 <= 1'h0; // @[util.scala:465:24]
valids_2 <= 1'h0; // @[util.scala:465:24]
valids_3 <= 1'h0; // @[util.scala:465:24]
valids_4 <= 1'h0; // @[util.scala:465:24]
valids_5 <= 1'h0; // @[util.scala:465:24]
valids_6 <= 1'h0; // @[util.scala:465:24]
valids_7 <= 1'h0; // @[util.scala:465:24]
valids_8 <= 1'h0; // @[util.scala:465:24]
valids_9 <= 1'h0; // @[util.scala:465:24]
valids_10 <= 1'h0; // @[util.scala:465:24]
valids_11 <= 1'h0; // @[util.scala:465:24]
valids_12 <= 1'h0; // @[util.scala:465:24]
valids_13 <= 1'h0; // @[util.scala:465:24]
valids_14 <= 1'h0; // @[util.scala:465:24]
valids_15 <= 1'h0; // @[util.scala:465:24]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:470:27]
end
else begin // @[util.scala:448:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40]
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40]
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40]
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40]
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40]
valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40]
valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:475:24]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:476:24]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16]
maybe_full <= do_enq; // @[util.scala:470:27, :475:24]
end
if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33]
uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_0) // @[util.scala:465:24]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33]
uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_1) // @[util.scala:465:24]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33]
uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_2) // @[util.scala:465:24]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33]
uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_3) // @[util.scala:465:24]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33]
uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_4) // @[util.scala:465:24]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33]
uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_5) // @[util.scala:465:24]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33]
uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_6) // @[util.scala:465:24]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33]
uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_7) // @[util.scala:465:24]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33]
uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_8) // @[util.scala:465:24]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33]
uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_9) // @[util.scala:465:24]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33]
uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_10) // @[util.scala:465:24]
uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33]
uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_11) // @[util.scala:465:24]
uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33]
uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_12) // @[util.scala:465:24]
uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33]
uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_13) // @[util.scala:465:24]
uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33]
uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_14) // @[util.scala:465:24]
uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33]
uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_15) // @[util.scala:465:24]
uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20]
always @(posedge)
ram_16x131 ram_ext ( // @[util.scala:464:20]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:475:24]
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20]
); // @[util.scala:464:20]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7]
assign io_empty = io_empty_0; // @[util.scala:448:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_13( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_25 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_90( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_109( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_144( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_9( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1562 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1562; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1562; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1635 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1635; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1635; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1635; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1488 = _T_1562 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1488 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1488 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1488 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1488 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1488 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1534 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1534 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1503 = _T_1635 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1503 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1503 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1503 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1606 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1606 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1588 = _T_1635 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1588 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1588 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1588 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File PMP.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class PMPConfig extends Bundle {
val l = Bool()
val res = UInt(2.W)
val a = UInt(2.W)
val x = Bool()
val w = Bool()
val r = Bool()
}
object PMP {
def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp.cfg := reg.cfg
pmp.addr := reg.addr
pmp.mask := pmp.computeMask
pmp
}
}
class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
val cfg = new PMPConfig
val addr = UInt((paddrBits - PMP.lgAlign).W)
def reset(): Unit = {
cfg.a := 0.U
cfg.l := 0.U
}
def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U
Mux(napot, addr | (mask >> 1), ~(~addr | mask))
}
def napot = cfg.a(1)
def torNotNAPOT = cfg.a(0)
def tor = !napot && torNotNAPOT
def cfgLocked = cfg.l
def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor
}
class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(paddrBits.W)
import PMP._
def computeMask = {
val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)
Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)
}
private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U
if (lgMaxSize <= pmpGranularity.log2) {
eval(x, comparand, mask)
} else {
// break up the circuit; the MSB part will be CSE'd
val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)
val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
msbMatch && lsbMatch
}
}
private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
if (lgMaxSize <= pmpGranularity.log2) {
x < comparand
} else {
// break up the circuit; the MSB part will be CSE'd
val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U
val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)
msbsLess || (msbsEqual && lsbsLess)
}
}
private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
!boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)
private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
boundMatch(x, 0.U, lgMaxSize)
private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))
}
private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>
f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)
}
private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {
val beginsAfterLower = !(x < prev.comparand)
val beginsAfterUpper = !(x < comparand)
val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
}
// returns whether this PMP completely contains, or contains none of, a page
def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =
Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))
// returns whether this matching PMP fully contains the access
def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {
val lsbMask = UIntToOH1(lgSize, lgMaxSize)
val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U
val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U
val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)
val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U
Mux(napot, pow2Aligned, rangeAligned)
}
// returns whether this PMP matches at least one byte of the access
def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))
}
class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
def apply(addr: UInt, pgLevel: UInt): Bool = {
pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>
(h && pmp.homogeneous(addr, pgLevel, prev), pmp)
}._1
}
}
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
with HasCoreParameters {
override def desiredName = s"PMPChecker_s${lgMaxSize}"
val io = IO(new Bundle {
val prv = Input(UInt(PRV.SZ.W))
val pmp = Input(Vec(nPMPs, new PMP))
val addr = Input(UInt(paddrBits.W))
val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))
val r = Output(Bool())
val w = Output(Bool())
val x = Output(Bool())
})
val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U
val pmp0 = WireInit(0.U.asTypeOf(new PMP))
pmp0.cfg.r := default
pmp0.cfg.w := default
pmp0.cfg.x := default
val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty)
property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) {
property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access")
property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit")
}
val cur = WireInit(pmp)
cur.cfg.r := aligned && (pmp.cfg.r || ignore)
cur.cfg.w := aligned && (pmp.cfg.w || ignore)
cur.cfg.x := aligned && (pmp.cfg.x || ignore)
Mux(hit, cur, prev)
}
io.r := res.cfg.r
io.w := res.cfg.w
io.x := res.cfg.x
}
| module PMPChecker_s2_2( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire [4:0] _res_hit_T_10 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_36 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_62 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_88 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_114 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_140 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_166 = 5'hC; // @[package.scala:243:71]
wire [4:0] _res_hit_T_192 = 5'hC; // @[package.scala:243:71]
wire [1:0] _res_hit_T_12 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_38 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_64 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_90 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_116 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_142 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_168 = 2'h3; // @[package.scala:243:46]
wire [1:0] _res_hit_T_194 = 2'h3; // @[package.scala:243:46]
wire [31:0] _res_hit_T_196 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_197 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_T_195 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_198 = 32'h0; // @[PMP.scala:60:27]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire _res_hit_T_199 = 1'h0; // @[PMP.scala:77:9]
wire _res_hit_T_200 = 1'h1; // @[PMP.scala:88:5]
wire [1:0] io_size = 2'h2; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] _res_hit_T_11 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_37 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_63 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_89 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_115 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_141 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_167 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] _res_hit_T_193 = 2'h0; // @[package.scala:243:76]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_1; // @[PMP.scala:60:36]
assign _res_hit_T_1 = _GEN; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_19; // @[PMP.scala:60:36]
assign _res_hit_T_19 = _GEN; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_3 = {_res_hit_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_5 = io_addr_0 ^ _res_hit_T_4; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_6 = ~io_pmp_7_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_8 = _res_hit_T_7 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_9 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_13; // @[PMP.scala:60:36]
assign _res_hit_T_13 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_27; // @[PMP.scala:60:36]
assign _res_hit_T_27 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_45; // @[PMP.scala:60:36]
assign _res_hit_T_45 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_14 = ~_res_hit_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_15 = {_res_hit_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_16 = ~_res_hit_T_15; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_17 = io_addr_0 < _res_hit_T_16; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_18 = ~_res_hit_T_17; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_20 = ~_res_hit_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_21 = {_res_hit_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_22 = ~_res_hit_T_21; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_23 = io_addr_0 < _res_hit_T_22; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_24 = _res_hit_T_18 & _res_hit_T_23; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_9 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_8 : _res_hit_T_25; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18; // @[PMP.scala:177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22; // @[PMP.scala:178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27; // @[PMP.scala:177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31; // @[PMP.scala:178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36; // @[PMP.scala:177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40; // @[PMP.scala:178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = _res_cur_cfg_r_T; // @[PMP.scala:182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = _res_cur_cfg_w_T; // @[PMP.scala:183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = _res_cur_cfg_x_T; // @[PMP.scala:184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_28 = ~_res_hit_T_27; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_29 = {_res_hit_T_28[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_30 = ~_res_hit_T_29; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_31 = io_addr_0 ^ _res_hit_T_30; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_32 = ~io_pmp_6_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_33 = _res_hit_T_31 & _res_hit_T_32; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_34 = _res_hit_T_33 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_35 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_39; // @[PMP.scala:60:36]
assign _res_hit_T_39 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_53; // @[PMP.scala:60:36]
assign _res_hit_T_53 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_71; // @[PMP.scala:60:36]
assign _res_hit_T_71 = _GEN_5; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_40 = ~_res_hit_T_39; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_41 = {_res_hit_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_43 = io_addr_0 < _res_hit_T_42; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_47 = {_res_hit_T_46[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_48 = ~_res_hit_T_47; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_49 = io_addr_0 < _res_hit_T_48; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_50 = _res_hit_T_44 & _res_hit_T_49; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_35 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_26 ? _res_hit_T_34 : _res_hit_T_51; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63; // @[PMP.scala:177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67; // @[PMP.scala:178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72; // @[PMP.scala:177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76; // @[PMP.scala:178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81; // @[PMP.scala:177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85; // @[PMP.scala:178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = _res_cur_cfg_r_T_2; // @[PMP.scala:182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = _res_cur_cfg_w_T_2; // @[PMP.scala:183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = _res_cur_cfg_x_T_2; // @[PMP.scala:184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_54 = ~_res_hit_T_53; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_55 = {_res_hit_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_56 = ~_res_hit_T_55; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_57 = io_addr_0 ^ _res_hit_T_56; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_58 = ~io_pmp_5_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_59 = _res_hit_T_57 & _res_hit_T_58; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_60 = _res_hit_T_59 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_61 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_65; // @[PMP.scala:60:36]
assign _res_hit_T_65 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_79; // @[PMP.scala:60:36]
assign _res_hit_T_79 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_97; // @[PMP.scala:60:36]
assign _res_hit_T_97 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_66 = ~_res_hit_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_67 = {_res_hit_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_68 = ~_res_hit_T_67; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_69 = io_addr_0 < _res_hit_T_68; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_70 = ~_res_hit_T_69; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_72 = ~_res_hit_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_73 = {_res_hit_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_74 = ~_res_hit_T_73; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_75 = io_addr_0 < _res_hit_T_74; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_76 = _res_hit_T_70 & _res_hit_T_75; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_61 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_52 ? _res_hit_T_60 : _res_hit_T_77; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108; // @[PMP.scala:177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112; // @[PMP.scala:178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117; // @[PMP.scala:177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121; // @[PMP.scala:178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126; // @[PMP.scala:177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130; // @[PMP.scala:178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = _res_cur_cfg_r_T_4; // @[PMP.scala:182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = _res_cur_cfg_w_T_4; // @[PMP.scala:183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = _res_cur_cfg_x_T_4; // @[PMP.scala:184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_80 = ~_res_hit_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_81 = {_res_hit_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_82 = ~_res_hit_T_81; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_83 = io_addr_0 ^ _res_hit_T_82; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_84 = ~io_pmp_4_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_85 = _res_hit_T_83 & _res_hit_T_84; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_86 = _res_hit_T_85 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_87 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_91; // @[PMP.scala:60:36]
assign _res_hit_T_91 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_105; // @[PMP.scala:60:36]
assign _res_hit_T_105 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_123; // @[PMP.scala:60:36]
assign _res_hit_T_123 = _GEN_15; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_92 = ~_res_hit_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_93 = {_res_hit_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_94 = ~_res_hit_T_93; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_95 = io_addr_0 < _res_hit_T_94; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_99 = {_res_hit_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_101 = io_addr_0 < _res_hit_T_100; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_102 = _res_hit_T_96 & _res_hit_T_101; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_103 = _res_hit_T_87 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_78 ? _res_hit_T_86 : _res_hit_T_103; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153; // @[PMP.scala:177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157; // @[PMP.scala:178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162; // @[PMP.scala:177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166; // @[PMP.scala:178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171; // @[PMP.scala:177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175; // @[PMP.scala:178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = _res_cur_cfg_r_T_6; // @[PMP.scala:182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = _res_cur_cfg_w_T_6; // @[PMP.scala:183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = _res_cur_cfg_x_T_6; // @[PMP.scala:184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_104 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_106 = ~_res_hit_T_105; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_107 = {_res_hit_T_106[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_108 = ~_res_hit_T_107; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_109 = io_addr_0 ^ _res_hit_T_108; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_110 = ~io_pmp_3_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_111 = _res_hit_T_109 & _res_hit_T_110; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_112 = _res_hit_T_111 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_113 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_117; // @[PMP.scala:60:36]
assign _res_hit_T_117 = _GEN_20; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_131; // @[PMP.scala:60:36]
assign _res_hit_T_131 = _GEN_20; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_149; // @[PMP.scala:60:36]
assign _res_hit_T_149 = _GEN_20; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_118 = ~_res_hit_T_117; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_119 = {_res_hit_T_118[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_120 = ~_res_hit_T_119; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_121 = io_addr_0 < _res_hit_T_120; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_122 = ~_res_hit_T_121; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_124 = ~_res_hit_T_123; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_125 = {_res_hit_T_124[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_126 = ~_res_hit_T_125; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_127 = io_addr_0 < _res_hit_T_126; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_128 = _res_hit_T_122 & _res_hit_T_127; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_129 = _res_hit_T_113 & _res_hit_T_128; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_104 ? _res_hit_T_112 : _res_hit_T_129; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198; // @[PMP.scala:177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202; // @[PMP.scala:178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207; // @[PMP.scala:177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211; // @[PMP.scala:178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216; // @[PMP.scala:177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220; // @[PMP.scala:178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = _res_cur_cfg_r_T_8; // @[PMP.scala:182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = _res_cur_cfg_w_T_8; // @[PMP.scala:183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = _res_cur_cfg_x_T_8; // @[PMP.scala:184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_130 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_132 = ~_res_hit_T_131; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_133 = {_res_hit_T_132[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_134 = ~_res_hit_T_133; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_135 = io_addr_0 ^ _res_hit_T_134; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_136 = ~io_pmp_2_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_137 = _res_hit_T_135 & _res_hit_T_136; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_138 = _res_hit_T_137 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_139 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_143; // @[PMP.scala:60:36]
assign _res_hit_T_143 = _GEN_25; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_157; // @[PMP.scala:60:36]
assign _res_hit_T_157 = _GEN_25; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_175; // @[PMP.scala:60:36]
assign _res_hit_T_175 = _GEN_25; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_144 = ~_res_hit_T_143; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_145 = {_res_hit_T_144[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_146 = ~_res_hit_T_145; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_147 = io_addr_0 < _res_hit_T_146; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_148 = ~_res_hit_T_147; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_151 = {_res_hit_T_150[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_153 = io_addr_0 < _res_hit_T_152; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_154 = _res_hit_T_148 & _res_hit_T_153; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_155 = _res_hit_T_139 & _res_hit_T_154; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_130 ? _res_hit_T_138 : _res_hit_T_155; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243; // @[PMP.scala:177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247; // @[PMP.scala:178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252; // @[PMP.scala:177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256; // @[PMP.scala:178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261; // @[PMP.scala:177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265; // @[PMP.scala:178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = _res_cur_cfg_r_T_10; // @[PMP.scala:182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = _res_cur_cfg_w_T_10; // @[PMP.scala:183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = _res_cur_cfg_x_T_10; // @[PMP.scala:184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_156 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_158 = ~_res_hit_T_157; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_159 = {_res_hit_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_160 = ~_res_hit_T_159; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_161 = io_addr_0 ^ _res_hit_T_160; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_162 = ~io_pmp_1_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_163 = _res_hit_T_161 & _res_hit_T_162; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_164 = _res_hit_T_163 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_165 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_169; // @[PMP.scala:60:36]
assign _res_hit_T_169 = _GEN_30; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_183; // @[PMP.scala:60:36]
assign _res_hit_T_183 = _GEN_30; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_201; // @[PMP.scala:60:36]
assign _res_hit_T_201 = _GEN_30; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_170 = ~_res_hit_T_169; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_171 = {_res_hit_T_170[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_172 = ~_res_hit_T_171; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_173 = io_addr_0 < _res_hit_T_172; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_174 = ~_res_hit_T_173; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_176 = ~_res_hit_T_175; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_177 = {_res_hit_T_176[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_178 = ~_res_hit_T_177; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_179 = io_addr_0 < _res_hit_T_178; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_180 = _res_hit_T_174 & _res_hit_T_179; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_181 = _res_hit_T_165 & _res_hit_T_180; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_156 ? _res_hit_T_164 : _res_hit_T_181; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288; // @[PMP.scala:177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292; // @[PMP.scala:178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297; // @[PMP.scala:177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301; // @[PMP.scala:178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306; // @[PMP.scala:177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310; // @[PMP.scala:178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = _res_cur_cfg_r_T_12; // @[PMP.scala:182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = _res_cur_cfg_w_T_12; // @[PMP.scala:183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = _res_cur_cfg_x_T_12; // @[PMP.scala:184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_182 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_184 = ~_res_hit_T_183; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_185 = {_res_hit_T_184[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_186 = ~_res_hit_T_185; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_187 = io_addr_0 ^ _res_hit_T_186; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_188 = ~io_pmp_0_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_189 = _res_hit_T_187 & _res_hit_T_188; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_190 = _res_hit_T_189 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_191 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [31:0] _res_hit_T_202 = ~_res_hit_T_201; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_203 = {_res_hit_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_204 = ~_res_hit_T_203; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_205 = io_addr_0 < _res_hit_T_204; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_206 = _res_hit_T_205; // @[PMP.scala:77:9, :94:48]
wire _res_hit_T_207 = _res_hit_T_191 & _res_hit_T_206; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_182 ? _res_hit_T_190 : _res_hit_T_207; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333; // @[PMP.scala:177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337; // @[PMP.scala:178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342; // @[PMP.scala:177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346; // @[PMP.scala:178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351; // @[PMP.scala:177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355; // @[PMP.scala:178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = _res_cur_cfg_r_T_14; // @[PMP.scala:182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = _res_cur_cfg_w_T_14; // @[PMP.scala:183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = _res_cur_cfg_x_T_14; // @[PMP.scala:184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
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